EP0685857B1

EP0685857B1 - Inductor chip device

Info

Publication number: EP0685857B1
Application number: EP95303410A
Authority: EP
Inventors: David John Pedder
Original assignee: Mitel Semiconductor Ltd
Current assignee: Intarsia Corp
Priority date: 1994-06-03
Filing date: 1995-05-22
Publication date: 1999-09-08
Anticipated expiration: 2015-05-22
Also published as: GB9411107D0; DE69511940T2; JPH07335439A; ES2139841T3; GB2290171B; ATE184419T1; GB2290171A; EP0685857A1; DE69511940D1

Abstract

An inductor chip device for mounting on multichip-module, direct-chip-attach or surface-mount assemblies comprises a dielectric substrate (12), a spiral metallisation structure (14) defined on one major surface of the substrate, and a plurality of solder bumps (18, 19) defined on the other major surface of the substrate, the spiral structure being electrically connected to the plurality of solder bumps by means of metal-filled vias. Single or multilayer inductors may be defined, the latter providing higher inductance values in the same chip area. The multilayer inductors are constructed using a multilayer metal-polyimide or similar dielectric structure. The chip inductor provides a very small, accurate, discrete device with high inductance, high Q-factor and high self-resonant frequency. <IMAGE>

Description

The invention concerns an inductor chip device, and in particular, but not exclusively, an inductor chip device for mounting on a multichip module, a direct-chip-attach assembly, or a surface-mount assembly.
There is a growing requirement in the construction of very compact, low-cost radios and other RF communications circuits, for small, high-performance and cost-effective inductor components.
Surface-mountable chip inductors have recently become available that measure 2×1.25 mm in area (a standard surface-mount "0805" format), and that offer inductance values up to some 20 nH, with self-resonant frequencies of 1-2 GHz and quality (Q) factors that peak at about 80 at about half the self-resonant frequency.
Very compact inductors have also been realised in an integrated form within the upper metallisation layers of a multichip module substrate structure. Such inductors can provide inductance values between 1 and 100 nH within a 1mm square footprint, with self-resonant frequencies between 20 GHz and 500 MHz. Q-factor in these multichip-module inductors is determined by the inductor resistance at low frequencies, while the peak Q-factor is related to the nature and dielectric structure of the substrate employed. High-resistivity silicon substrates with inductors defined in an aluminium-polyimide multichip-module structure can provide Q-factors between about 5 and 20, depending upon the inductor structure and inductance value. The peak Q-factor occurs at a frequency between one-quarter and one-half the self-resonant frequency.
In accordance with the invention, there is provided an inductor chip device for mounting on a multichip module, on a direct-chip-attach assembly or on a surface-mount assembly, comprising a dielectric substrate, a spiral metallisation structure defined on one major surface of the substrate, and a plurality of solder bumps for effecting said mounting defined on the other major surface of the substrate, the spiral structure being electrically connected to the plurality of solder bumps by means of metal-filled vias.
Methods of making an inductor chip device according to the invention are disclosed in Claim 2, 3 and 5.
By arranging the inductor metallisation structure on one face of the substrate and the connections to the inductor structure on the opposite face, the capacitance of the inductor to ground is minimised and therefore the self-resonant frequency is maximised. Thus, where the closest ground structure in actual use of the inductor chip device, e.g. in a multichip-module assembly, is located on the plane of the solder bumps, the capacitance to ground will be determined essentially by the dielectric constant of the substrate and its thickness, a greater thickness giving a lower capacitance and a higher self-resonant frequency.
The use of solid, metal-filled through-vias to form the connections to the inductor structure minimises the resistance and inductance of the inductor feed structure, thereby maximising the Q-factor and self-resonant frequency of the inductor. This effect is further enhanced in that attachment of the inductor chip device to the next level of assembly is effected by flip-chip solder bonding, through the solder bumps.
The geometry of the inductor structure may be a circular, square, rectangular or polygonal spiral configuration. For mounting to a multichip-module assembly, a square format is to be preferred, whereas if the inductor device is to be mounted onto a direct-chip-attach or surface-mount device, a rectangular format is preferable.
The substrate may be either a pre-fired alumina or aluminium nitride substrate with vias formed by the laser-drilling of the substrate when in its pre-fired state and by the filling of the holes thereby produced by a copper-tungsten composite material produced by a liquid phase impregnation process. Alternatively, the substrate may be a co-fired alumina substrate, the vias being sintered tungsten or molybdenum vias formed in the substrate during co-firing.
The spiral structure may be a copper metallisation structure, and may be photolithographically defined. Use of copper for the metallisation minimises the series resistance of the inductor and therefore maximises the Q-factor. Defining the inductor geometry by means of a photolithographic patterning process enables very accurate inductor dimensions to be achieved, and ensures therefore a high reproducibility of inductance value from device to device.
The spiral metallisation structure may comprise a thin, metallic adhesion layer, a plating seed layer and a thick copper layer, deposited in that order on the substrate. The adhesion layer may be a chromium, titanium or nichrome adhesion layer, and the plating seed layer may be a copper plating seed layer.
The solder bumps are preferably formed on a multilayer metallisation structure comprising a chromium adhesion layer, a chromium-copper layer, and a copper or copper-plus-gold layer deposited in that order on the substrate.
The inductor chip device may include at least one further metallisation layer and dielectric layer, the spiral structure being defined in the metallisation layer formed on the major surface of the substrate and in the at least one further metallisation layer. The at least one further dielectric layer may be a polyimide layer.
The advantage of employing a multilayer structure is that the inductance value may be significantly increased. Thus, by providing a two-layer structure, an approximately fourfold increase (2 squared) in inductance per unit area may be achieved for a given number of turns, n.
At least one further solder bump may be included to ensure mechanical stability when the inductor device is mounted on a multichip-module device, etc. The minimum number of solder bump connections that is required is that number which effects the necessary electrical connections between the inductor structure and the multichip-module device, etc. The electrical connections may include not only end connections to the inductor, but also one or more tap connections inbetween. However, where the total number of electrical connections in the inductor chip device is insufficient to maintain mechanical stability when the chip device is mounted, extra non-electrical solder bump connections may be needed. The absolute minimum number of solder bump connections may therefore be said to be three, but four such connections would be a normal practical minimum.
An embodiment of the invention will now be described, by way of example only, with reference to the drawings, of which:
Figure 1 is a side view of an inductor chip device according to the invention, and
Figure 2 is a plan view corresponding to the side view of Figure 1.
Referring to Figures 1 and 2, one embodiment of an inductor chip device for mounting to a multichip-module assembly according to the invention is shown comprising an alumina substrate 12, on one major surface 13 of which is disposed a metallisation layer 14 configured as a square spiral. On the other major surface 15 is disposed a further metallisation layer 16 configured as a number of pads or islands, upon which are formed a corresponding number of solder bumps 17. The two ends 20, 21 of the spiral inductor structure are electrically connected to two of the solder bumps 17 through two metal-filled via structures 18 and 19, respectively. The two bumps to which the via structures 18, 19 are connected are shown as 22 and 23, respectively in Figure 2. In addition to the bumps 22, 23 there are additional bumps 24-26 which serve not to electrically connect the inductor to the multichip-module assembly (not shown), but to ensure a firm seating of the inductor chip on the assembly.
The inductor chip device is flip-chip solder-bonded to mating solder-bump, or other, structures on the multichip-module device.
The substrate 12 and metal-filled vias of the inductor chip device may be fabricated by a process such as that described in patent specification GB 2,226,707 in the name of Micro Substrates Inc. Thus, a high-density, polycrystalline alumina ceramic wafer with a well defined surface finish and a uniform thickness may be first processed to provide an array of narrow holes through the thickness of the wafer. This may be achieved by a laser drilling process, using a CO₂ or neodinium-YAG laser source, to produce narrow (∼ 125 µm diameter) holes which are slightly tapered from front to back. The disposition of the holes will follow the pattern shown in Figure 2.
The array of through wafer holes may then be filled with a conducting, metallic plug via structure using a copper-tungsten liquid-phase-impregnated composite structure. In this structure, the tungsten material is employed in a powder form in an organic binder and solvent carrier system and the via holes are filled with the tungsten powder "ink" by a screen-printing process, assisted by vacuum or applied pressure.
After hole-filling, any excess tungsten ink may be removed and the wafer fired in a partially oxidising atmosphere (for example, wet hydrogen) to burn off the organic binder and to partially sinter the remaining tungsten powder without the formation of tungsten oxides. A peak process temperature of 1400-1600 °C may be required for this process stage. A partially oxidising atmosphere is also important in this step to ensure good adhesion between the tungsten plug metallisation and the alumina ceramic. The resulting structure comprises a porous tungsten via in every laser-drilled through-via in the alumina wafer. A fully dense plug via structure may then be achieved by the infiltration of liquid copper into the porous tungsten via. The copper may be applied by the screen-printing of a copper "ink" material or by a similar process, followed by the heat treatment of the wafer to remove the binder, if one is employed, and then to melt the copper (typically in an hydrogen atmosphere at above 1083 °C). The liquid copper naturally wets the tungsten, particularly in the presence of certain trace element (surface) additives such as nickel, and thus fills the porous plug via structure to create a solid plug via on cooling to ambient temperature. Any excess material may then be removed by a final lapping and polishing operation that also provides the required surface finish and wafer thickness. Wafers may conveniently be produced at dimensions identical to those of silicon IC wafers, for example 100 mm diameter, 380 µm thickness or 150 mm diameter, 525 µm thickness, to facilitate processing. The use of a solid via structure greatly facilitates subsequent processing of the wafer since a polished, planar surface is provided that can be readily coated with resist, polyimide or other processing materials by IC-like spin-coating processes. A planar surface also aids low defectivity and low particulate levels in wafer processing.
Having obtained the ceramic substrate with its appropriately located metal-filled vias, the inductor structure is then defined on one face of the wafer. A thin metallic adhesion layer (using a reactive metal system such as chromium, titanium or nichrome) and a plating seed layer (in the form of a thin copper layer) are sputter-deposited onto the surface in succession. These layers are typically between 0.05 and 0.5 µm thick. The adhesion layer provides a strong bond to the alumina surface and also a good electrical connection to the copper-tungsten solid plug vias. The copper layer provides a compatible surface onto which to plate additional copper. A thick layer of a photoresist material is applied to this face of the wafer and patterned to define a spiral opening structure into which the copper metallisation that forms the inductor itself is then plated. The copper plating should be of the maximum thickness consistent with good control of the plated structure and small spacing between the inductor turns (for lowest resistance at a given inductor pitch and hence maximum Q-factor). The inductor geometry will be limited by the resolution and feature aspect ratios that can be defined in the resist, together with the properties of the plating solution (throwing power and plating efficiency). Materials exist that can allow at least 25 µm copper thicknesses at feature separations of as little as 10 µm. This should lead to inductor peak Q-factors of at least 100 in inductors of mm dimensions. After electroplating, the resist mask and the plating seed layer and adhesion layer are stripped by suitable solvent and etchant treatments from all surface areas apart from where the inductors are defined.
In order to protect the wafer from damage in subsequent process steps, the completed plated copper inductor structure is coated with a suitable passivation, e.g. a polyimide.
The wafer is then inverted and an array of solder bump structures are defined, some over the exposed copper-tungsten plug vias that make the connections between the inductor input and output points on the other face of the wafer, and some at other points on the surface, as will be explained below.
The solder bump structure requires a solderable metallisation layer to which the solder bump itself is wetted and which defines the area of the solder bump. Chromium-copper or chromium-copper-gold multilayer metallisation structures are suitable for this requirement. The first, chromium, layer provides adhesion and an ohmic connection to the underlying copper-tungsten plug via surface, while an alloyed chromium-copper layer follows which provides solderability without layer dissolution (for multiple solder bump melting operations). The final copper or copper-plus-gold layers provide initial solderability, these metals dissolving into the solder on bump reflow and reprecipitating on cooling as intermetallic compounds of tin. The gold, if employed, allows the solderable layer to be exposed to the atmosphere without oxidation prior to solder deposition. Solderable metallisation layers of this type may be defined by sequential vapour deposition through an etched metal foil or similar physical masking structure.
The solder itself is a tin-lead eutectic composition (63Sn-37Pb by weight, melting point 183 °C) for direct-chip-attach or surface-mount applications, or is a 95Pb-5Sn composition (melting point 310 °C) for multichip-module applications. The solder may be applied by electrodeposition using a seed layer and photoresist masking scheme similar to that described for the plating of the copper inductor structure on the first face of the wafer. Alternatively a physical masking structure may be employed with a vapour deposition process similar to that described for the solderable metallisation deposition. The solder may be deposited as separate layers of lead and tin, or as an alloy.
After deposition and patterning of the solderable metallisation and solder layers, the solder bumps are reflowed by heating to above the solder liquidus temperature under inert or reducing atmosphere conditions. Solder bump diameters close to those of the copper-tungsten plug vias are appropriate for the flip-chip inductor structure, i.e. 125 µm diameter. Bump heights between 30 and 100 µm are suitable, depending upon whether the inductor is to be used in a direct-chip-attach, surface-mount or multichip-module application. Such bump geometries are also typical for flip-chip solder-bonded integrated circuits for multichip-module and direct-chip-attach applications.
A total of five solder bumps are defined, two over the input and output plug via connections to the inductor, and a further three distributed across the alumina surface to provide mechanical support for the mounted flip-chip inductor.
As far as size of the inductor chip is concerned, preferred dimensions are 0.5, 1.0, 1.25, 1.5 or 2.0 mm square. This gives some consistency with the trend in discrete surface-mount component sizes, which are currently following a reduction from 0805 (2.0 × 1.25 mm) to 0603 (1.5 × 0.75 mm) to 0402 (1.0 × 0.5 mm).
After processing of the inductor and solder bump faces of the wafer, the temporary passivation layers which were employed to protect the inductor face are removed, the wafer is inspected and dimensional and electrical measurements are made to determine inductor yield and to ensure that the component characteristics are within the prescribed limits. Any defective inductors are identified, for example by ink marking, and the individual inductor components are separated by mechanical sawing or laser scribing.
In a second embodiment (not shown) of the inductor chip device according to the invention, a co-fired alumina substrate is used instead of a pre-fired substrate, the vias being then of sintered tungsten or molybdenum. The steps for obtaining the copper spiral metallisation and the solder bumps are as described for the first embodiment.
In a third embodiment (not shown) of the inductor chip device according to the invention, a multilayer inductor is formed in a pre-fired substrate by the plating of copper layers separated by a polyimide dielectric. Vias are defined through the interlayer polyimide material by dry etching, in order electrically to link the inductor spirals situated in the inner metallisation layers and that in the outer metallisation layer.
Dielectric materials other than polyimide may be used for the intermediate layer or layers, and means other than dry etching may be employed for defining the interlayer vias.
Although a total of five solder bumps are shown in Figure 2, more or less may be required, depending mainly on the size of the chip being produced. Also, there may be more than two solder bumps in electrical contact with the inductor metallisation structure. Thus, for instance, an inductor spiral may be tapped at some point or points along its length, or a multilayer inductor may be tapped at its interlayer junctions. These variations require an appropriate number of metal-filled vias to form the electrical connections, and correspondingly fewer solder bumps may then be required purely for maintaining mechanical stability.

Claims

An inductor chip device for mounting on a multichip module, on a direct-chip-attach assembly or on a surface-mount assembly, comprising a dielectric substrate (12), a spiral metallisation structure (14) defined on one major surface of the substrate, and a plurality of solder bumps (17) for effecting said mounting defined on the other major surface of the substrate, the spiral structure being electrically connected to the plurality of solder bumps by means of metal-filled vias (18, 19).
A method of making an inductor chip device according to Claim 1, in which the substrate is made by pre-firing an alumina or an aluminium nitride substrate on which vias are formed by laser-drilling of the substrate when in its pre-fired state and by filling the holes thereby produced by a copper-tungsten composite material produced by a liquid phase impregnation process.
A method of making an inductor chip device according to Claim 1, in which the substrate is made by co-firing an alumina substrate and in which the vias are sintered tungsten or molybdenum vias formed in the substrate during co-firing.
An inductor chip device according to Claim 1, in which the spiral structure is a copper metallisation structure.
A method of making an inductor chip device according to Claim 4, in which the spiral structure is made by a photolithographic process.
An inductor chip device according to Claim 4, in which the spiral metallisation structure comprises a thin, metallic adhesion layer, a plating seed layer and a thick copper layer, deposited in that order on the substrate.
An inductor chip device according to Claim 6, in which the adhesion layer is a chromium, titanium or nichrome adhesion layer, and the plating seed layer is a copper plating seed layer.
An inductor chip device according to Claims 1, 4, 6 or 7, in which the solder bumps are formed on a multilayer metallisation structure comprising a chromium adhesion layer, a chromium-copper layer, and a copper or copper-plus-gold layer deposited in that order on the substrate.
An inductor chip device according to Claims 1, 4, 6, 7 or 8, including at least one further metallisation layer and dielectric layer, the spiral structure being defined in the metallisation layer formed on the one major surface of the substrate and in the at least one further metallisation layer.
An inductor chip device according to Claim 9, in which the at least one further dielectric layer is a polyimide layer.
An inductor chip device according toClaims 1, 4, 6, 7, 8, 9 or 10, in which at least one further solder bump is included to ensure mechanical stability when the inductor device is mounted.