KR20030048691A - low value, low variation high frequency inductor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A high-frequency inductor and a manufacturing method thereof are provided to reduce the damage of a substrate by preventing a self-resonance frequency from decreasing due to a fidelity and a parasitic capacitor. CONSTITUTION: A interlayer insulating film(42) having a predetermined thickness is formed on a substrate(40). A contact hole(44) is formed on the interlayer insulating film(42) to expose the substrate(40). The contact hole(44) is filled with a conductive plug(46) used as the first inductor unit. A flip chip bump(48a) covering the whole front surface of the conductive plug(46) on the interlayer insulating film(42). The flip chip bump(48a) is used as the second inductor unit. An RF(Radio Frequency) chip(50) including an active device and a passive device is formed at predetermined intervals from a surface of the interlayer insulating film(42). The flip chip bump(48a) connects the conductive plug(46) and a pad of the RF chip(50) between the interlayer insulating film(42) and the RF chip(50).

Description

Low frequency, low variation high frequency inductor and method for manufacturing the same

The present invention relates to an inductor provided in an RF unit of a wireless communication terminal, and more particularly, to an inductor having a low inductance value and a small change in the value.

Current wireless communication terminals are not only smaller and lighter than earlier in development, but also have lower power consumption and product costs. However, reducing the overall size and power consumption of the wireless communication terminal and lowering the manufacturing cost, etc. are still a prerequisite for implementing a high quality wireless communication terminal.

In order to solve this problem, it is more effective to implement the high frequency part of the wireless communication terminal, that is, the RF terminal as one chip. Therefore, it is important to reduce the size of the electronic components constituting the RF stage, especially the inductor included in the chip, and it is also important to keep the high Q-factor and inductance of the inductor stable. .

In general, most of the inductors used in the RF stage are spiral inductors or bondwire inductors.

The spiral inductor is a spiral wound of a metal wire several times on a plane as shown in FIG. 1, one end of which is connected to the input terminal 10, and the other end of which is connected to the output terminal 12.

Referring to FIG. 2, a cross-sectional equivalent circuit of FIG. 1, a first parasitic capacitor 22 exists between a metal line 18 formed between an input terminal 10 and an output terminal 12 of an inductor, and the metal line 18 It can be seen that there is a second parasitic capacitor 24 between) and the substrate 20.

These parasitic capacitors lower the inductor's self-resonant frequency and lower its fidelity. In particular, when the substrate (not shown) is a silicon substrate, a substrate loss in which an input signal flowing into the input terminal 10 leaks to the substrate is increased.

On the other hand, an inductor composed of bond wires is an inductor using a wire used when packaging a bare chip (not shown) on the substrate, thereby making it possible to make an inductor having a high fidelity and a small value. Although there is an advantage in that it occupies a large area for the package, the total area of the RF chip is increased, and the shape and length of the wire may vary slightly depending on the process, and thus the value of inductance may vary slightly.

When an inductor with a small inductance is required, the influence of the inductance is small even though the change in inductance is small.

For example, the input impedance of a low noise amplifier of a wireless communication terminal is determined by the source inductor of the first transistor, and its value is required to decrease as the frequency increases. For example, in a low noise amplifier in a wireless LAN USII band (5.725-5.825 GHz), the source inductor needs about 0.5 nH, which is generally implemented as a bond wire. In this case, an error of about 0.1 nH may be generated due to a change in process. However, due to this error, input reflection is worse than 10 decibels (dB). This result is a big problem in the design of LNA.

Therefore, the technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, and has a small inductance value by preventing the fidelity due to substrate loss and the self-resonance frequency from being lowered due to parasitic capacitors. In addition, the present invention provides an inductor provided in the RF unit of a wireless communication terminal which can minimize the change of this value and greatly reduce the RF chip area.

Another object of the present invention is to provide a method of manufacturing the inductor.

1 is a plan view of a spiral inductor according to the prior art.

FIG. 2 is a cross-sectional equivalent circuit diagram of the inductor shown in FIG. 1.

3 is a cross-sectional view illustrating a cross section of an inductor provided in an RF unit of a wireless communication terminal according to a first embodiment of the present invention.

4 shows a part of the inductor shown in FIG. 3 and an equivalent circuit thereof.

5 to 8 are cross-sectional views illustrating cross-sections of inductors provided in the RF unit of the wireless communication terminal according to the second to fifth embodiments of the present invention.

9 to 13 are cross-sectional views showing step by step an inductor manufacturing method according to a first embodiment of the present invention.

14 to 17 are cross-sectional views illustrating a method of manufacturing an inductor according to a second exemplary embodiment of the present invention.

18 to 22 are cross-sectional views showing step by step an inductor manufacturing method according to a third embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40: substrate 42: interlayer dielectric film having a low loss

44, 44a: contact hole 46: conductive plug

48, 54: member for forming flip chip bump

48a, 54a: flip chip bump 50: RF chip

52: bonding layer 56, 58: conductive adhesive film

60: pad area of RF chip

In order to achieve the above technical problem, the present invention is a first inductor means which is provided to electrically connect the RF chip provided on the substrate at a predetermined distance from the substrate surrounded by a low loss dielectric material; And a second inductor means for connecting the first inductor means and the RF chip to provide the inductor provided in the RF unit of the wireless communication terminal.

The first inductor means is a conductive plug and the second inductor means is a flip chip bump in contact with the other end of the conductive plug.

The conductive plug is connected to the substrate via third inductor means.

A conductive adhesive film is further provided between the third inductor means and the substrate and / or between the flip chip bump and the conductive plug.

In order to achieve the above object, the present invention provides a first step of forming a low loss interlayer dielectric film on a substrate, and a first inductor means connected to the substrate through the interlayer dielectric film in the interlayer dielectric film. And a third step of forming an RF chip on the interlayer dielectric layer at predetermined intervals, the second inductor means being formed through the second inductor means connected to the pad region of the RF chip. It provides a method of manufacturing an inductor, characterized in that.

The second step may further include forming a contact hole in which the substrate is exposed in the interlayer dielectric layer, and filling the contact hole with a conductive plug by the first inductor means.

The third step may include forming bumps for flip chip bonding on a pad region of the RF chip, aligning the RF chips so that the bumps correspond one-to-one with the conductive plugs, and at a predetermined temperature and pressure. Bonding the substrate and the RF chip to bond the both.

According to another embodiment of the present invention, the third step may include forming a bump on the interlayer dielectric layer to be in contact with the conductive plug, wherein the pad region of the RF chip corresponds one-to-one with the bump. Aligning and flip chip bonding the substrate and the RF chip by pressing the substrate and the RF chip at a predetermined temperature and pressure.

In order to achieve the above object, the present invention provides a first step of forming a low loss interlayer dielectric film including a first inductor means therethrough, and a second inductor means for connecting the substrate and the first inductor means. A second step of locating the interlayer dielectric film over the substrate at a predetermined distance; and placing an RF chip at a predetermined distance over the interlayer dielectric film, wherein the first inductor means and the pad region of the RF chip are connected. And a third step of positioning via the third inductor means.

The first step includes forming the interlayer dielectric film on a first substrate, forming a contact hole in the interlayer dielectric film to expose the first substrate, and conducting conductive material in the contact hole as the first inductor means. Filling a plug and separating the interlayer dielectric film from the first substrate.

The second and third inductor means are flip chip bumps.

The second step may include forming the flip chip bumps on the substrate in consideration of the spacing and the area of the pad area of the RF chip, and aligning the interlayer dielectric layers such that the conductive plugs and the flip chip bumps are in one-to-one correspondence. And chip bonding the substrate and the interlayer dielectric layer at a predetermined temperature and pressure to flip chip bond.

On the other hand, according to another embodiment of the present invention, the step of forming a flip chip bump in contact with the conductive plug on one surface of the interlayer dielectric film, and the substrate and the interlayer dielectric film at a predetermined temperature and pressure Bonding and bonding.

The third step may include forming the flip chip bump on the RF chip pad region, aligning the RF chip so that the flip chip bump and the conductive plug correspond one-to-one, and at a predetermined temperature and pressure. And bonding the RF chip and the interlayer dielectric layer to each other.

A conductive adhesive film is formed on the substrate or the interlayer dielectric film before flip chip bonding the substrate and the interlayer dielectric film or before flip chip bonding the interlayer dielectric film and the RF chip.

By using the present invention, since the substrate loss is minimized, high fidelity can be obtained and the self resonance frequency can be increased. In addition, it is possible to minimize the change of the inductor value by excellent reproducibility of the inductor according to the iterative process. In addition, the size of the entire chip can be reduced by applying flip chip bonding.

Hereinafter, an inductor provided in an RF unit of a wireless communication terminal according to an embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, the inductor provided in the RF unit of the wireless communication terminal will be described.

<First Embodiment>

Referring to FIG. 3, an interlayer dielectric film 42 having a predetermined thickness is formed on the substrate 40. The substrate 40 may be a printed circuit board (PCB), a ceramic substrate, a glass substrate, a silicon substrate, or the like, but other substrates capable of packaging may be used. The interlayer dielectric film 42 is preferably small in dielectric constant and conductivity and has a small loss tangent. A contact hole 44 through which the substrate 40 is exposed is formed in the interlayer dielectric film 42, and the contact hole 44 is filled with the conductive plug 46. The conductive plug 46 is used as the first inductor means. Flip chip bumps 48a are formed on the interlayer dielectric film 42 to cover the entire upper surface of the conductive plug 46. Flip chip bump 48a is used as the second inductor means. An RF chip 50 including an active device, a passive device, and the like is provided at a predetermined distance from the surface of the interlayer dielectric film 42. The RF chip 50 is supported by flip chip bumps 48a in contact with their pads (not shown). As a result, the flip chip bump 48a serves to connect the pads of the conductive plug 46 and the RF chip 50 between the interlayer dielectric film 42 and the RF chip 50.

The conductive plug 46 used as the first inductor means and the flip chip bump 48a used as the second inductor means include not only an inductor component but also a resistor component and a capacitor component. This fact is further clarified by referring to Fig. 4 in which the conductive plug 46 and the flip chip bumps 48a are shown as equivalent circuits.

In the equivalent circuit of FIG. 4, the first resistor R1 and the first inductor L1 are due to the flip chip bumps 48a and the second resistor R2 and the second inductor L2 configured in parallel with the capacitor C. ) Is due to the conductive plug 46 filled in the contact hole 44. The capacitor C represents a capacitor composed of the conductive plug 46, the substrate 40, and the interlayer dielectric film 42.

Second Embodiment

Referring to FIG. 5, the conductive adhesive film 52 and the interlayer dielectric film 42 are sequentially formed on the substrate 40. The conductive adhesive film 52 is for enhancing the adhesion between the substrate 40 and the interlayer dielectric film 42. In the conductive adhesive film 52 and the interlayer dielectric film 42, a contact hole 44 exposing a predetermined region of the substrate 40 is formed, and the contact hole 44 is filled with the conductive plug 46. The exposed front surface of the conductive plug 46 on the dielectric film 42 is in contact with the flip chip bump 48a. The upper portion of the flip chip bump 48a is in contact with the pad region of the RF chip 50. Due to the flip chip bumps 48a, the RF chip 50 and the interlayer dielectric layer 42 are spaced apart by a distance corresponding to the height of the flip chip bumps 48a.

Third Embodiment

Flip chip bumps are provided above and below the interlayer dielectric film.

Specifically, referring to FIG. 6, a first flip chip bump 54a is formed on the substrate 40. An interlayer dielectric film 42 is formed on the substrate 40 with the first flip chip bumps 54a as a support. A contact hole 44 through which the first flip chip bumps 54a are exposed is formed in the interlayer dielectric film 42. The contact hole 44 is filled with the conductive plug 46. A flip chip bump 48a is formed in the interlayer dielectric film 42 in contact with the conductive plug 46. The RF chip 50 is provided above the interlayer dielectric film 42 with the flip chip bumps 48a supported.

In the third embodiment, the first flip chip bump 54a is used as another inductor means together with the conductive plug 46 and the flip chip bump 48a.

Fourth Example

As shown in FIG. 7, a conductive adhesive film 56 is formed between the interlayer dielectric film 42 and the flip chip bumps 48a to cover the exposed front surface of the conductive plug 46 and the front surface of the interlayer dielectric film 42. It is. At this time, the conductive adhesive film 56 is an anisotropic conductive adhesive film (Isotripic Conductive Adhesive film), non-conductive adhesive film (Non Conductive) in which the electrical resistance is lowered in the direction of pressure Adhesive layer). In other words, the portion 56a pressed by the flip chip bump 48a in the conductive adhesive film 56 has a lower electrical resistance than the other portion 56b so that the electrical signal is transferred from the flip chip bump 48a to the conductive plug 46. Only delivered.

Fifth Embodiment

As shown in FIG. 8, the conductive adhesive film 58 is provided between the substrate 40 and the first flip chip bumps 54a in the third embodiment. In this case, the conductive adhesive film 58 is preferably the same as the conductive adhesive film 56 of the fourth embodiment shown in FIG.

Next, a method of manufacturing an inductor used in an RF unit of a wireless communication terminal according to the embodiments of the present invention described above will be described.

<First Embodiment>

First, as shown in FIG. 9, an interlayer dielectric film 42 is formed on a substrate 40. The substrate 40 is preferably formed of a printed circuit board (PCB), a ceramic substrate, a glass substrate, a silicon substrate, or the like, but may be formed of another substrate which can be packaged. The interlayer dielectric film 42 is preferably formed of a dielectric film having a low dielectric loss.

Subsequently, as shown in FIG. 10, a contact hole 44 through which the substrate 40 is exposed is formed in the interlayer dielectric film 42. This contact hole 44 is filled with the conductive plug 46 (FIG. 11). In this process, the surface of the resultant is planarized. The conductive plug 46 is used as the first inductor means.

Meanwhile, as illustrated in FIG. 12, bump members 48 for flip chip bonding are formed on the pad region 60 of the RF chip 50 including a transmitter and a receiver configured of active and passive elements. After inverting the RF chip 50, the bump members 48 and the conductive plugs 46 are aligned in a one-to-one correspondence, and flip chip bonding of the RF chip 50 to the substrate 40 is illustrated in FIG. 13. . In this way, the inductor according to the first embodiment is formed. In this process, the bump member 48 is melted under a predetermined temperature and pressure to form a flip chip bump 48a between the pad region 60 of the RF chip 50 and the conductive plug 46. Flip chip bump 48a is used as the second inductor means. In this way, an inductor having a small inductance necessary for the input / output terminal of the RF chip 50 is formed.

As described above, since the bump member 48 and the conductive plug 46 correspond one-to-one, when forming the contact hole 44, the spacing and diameter of the contact hole 44 are determined by the pad region of the RF chip 50. It is preferable to consider and set the space | interval of 60 and the magnitude | size of the bump member 48.

On the other hand, the bump member 48 is formed on the interlayer dielectric film 42 so as to be in contact with the conductive plug 46, and then the pad region 60 of the RF chip 50 is one-to-one with the bump member 48. Correspondingly, the RF chip 50 may be aligned, and then the RF chip 50 and the substrate 40 may be compressed at a predetermined temperature and pressure to bond the two.

Second Embodiment

14 to 17, the conductive adhesive film 52 and the interlayer dielectric film 42 are sequentially formed on the substrate 40 (FIG. 14). The conductive adhesive film 52 is a material layer for increasing adhesion between the interlayer dielectric film 42 and the substrate and may be electrically connected to the wiring of the substrate. A contact hole 44a through which the substrate 40 is exposed is formed in the conductive adhesive film 52 and the interlayer dielectric film 42 (FIG. 15). The contact hole 44a is filled with the conductive plug 46, and the surface of the resultant is flat (Fig. 16). Subsequent steps shown in FIG. 17 proceed in the same manner as in the first embodiment. In this way, the inductor according to the second embodiment shown in FIG. 5 is formed.

Third Embodiment

18 to 22, an interlayer dielectric film 42 is formed on the substrate 62. A contact hole 44 through which the substrate 62 is exposed is formed in the interlayer dielectric film 42. The conductive plug 46 is filled in the contact hole 44. The surface of the resultant filled conductive plug 46 is planarized. Thereafter, as shown in FIG. 19, the interlayer dielectric film 42 filled with the contact plug 44 with the conductive plug 46 is separated from the substrate 62. On one surface of the separated interlayer dielectric film 42, a bump member 54 is formed which is in contact with the conductive plug 46, preferably covering the entire surface of the conductive plug 46 (FIG. 20). The surface on which the bump member 54 of the interlayer dielectric film 42 is formed is faced toward the substrate 40 and the both are bonded using the bump 54. In this process, the bump member 54 is subjected to a predetermined temperature and pressure, and as a result, a first flip chip bump 54a is formed between the substrate 40 and the interlayer dielectric film 42 (FIG. 21). The flip chip bonding process of the RF chip 50 on the substrate 40 and the flip chip bonded interlayer dielectric film 42 proceeds as in the first embodiment. In this way, the inductor according to the third embodiment of the present invention shown in FIG. 6 is formed. In this case, the inductor consists of two flip chip bumps 48a and 54a and a conductive plug 46 connecting them.

Although not shown in the drawings, the method of manufacturing the inductors according to the fourth and fifth embodiments shown in FIGS. 7 and 8 respectively includes the interlayer including the conductive plugs 46 in the method of manufacturing the inductors according to the first embodiment. Forming a conductive adhesive film 56 between the dielectric film 42 and the flip chip bumps 48a, and between the substrate 40 and the flip chip bumps 54a in the inductor manufacturing method according to the third embodiment. It is characterized by including the process of forming the electroconductive adhesive film 58 in the.

On the other hand, in the inductor manufacturing method according to the fifth embodiment, a conductive adhesive film is formed on the exposed front surface of the interlayer dielectric film 42 and the conductive plug 46, and then flip chip bumps 48a are formed on the conductive adhesive film. There may be a method of forming the RF chip 50 through.

Further, in the inductor manufacturing method according to the second embodiment including the process of forming the conductive adhesive film, a conductive adhesive film is formed on the exposed front surface of the interlayer dielectric film 42 and the conductive plug 46 and then flips on the conductive adhesive film. There may be further a method of forming the RF chip 50 through the chip bump 48a.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may develop a novel flip chip bump forming process and apply it to the inductor manufacturing method according to the embodiment of the present invention. It may be formed of a plurality of dielectric film films as low as possible. In addition, the shape of the contact hole 44 may be variously changed. For example, instead of a constant diameter contact hole as described in the embodiment of the present invention, it may be provided with a stepped contact hole having a diameter partially or sequentially and filled with a conductive plug as an inductor element. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, since the conductive plug, which is one of the elements constituting the inductor, is surrounded by a dielectric layer having a low dielectric constant and low conductivity and a small loss angle, the substrate loss is minimized. As a result, high fidelity can be obtained. In addition, since the capacitance of the parasitic capacitor is extremely small, a high self resonant frequency can be obtained. In addition, since a conductive plug having a short length with a flip chip bump can be formed with high reproducibility using a semiconductor manufacturing process, an inductor having a small inductance desired and minimizing a change in its value can be obtained. In addition, since flip chip bonding is used, the chip size can be reduced by 70% or more compared with the case of using wire bonding.

Claims (25)

First inductor means arranged to electrically connect an RF chip provided on the substrate with the substrate at a predetermined distance from the substrate, the first inductor means being surrounded by a low loss dielectric material; And And a second inductor means for connecting the first inductor means and the RF chip. 2. The inductor of claim 1, wherein the first inductor means has a conductive plug having one end connected to the substrate and the other end connected to the second inductor means. 3. The inductor of claim 2, wherein the second inductor means is a flip chip bump in contact with the other end of the conductive plug. 4. The inductor of claim 3, further comprising a conductive adhesive film surrounding the conductive plug between the low loss dielectric material and the substrate. 4. The inductor of claim 3, wherein the conductive plug is connected to the substrate through a third inductor means. 6. The inductor of claim 5, further comprising a conductive adhesive film between the third inductor means and the substrate. The inductor of claim 6, further comprising a conductive adhesive layer between the flip chip bump and the conductive plug. 7. The inductor of claim 5 or 6, wherein the third inductor means is a flip chip bump. 4. The inductor of claim 3, further comprising a conductive adhesive film between the flip chip bump and the conductive plug. The inductor of claim 4, wherein a conductive adhesive film is further provided between the conductive plug and the flip chip bumps. Forming a low loss interlayer dielectric film on the substrate; Forming a first inductor means in the interlayer dielectric film to pass through the interlayer dielectric film and to be connected to the substrate; And And forming an RF chip on the interlayer dielectric film at predetermined intervals, and forming the RF chip through the first inductor means and the second inductor means connected to the pad region of the RF chip. Inductor manufacturing method. 12. The method of claim 11, wherein the second step comprises: forming a contact hole in the interlayer dielectric film to expose the substrate; And And filling a conductive plug in said contact hole with said first inductor means. The method of claim 12, wherein the third step comprises: forming bumps for flip chip bonding on a pad region of the RF chip; Aligning the RF chip such that the bumps correspond one-to-one with the conductive plugs; And Bonding the substrate and the RF chip at a predetermined temperature and pressure to bond both of the substrate and the RF chip. 13. The method of claim 12, wherein the third step comprises: forming a bump on the interlayer dielectric film to contact the conductive plug; Aligning the RF chip so that a pad area of the RF chip corresponds one-to-one with the bump; And And crimping the substrate and the RF chip at a predetermined temperature and pressure to flip chip bond them both. 15. The method of manufacturing the inductor according to claim 13 or 14, wherein a conductive adhesive film is first formed before forming the interlayer dielectric film. The method of claim 13, further comprising forming a conductive adhesive film covering the exposed surface of the conductive plug on the interlayer dielectric film before pressing the substrate and the RF chip. A first step of forming a low dielectric constant interlayer dielectric film comprising first inductor means therethrough; A second step of placing the interlayer dielectric film over a predetermined distance on the substrate via a second inductor means connecting the substrate and the first inductor means; And And positioning a RF chip on the interlayer dielectric film at a predetermined distance, and positioning the RF chip through a third inductor means connecting the first inductor means and a pad region of the RF chip. Inductor manufacturing method. 18. The method of claim 17, wherein the first step comprises: forming the interlayer dielectric film on a first substrate; Forming a contact hole in the interlayer dielectric layer to expose the first substrate; Filling a conductive plug in said contact hole with said first inductor means; And Separating said interlayer dielectric film from said first substrate. 18. The method of claim 17 wherein the second and third inductor means are flip chip bumps. 20. The method of claim 19, wherein the second step comprises: forming the flip chip bumps on the substrate in consideration of an interval and an area of a pad area of the RF chip; Aligning the interlayer dielectric film such that the conductive plug and the flip chip bumps are in one-to-one correspondence; And And bonding the substrate and the interlayer dielectric film by flip chip bonding at a predetermined temperature and pressure. 20. The method of claim 19, wherein the second step comprises: forming a flip chip bump in contact with the conductive plug on one surface of the interlayer dielectric film; And And bonding and bonding the substrate and the interlayer dielectric film at a predetermined temperature and pressure. 22. The method of claim 20 or 21, wherein the third step comprises: forming the flip chip bumps on the RF chip pad region; Aligning the RF chip such that the flip chip bump and the conductive plug correspond one-to-one; And And bonding and bonding the RF chip and the interlayer dielectric film at a predetermined temperature and pressure. 23. The method of claim 22, wherein a conductive adhesive film is formed on the substrate prior to flip chip bonding the substrate and the interlayer dielectric film. 23. The method of claim 22, wherein before the flip chip bonding of the interlayer dielectric film and the RF chip, a conductive adhesive film covering the exposed surface of the conductive plug is formed on the interlayer dielectric film. 24. The method of claim 23, wherein a conductive adhesive film is formed on the interlayer dielectric film to cover the exposed surface of the conductive plug before flip chip bonding the interlayer dielectric film and the RF chip.