EP0662650A2 - Dispositif pour le mesure d'intervalles courtes - Google Patents

Dispositif pour le mesure d'intervalles courtes Download PDF

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Publication number
EP0662650A2
EP0662650A2 EP94117713A EP94117713A EP0662650A2 EP 0662650 A2 EP0662650 A2 EP 0662650A2 EP 94117713 A EP94117713 A EP 94117713A EP 94117713 A EP94117713 A EP 94117713A EP 0662650 A2 EP0662650 A2 EP 0662650A2
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EP
European Patent Office
Prior art keywords
pulses
input
measuring
time
mess
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EP94117713A
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German (de)
English (en)
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EP0662650A3 (fr
EP0662650B1 (fr
Inventor
Roland Eusemann
Patrick Zisch
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Siemens AG
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Landis and Gyr Technology Innovation AG
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Publication of EP0662650A2 publication Critical patent/EP0662650A2/fr
Publication of EP0662650A3 publication Critical patent/EP0662650A3/fr
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Publication of EP0662650B1 publication Critical patent/EP0662650B1/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the invention relates to a device and a method for measuring small time intervals according to the preamble of claims 1 and 8 and to the use thereof in a flow volume measuring device.
  • a number of digital and analog electronic measuring methods are known for measuring time intervals in the nanosecond range.
  • the digital processes are characterized by almost unlimited dynamics, i.e. the ratio of the smallest to the largest measurable time interval.
  • the resolution of these methods is comparatively low.
  • the resolution is limited by the maximum clock frequency of the counters, which is approximately 1 GHz in modern counters. Accordingly, the resolution of the simple digital counting method is limited to values greater than approximately 1 ns.
  • Young describes in "1 nanosecond time interval counter"; Instruments & Control Systems 38 (1965), p. 105, how a higher resolution can be achieved through the use of digital interpolation methods by using fast coincidence circuits instead of fast counting circuits, which can be implemented more easily and cost-effectively.
  • Substantially higher resolutions result from the use of analog interpolation methods, whereby a reduction of the digitization errors by 3 to 4 orders of magnitude is possible.
  • analog interpolation methods include pulse width multiplication, as described by G. Kramer in "A high-resolution electronic timepiece”; Telecommunications Magazine 23 (1970) Issue 9, p. 433, or a time-to-amplitude conversion, e.g. from the dissertation by J. W. Klein “Electronic time measurement in the nanosecond and subnanosecond area", TH Aachen (1971) is known.
  • Temporal resolutions down to about 5ps can be achieved with these methods without using the expensive, fast counter circuits.
  • the measurement duration and the energy consumption increase with increasing length of the time interval, so that in these methods the ratio of the maximum to the minimum time intervals, i.e. the dynamics must be limited in order to obtain reasonable measuring times and low energy consumption.
  • the dynamics of these processes are therefore limited to values below 1000.
  • these analog measurement methods have poor long-term stability.
  • An example of such an application is the measurement of a volume flow in a measuring tube using ultrasound after Runtime difference method, which is known for example from CH-PS 604 133.
  • the flow is determined on the basis of the transit time difference between two ultrasound wave packets, which are emitted simultaneously by two transducers for ultrasound arranged at a short distance in front of the end faces of the measuring tube during the transmission phase of a measuring cycle and pass through the measuring tube in the opposite direction, the flow of a medium in the measuring tube one ultrasonic wave packet slows down and the other speeds up.
  • the two ultrasound wave packets therefore arrive with a time shift at the opposite measuring transducer and on the transducer which has now switched to reception for the reception phase of the measurement cycle and converts the sound waves into reception signals.
  • the two received signals thus have a phase shift ⁇ which is dependent on the flow and can be determined by a phase detector.
  • the phase detector generates a pulse from the two received signals for each period of the ultrasonic waves, the duration or width of which is proportional to the phase shift ⁇ between the two received signals.
  • the invention has for its object to provide an inexpensive device for measuring small time intervals, with which the width of pulses within a pulse packet with high resolution and a large dynamic range can be measured with low energy consumption.
  • FIG. 1 a shows the voltage U P of output pulses during the reception phase at the output of a phase detector 99 in FIG. 1 b of a flow volume counter 98 described in the above-mentioned CH-PS 604 133 as a function of time t.
  • the phase detector 99 of the flow volume counter is for Comparing the transit time of the ultrasonic waves delayed or accelerated on the way through a measuring tube 97 by the flow velocity of a medium.
  • a pulse packet delivered at the output of the phase detector 99 during a measurement phase is composed of N individual pulses, N being advantageously chosen to be 50 or more. All N individual pulses within the same pulse packet ideally have the same width from the time interval ⁇ t, since the flow speed changes only imperceptibly during a measurement phase.
  • phase detector 99 is connected via an input line 114 to a measuring circuit 100, which is also suitable, among other things, for measuring the flow velocity of the medium in a flow volume counter 98.
  • the block diagram of the measuring circuit comprises an input switch 1, a measuring oscillator 2, a start logic 3, a first gate circuit 4, a second gate circuit 5, a summing element 6, a stop logic 7, an input pulse counter 8, a sampling pulse counter 9, a time expansion element 10 and a microprocessor 11.
  • the summing element 6 and the input pulse counter 8 are registration means for the input pulses, while the measuring oscillator 2, the sampling pulse counter 9 and the time expansion element 10 work together as measuring means for the registered input pulses.
  • the microprocessor 11 is set up to control the measurement process and to evaluate the measurement results and is connected via control lines 101 to 104 to the input switch 1, the start logic 3, the input pulse counter 8 and the sampling pulse counter 9.
  • the measuring oscillator 2 transmits calibration pulses of a predetermined width via a connection 105 to the input switch 1 and via a line 106 to the second gate circuit 5.
  • the start logic 3 controls the first gate circuit 4 and the second gate circuit 5 via gate control lines 107 and 108.
  • the stop logic 7 is via a start line 109 to the start logic 3 and via a stop line 110 to the first gate circuit 4, there is also an enable connection 111 to the timing element 10, while the stop logic 7 receives control commands from the summing element 6 via a stop signal line 112.
  • the time expansion element 10 has a connection by means of an end signal line 113 to the second gate circuit 5.
  • the input pulses whose width ⁇ t (FIG. 1a) is to be measured, reach the switch 1 of the measuring circuit on the input line 114.
  • the calibration pulses generated by the measuring oscillator 2 are on the Connection 105 or the input pulses on input line 114 at the output of switch 1 are routed to a signal line 115.
  • the signal line 115 branches to the start logic 3, to the first gate circuit 4 and to the stop logic 7.
  • the output of the first gate circuit 4 is connected to a pulse line 116 to the pulse inputs of the summing element 6 and the input pulse counter 8.
  • a sum pulse line 117 establishes the connection between the output of the summing element 6 and the signal input of the timing element 10.
  • the output of the second gate circuit 5 is connected to a scanning pulse line 118 to the pulse input of the scanning pulse counter 9.
  • Inputs of the microprocessor 11 are connected via counter lines 119 and 120 to the input pulse counter 8 and the sampling pulse counter 9 for reading out the corresponding counter reading.
  • the microprocessor 11 Before each measurement or calibration cycle, the microprocessor 11 sets the circuit into a defined initial state via reset lines, not shown here, which connect the microprocessor 11 with the start logic 3, the first and second gate circuits 4 and 5, the summing element 6, the stop logic 7, and the input pulse counter 8 and the sampling pulse counter 9 connect. After each end of a measurement cycle, the microprocessor 11 reads out the input pulse counter 8 and the sampling pulse counter 9 and calculates the width ⁇ t of the input pulses based on the counter readings. Within a measurement cycle, the measurement sequence is controlled exclusively by the start logic 3 and the stop logic 7, which in particular handle all time-critical processes. This has the advantage that the higher-level control by the microprocessor 11 does not have to be time-critical.
  • the measuring circuit has two operating modes, measuring and calibration. Switching between the two operating modes takes place in the electronic input switch 1, which is controlled by the microprocessor 11 via the first control line 101. Depending on the signal level on the first control line 101, either the input pulses in the measuring mode or the calibration pulses from the measuring oscillator 2 in the calibration mode are present at the output of the switch 1, which are passed via the signal line 115 to the start logic 3, the first gate circuit 4 and the stop logic 7 .
  • the measuring circuit treats the input and calibration pulses as completely equivalent. Therefore, instead of the input and calibration pulses, only the input pulses on the signal line 115 are referred to below.
  • the start logic 3 After release by the microprocessor 11 via the second control line 102, the start logic 3 opens the first gate circuit 4 by means of a with the following rising edge of the input pulses arriving via the signal line 115 at the start logic 3 Signals on the first gate control line 107, so that the input pulses also pass through the first gate circuit 4 via the pulse line 116 to the input of the summing element 6 and to the input of the input pulse counter 8.
  • the summing element 6 adds up the widths ⁇ t i of the successive input pulses. As soon as the sum ⁇ t S of the widths ⁇ t i exceeds a predetermined limit, the registration interval R, the stop logic 7 is activated via the stop signal line 112.
  • the stop logic 7 waits until the input pulse currently present has ended and then closes the first gate circuit 4 with a signal on the stop line 110 and at the same time resets the start logic 3 with a signal on the start line 109 into the ready state. There are therefore no further input pulses to the summing element 6 and to the input pulse counter 8.
  • the number k mess of the summed input pulses is stored in the input pulse counter 8 and is transmitted via the first counter line 119 to the microprocessor 11 for evaluation and stored there.
  • the start logic 3 initiates the opening of the second gate circuit 5 via the second gate control line 108, and at the same time the stop logic 7 enables the time expansion element 10 via the enable line 111, the time expansion element 10 releasing the sum pulse on the sum pulse line 117 the width ⁇ t S is extended in time by the expansion factor z and sends a positive output pulse with the width z ⁇ ⁇ t S via the end signal line 113 to the second gate circuit 5.
  • the calibration pulses generated by the measuring oscillator 2 pass through the line 106 as a scanning pulse to the scanning pulse counter 9 via the scanning pulse line 118 and are summed up there until the second gate circuit 5 through the falling edge of the timing signal via the end signal line 113 10 sent output pulse is closed.
  • the number N mess stored in the scanning pulse counter 9 is read out and stored by the microprocessor 11 via the second counter line 120.
  • the pulses arriving on the pulse line 116 are first summed up in the summing element 6 and the sum pulse is then stretched in the time expansion element 10.
  • a signal for opening the second gate circuit 5 is sent to the start logic 3 via the start line 109 in synchronism with the closing of the first gate circuit 4 by the stop logic 7.
  • the stop logic 7 releases the time expansion element 10 via the enable line 111, the time expansion element 10 extending the sum pulse on the pulse line 116 of the width ⁇ t S by the expansion factor z and a positive output pulse with the width z ⁇ ⁇ t S via the End signal line 113 sends to the second gate circuit 5.
  • the Calibration pulses on line 106 then pass through the second gate circuit 5 via the scanning pulse line 118 to the scanning pulse counter 9, the count of which after closing the second gate circuit 5 is the number N mess .
  • the advantage of the time expansion circuit 10 is due to the fact that it extends the width ⁇ t i of the input pulses present on the signal line 115 by an expansion factor z. Since in reality the widths ⁇ t i of the N individual input pulses of the same measurement cycle only scatter by a very small amount as a result of the "jitter" in the switching elements and this random error is averaged out by the method described, for a measurement cycle with the same widths ⁇ t is the N to calculate individual input pulses.
  • T osz is the period of the measuring oscillator 2.
  • the stop logic 7 ensures that the width ⁇ t S of the sum pulse is almost constant. This has the effect that the number N mess of the sampling pulses is almost independent of the width ⁇ t of the input pulses.
  • the minimum required number N of the input pulses in the pulse packet and the number k mess of the summed input pulses in the input pulse counter 8 are not independent of one another, since the number N determines the shortest, measurable time interval ⁇ t and its digitization error f because the number k mess is not greater than N can be.
  • the long-term constancy of the expansion factor z depends on the temperature and changes over time due to the aging of the components.
  • the first measurement carried out a calibration of the measuring circuit, which is repeated after a predetermined number of measuring cycles with the input pulses on the input line 114.
  • the calibration pulses from the measuring oscillator 2 are applied to the signal line 115 via the input switch 1.
  • the microprocessor 11 calculates the expansion factor z according to equation (3) .
  • z (N cal ⁇ T osz ) / (k cal ⁇ ⁇ t osz ) (3)
  • the microprocessor 11 stores the expansion factor z or N cal and k cal for the evaluation of the subsequent measurement cycles.
  • the temperature response and the stability of the measuring circuit are only determined by the properties of the measuring oscillator 2.
  • the use of a quartz-controlled measuring oscillator 2 has the advantage that the measuring circuit is characterized by a low temperature drift and high long-term stability, as are also known from inexpensive quartz crystals.
  • the measuring circuit therefore has the particular advantage that it does not require fast counting circuits and can therefore be manufactured inexpensively.
  • FIG. 3 shows an advantageous embodiment of the invention.
  • the summing element 6 (FIG. 2) and the time expansion element 10 (FIG. 2) comprise a capacitor 12, two constant current sources, the charging source 13 and the current sink 14, two controllable switches 15 and 16 and two comparators 17 and 18 with associated reference voltage sources 19 and 20.
  • the first reference voltage source 19 has a first reference voltage U R1 and the second reference voltage source 20 has a second reference voltage U R2 .
  • To control the first controllable switch 15, its control input is connected to the output of the first comparator 17 via a switching line 121.
  • the constant current source 13 or 14 can be connected to the one pole 21 of the capacitor 12 with the voltage U via the controllable switch 15 or 16.
  • One input of the comparator 17 or 18 is connected to the pole 21, while the other input of the comparator 17 or 18 is connected to the reference voltage source 19 or 20.
  • the start logic 3 (FIG. 2) and the stop logic 7 (FIG. 2) are combined as control logic 22.
  • the microprocessor 11 is connected to the components of the measuring circuit, via the first control line 101 to the input switch 1, via the second control line 102 to the control logic 22, via the third control line 103 to the input pulse counter 8, via the fourth control line 104 with the scanning pulse counter 9.
  • the microprocessor 11 reads out the count of the input pulse counter 8 or the scanning pulse counter 9 via the first or second counter line 119 or 120.
  • the summation of the widths ⁇ t (FIG. 1a) of the input or calibration pulses on the signal line 115 and the time expansion by the expansion factor z are carried out by charging and discharging the capacitor 12 with the aid of the two constant current sources, a charging current source 13 and a current sink 14 Voltage U across the capacitor 12 is monitored by the two comparators 17 and 18. Between the measurements, the comparator 17 in conjunction with the charging current source 13 and the switch 15 ensures that the voltage U at the pole 21 is approximately equal to the first reference voltage U R1 of the reference voltage source 19. As soon as the voltage U falls below the reference voltage U R1 , the output of the comparator 17 and thus the level on the switching line 121 go to logic "high".
  • the registration interval R is defined as the difference between the two reference voltages U R1 and U R2 .
  • the circuit can also be designed such that the input pulses charge the capacitor 12 via the second controllable switch 16 and the capacitor 12 is discharged via the first controllable switch 15.
  • the control logic 22 blocks the AND gate used as the first gate circuit 4 by outputting a "low" level on the first gate control line 107. After release by the microprocessor 11, the control logic 22 waits until the next positive edge of the input pulses on the signal line 115, until it sets the measurement operation by setting the level of the first gate control line 107 to logic "high” enables.
  • the switchover between measurement and calibration is carried out by the microprocessor 11, which sends a control signal to the control input of the input switch 1 via the first control line 101.
  • the pulses passed by the first gate circuit 4 control the switch 16. Whenever a pulse is present on the pulse line 116 ("high" level), the switch 16 is closed, so that the capacitor 12 via the current sink 14 with a predetermined current I E is being discharged. The switch 16 is open between the successive pulses, so that the capacitor 12 is not discharged during the pulse pauses.
  • the voltage U on the capacitor 12 drops below the reference voltage U R1 immediately after the start of the measurement.
  • the output of the comparator 17 goes to "high" and opens the second gate circuit 5 via the second gate control line 108.
  • Another AND gate for example, is used as the second gate circuit 5, the second gate control line 108 leading to one input of the AND gate and the other input of the AND gate is connected to measuring oscillator 2 via line 106. Its calibration pulses are now switched as scanning pulses via the measuring pulse line 118 to the scanning pulse counter 9 and summed up there. At the same time, switch 15 is closed via switching line 121. The capacitor 12 is thereby charged with a charging current I L via the charging current source 13.
  • the charging current I L is three orders of magnitude smaller than the discharging current I E.
  • FIG. 4 shows the course of the voltage U P of the input pulses on the signal line 115 (FIG. 3) at the top and the course of the voltage U at the pole 21 (FIG. 3) as a function of the time t below.
  • the output of the second comparator 18 goes to logic "low” and sets the control logic 22 connected to the output of the second comparator 18 via a line 122 Standby.
  • the control logic 22 advantageously waits until the falling edge of the input pulse currently present appears, and then blocks the AND gate of the first gate circuit 4 by outputting a "low” level on the first gate control line 107.
  • the control logic 22 thus ensures that this last input pulse with the entire width ⁇ t (FIG. 1a) is also measured. No further pulses now reach the switching input of the second controllable switch 16 via the pulse line 116.
  • the number k mess or k cal of the summed input pulses is stored in the input pulse counter 8 and is read out and further processed by the microprocessor 11 after the end of the measurement.
  • the expansion factor z or N cal and k cal the microprocessor 11 then calculates the width ⁇ t of the input pulses according to equation (4).
  • the measuring circuit When dimensioning the measuring circuit, it is advantageously taken into account that the charging of the capacitor 12 during the pauses of the length ⁇ T S - ⁇ t ⁇ (FIG. 1a) between the input pulses is very much smaller than the discharge during the time ⁇ t. In this case, the time ⁇ t mess is almost independent of the width ⁇ t and the period T S of the input pulses. In particular, the lengths (T - ⁇ t) of the pauses can therefore vary from pulse to pulse and do not have to be constant as shown in FIGS. 1 and 4. In this case too, the measuring circuit always determines the correct width ⁇ t of the input pulses. If the widths ⁇ t differ from pulse to pulse, the measuring circuit determines the correct mean value from the N widths ⁇ t.
  • the first controllable switch 15 remains closed for the entire measurement period .DELTA.t mess , so that disturbances in the measurement process by switching the charging current source 13 on and off are avoided.
  • the pulse packet (FIG. 1a) contains information coded in the time interval ⁇ t, the width of the pulses, for example the flow velocity of the medium in the flow volume counter of CH-PS 604 133.
  • the measuring circuit also processes pulses with the widths ⁇ t i from a constant pulse stream, since the first gate circuit 4 (FIG. 2) determines the number N mess .

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP94117713A 1994-01-10 1994-11-10 Dispositif pour le mesure d'intervalles courtes Expired - Lifetime EP0662650B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CH5894 1994-01-10
CH5894 1994-01-10
CH58/94 1994-01-10

Publications (3)

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EP0662650A2 true EP0662650A2 (fr) 1995-07-12
EP0662650A3 EP0662650A3 (fr) 1997-04-02
EP0662650B1 EP0662650B1 (fr) 2000-09-13

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EP94117713A Expired - Lifetime EP0662650B1 (fr) 1994-01-10 1994-11-10 Dispositif pour le mesure d'intervalles courtes

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EP (1) EP0662650B1 (fr)
CZ (1) CZ287073B6 (fr)
DE (1) DE59409519D1 (fr)
DK (1) DK0662650T3 (fr)
PL (1) PL175439B1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8618965B2 (en) 2011-12-28 2013-12-31 St-Ericsson Sa Calibration of a charge-to-digital timer
WO2013098785A3 (fr) * 2011-12-28 2014-01-23 St-Ericsson Sa Convertisseur temps-numérique à charge résistive/résiduelle
US8659360B2 (en) 2011-12-28 2014-02-25 St-Ericsson Sa Charge-to-digital timer
RU2620191C1 (ru) * 2016-08-22 2017-05-23 Александр Абрамович Часовской Устройство измерения малого временного интервала
CN110412545A (zh) * 2019-07-26 2019-11-05 桂林理工大学 脉冲激光雷达时间间隔的模-数测量电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CZ308685B6 (cs) * 2019-12-08 2021-02-17 Pavel Ing. Trojánek Zařízení pro přesné měření časových intervalů

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245192A (en) * 1978-10-19 1981-01-13 Lockheed Corporation Periodicity verification circuit
DE3219788A1 (de) * 1982-05-25 1983-12-01 Siemens AG, 1000 Berlin und 8000 München Durchflussmengenmesseinrichtung fuer fluide und modifikation der durchflussmengenmesseirnichtung zur verwendung als waermemengenzaehler
JPS62257067A (ja) * 1986-05-01 1987-11-09 Kenwood Corp 時間幅測定方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245192A (en) * 1978-10-19 1981-01-13 Lockheed Corporation Periodicity verification circuit
DE3219788A1 (de) * 1982-05-25 1983-12-01 Siemens AG, 1000 Berlin und 8000 München Durchflussmengenmesseinrichtung fuer fluide und modifikation der durchflussmengenmesseirnichtung zur verwendung als waermemengenzaehler
JPS62257067A (ja) * 1986-05-01 1987-11-09 Kenwood Corp 時間幅測定方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 136 (P-694), 26.April 1988 & JP 62 257067 A (KENWOOD CORP), 9.November 1987, *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8618965B2 (en) 2011-12-28 2013-12-31 St-Ericsson Sa Calibration of a charge-to-digital timer
WO2013098785A3 (fr) * 2011-12-28 2014-01-23 St-Ericsson Sa Convertisseur temps-numérique à charge résistive/résiduelle
US8659360B2 (en) 2011-12-28 2014-02-25 St-Ericsson Sa Charge-to-digital timer
US9379729B2 (en) 2011-12-28 2016-06-28 St-Ericsson Sa Resistive/residue charge-to-digital timer
RU2620191C1 (ru) * 2016-08-22 2017-05-23 Александр Абрамович Часовской Устройство измерения малого временного интервала
CN110412545A (zh) * 2019-07-26 2019-11-05 桂林理工大学 脉冲激光雷达时间间隔的模-数测量电路

Also Published As

Publication number Publication date
PL306708A1 (en) 1995-07-24
EP0662650A3 (fr) 1997-04-02
DK0662650T3 (da) 2001-06-11
EP0662650B1 (fr) 2000-09-13
DE59409519D1 (de) 2000-10-19
CZ3995A3 (en) 1995-07-12
CZ287073B6 (en) 2000-08-16
PL175439B1 (pl) 1998-12-31

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