EP0638429B1 - Procédé de commande de la tête ligne d'un appareil d'impression thermique et appareil associé - Google Patents

Procédé de commande de la tête ligne d'un appareil d'impression thermique et appareil associé Download PDF

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Publication number
EP0638429B1
EP0638429B1 EP94401791A EP94401791A EP0638429B1 EP 0638429 B1 EP0638429 B1 EP 0638429B1 EP 94401791 A EP94401791 A EP 94401791A EP 94401791 A EP94401791 A EP 94401791A EP 0638429 B1 EP0638429 B1 EP 0638429B1
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EP
European Patent Office
Prior art keywords
heating elements
register
activation
activated
positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94401791A
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German (de)
English (en)
French (fr)
Other versions
EP0638429A1 (fr
Inventor
Alain Frederic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sagem SA
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Sagem SA
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Publication date
Application filed by Sagem SA filed Critical Sagem SA
Publication of EP0638429A1 publication Critical patent/EP0638429A1/fr
Application granted granted Critical
Publication of EP0638429B1 publication Critical patent/EP0638429B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
    • B41J2/355—Control circuits for heating-element selection

Definitions

  • a thermal printing device such as a fax machine, has a print head in which a plurality of elements resistive heaters can be activated to print a line.
  • Each heating element is connected to a power source and individually ordered to print or not a black dot.
  • each heating element is supplied under 24 volts and has a resistance of about 3000 ohms.
  • heating elements Given their number, the total current consumption of heating elements, if they had to be activated simultaneously, would be very high. As an example, around 1,800 elements would consume about 15 amps. This is why, in many fax machines, the heating elements are grouped into four blocks, for example 450 heating elements approximately, activated successively.
  • the power supply must therefore only supply a maximum current limited to approximately 3.5 amps for printing a block of black dots. Such a source However, the supply is still too bulky and expensive.
  • JP 58-175 677 teaches to order successively, one by one, the heating elements.
  • JP 63-42 874 teaches to count, in a row of points, the number of black dots to print to compare it to a maximum threshold determined from head temperature, estimated from number of previously printed dots and therefore cooling. In case of expected crossing of the threshold, the row of points is segmented, to make drop the current below. So this is how it works sequential by blocks indicated above.
  • the present invention aims to reduce the maximum supply current.
  • the heating elements are no longer activated by size blocks predetermined, as in the printing devices of the prior art, but by variable size blocks of a predetermined maximum number heating elements activated and of an indeterminate and variable number inactive heaters. So instead of booking durations printing for blocks of predetermined size, this is the information to be print, i.e. the presence of black dots, which defines the size of the blocks and thus allows to optimize the impression, by "ignoring" the presence white people.
  • the heating elements are grouped into size blocks predetermined, and, if the number of heating elements to activate a block is less than said predetermined number, before activation, the selection from the heating elements to be activated from another block.
  • the invention also relates to a thermal printing apparatus for placing implementing the method of the invention, comprising a line head, comprising a plurality of heating elements, an activation control register heating elements and a transfer register arranged to receive, storage means, activation control data and the transfer to the command register, and sequencing means for control the command register, and sequencing means for control the head transfer register, device characterized by the fact that the sequencing means are arranged to count the number heating elements whose activation is controlled, for controlling means for memorizing addresses of the positions of said elements heating and control of data storage means of command, and to inhibit the transfer register if said number exceeds a threshold greater than unity.
  • the thermal printing apparatus of the invention comprises, in its first embodiment, a thermal head 1 shown in Figure 1, including a row of 1728 heating elements printing, generally referenced 2, cooperates with a ribbon thermal transfer printing ink not shown, applied to a print medium consisting of paper, driven scrolling against the head 1.
  • the printing elements 2 with a resistance of 3000 ohms, are connected to a wire power supply 3 at +24 volts and are controlled by individual amplifiers / switches 4, operating in inverters and absorbing the 8 milliamps passing through each printing element 2 when activated.
  • Amplifiers 4 are each controlled by a memorized own activation bit in a memory point 6, here of the flip-flop type "D", of a register 5 print command buffer with inputs and outputs parallels comprising an ordered row of 1728 such points memory 6.
  • a demultiplexer circuit 10 has eleven inputs address, referenced 11, and 1728 respectively linked outputs to 1728 clock inputs 7 belonging respectively to 1728 memory points 6.
  • the 1728 memory points 6 respectively comprise 1728 data bit inputs 8A connected to a common link 8. It an input 9 is here provided, connected to all the memory points 6, allowing the simultaneous reset of all, that is to say their forcing in the same predetermined state, here a logic level 0, says inactive, for which the heating elements 2 are not supplied with current through the amplifiers 4.
  • the flip-flops "D" of the memory points 6 can for example be realized by means of integrated circuits, in TTL technology or CMOS, of type 7474 while demultiplexer 10 can, from even, be realized by means of several integrated circuits of the type 74154 or 74HC154 and a logic of selection of only one of them, acting on an address entry then serving as an entry for validation, the corresponding outputs of circuit 74 (HC) 154 being then unused.
  • JK type flip-flops could have been provided, divider by two, not flip-flops "D", which would have avoided the need for data link 8 since each addressing of such a divider would be enough to make it change state.
  • each memory point 6 is thus a bit activation of the heating elements 2, which can have two states, know an active state, here logic level 1, and an inactive state, here the logic level 0.
  • the address memory point "three" returns to 0 during the period T3, while the address memory point "one” returns to 0 during the period T4.
  • the impulses of order appearing from one period T1-T4 to the other pass to state 0, while in practice the data link 8 remains at the same level during each period T1-T4 and is read, by sampling, by an active edge, here falling, of the signal 7.
  • the periods T1-T4 are limited to a few tens of nanoseconds, which makes it possible to order all of the memory points 6 in a much less time than the 10 milliseconds provided by the standards for printing of a line.
  • Print register 5 includes, as indicated, 1728 data entries 8A of points memory 6 which, through doors 44 are connected to as many outputs of an input register 43 containing a series of signals binaries representing arranged numbers, encoded in this example, respectively representative of the gray intensities of points of a line to print.
  • a control circuit 41 is connected by means of a reading 42 of circuit 41, to input register 43 and command the opening of a determined number of doors 44, of position determined, this number of doors being a function of the numbers coded read in register 43, as explained below.
  • Hatched areas indicate blocks of bits transferred simultaneously, the position of the hatched areas of the register 43 corresponding to that of the hatched areas of the register 5, the presence of numbers other than zero, indicating gray, being marked by doubly blocks hatched. A coded number therefore corresponds to a bit of the same address of the printing register 5.
  • Figure 4 shows in more detail the diagram of Figure 3.
  • the output of the multiplexer 42 is connected to a transcoder circuit 47 which converts each coded number received into another number, not coded, of predetermined length, comprising bits at the head activation in state 1, in a number proportional to the intensity of the gray defined by the corresponding coded number, these non-coded numbers being stored in a memory 48.
  • the memory 48 is here a buffer memory allowing the memorization of the bits representing several lines, these bits therefore being control data heating element activation 6.
  • memory 48 has not been shown in FIG. 3 and would therefore be interpose, with the transcoder circuit 47, between the outputs of the entry register 43 and doors 44.
  • the output of memory 48 also attacks a counter 49 which detects the presence of activation bits in 1 and emits a signal stop 50 when it reaches a predetermined threshold value N.
  • the signal 50 has the effect of stopping an address counter 51 common driving the multiplexer 42 and the demultiplexer 10, connected output to the printing register 5 and here shown integrated into the circuit 41.
  • a sequencer circuit 52 forces counter 51 to a determined address value, from value "a" at the beginning, and starts a cycle of a sequence of reading the first bits of each uncoded word from memory 48. If the bit read is in "1”, this "1" is copied into the memory point 6 with the same address by addressing using the demultiplexer 10, and activation of the link 8 in the case, considered here, of use of type D flip-flops in the printing register 5.
  • a decoder, or comparator, integrated at the output of the counter 49 emits the stop signal 50, which stops any new sending of "1" to the printing register 5, and the address AS of the last memory point 6 in “1” is memorized by the circuit sequencer 52 in an address memory 54 belonging here to the sequencer circuit 52. Circuit 52 then resets to "a" the counter 49 to start a new cycle, relating to second bits of the uncoded numbers of the memory 48 and, then, sends a command to deactivate memory points 6, address "one" to AS, for which the second bit of the number is not coded is in state 0.
  • the maximum instantaneous current is thus limited to N times 8 milliamps.
  • the bits of the line next to be printed are read in the input register 43, to start a new printing, after advancing the support to to print.
  • the print head 101 is a commercial head and the demultiplexer 10 is replaced, in this second form of realization, by a shift transfer register 110, here integrated at head 101, receiving in series the 1728 activation bits by sound data entry 111 at the rate of a clock signal 111B applied to a 111A clock serial input.
  • the buffer register 105 is logically divided into four blocks 112-115 of 432 memory points 106, each with a input for validating the outputs of memory points 106 connected in specific to a validation command link 116-119.
  • An entrance clock 107 controls storage in all points memory 106.
  • the validation command links 116-119 authorize the output of the bits contained in blocks 112-115 and, in the absence of validation, force at logic level 0 the outputs corresponding to amplifiers 104, which corresponds a lack of activation command of the heating elements 102.
  • the head 101 is controlled by a circuit 141, homologous to the circuit 41 and connected to the output of an input shift register 143.
  • the input register 143 receives from the outside 1728 bits representing directly, in this example, the black or white dots of a line to be printed and transmits them to memory 148.
  • the operating principle of circuit 141 is similar to that of circuit 41, with the difference that it is each time transferred 1728 bits, including the N in the active state.
  • the counter 151 receives from clock sequencer 153 the clock signal 111B, also applied, as shown, to shift register 110.
  • the counter 151 systematically counts from 1 to 1728, without control by the stop signal 150, and is connected at output to sequencer 152.
  • the limit addresses of the areas of the line to be printed including the positions have already been processed by the sequencer 152 are memorized in a memory 154 of the sequencer 152 which thus acts as mask to determine the areas remaining to be treated.
  • a gate 153 here of the AND type, connects the output of memory 148 to entry 111 of shift register 110 and has two other inputs, control.
  • the first control input is connected to the sequencer 152 and the second control input receives the signal 150, which is also applied to the sequencer 152 and which is memorized in counter 149 until it is reset to zero, in order to keep the door locked 153.
  • circuit 141 The operation of circuit 141 is as follows.
  • the 1728 bits of a line are transferred from memory 148 to entry 111 of shift register 110 through gate 153, at clock signal timing 111B.
  • the signal 150 locks the door 153, the output of which is blocks at logic level 0 until the end of the transfer of 1728 bits, which inhibits the transmission of activation bits in numbers excessive, at level "1".
  • the signal 150 also controls the memorization by the sequencer 152, in the memory 154, of the AS address for which the bit transfer inhibition occurs of activation command in "1".
  • the heating elements 102 are individually activated by a serial transfer of activation commands and, for heating elements 102 which must remain inactive, we force, before transfer them, individual commands to an inactive state, 0.
  • the sequencer 152 controls, via a link 107A connected to the input 107 of the buffer register 105, the parallel loading of the bits of the register 110 in buffer register 105, when the duration necessary to print the previous points has passed.
  • the sequencer 153 activates, here simultaneously, the four validation command links 116-119. A variant in the control of these connections is explained further.
  • the transfer register 110 receives, from memory 148, activation command data and transfers it to the registry 105, and the sequencer 152 controls the transfer 110 and count, with the counter 149, the number heating elements 102 whose activation is controlled, for order its memory 154 for memorizing the addresses of heater positions 102 above and control the control data memory 148, and the sequencer 152 inhibits transfer register 110 if the above number exceeds the threshold N.
  • the four validation command links 116-119 are separate there could be expected that the 149 activation bit counter transferred to register 110 performs such a count for each block 112-115. In this case, it would be transferred each time four times N activation bits, as long as they exist in one such number, to shift register 110 then to register buffer 105. The sequencer 153 would then activate successively, in any desired order, the validation command links 116-119. The number of transfers would thus be reduced by a factor of 4.
  • the heating elements 102 are grouped in blocks of predetermined size and, if the number of elements heaters 102 to activate a block is less than the number predetermined N, before activation the selection is continued among the heating elements 102 to be activated from another block.
  • the transfer register 110 with the door 153, thus makes it possible to transfer line portions of sizes and positions respective predetermined and, in case of inhibition by the sequencer 152, it transmits to the command buffer register 105 print portions of white line.

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EP94401791A 1993-08-04 1994-08-03 Procédé de commande de la tête ligne d'un appareil d'impression thermique et appareil associé Expired - Lifetime EP0638429B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9309613 1993-08-04
FR9309613A FR2708525B1 (fr) 1993-08-04 1993-08-04 Procédé de commande de la tête ligne d'un appareil d'impression thermique et appareil d'impression thermique pour la mise en Óoeuvre du procédé.

Publications (2)

Publication Number Publication Date
EP0638429A1 EP0638429A1 (fr) 1995-02-15
EP0638429B1 true EP0638429B1 (fr) 1998-11-25

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EP94401791A Expired - Lifetime EP0638429B1 (fr) 1993-08-04 1994-08-03 Procédé de commande de la tête ligne d'un appareil d'impression thermique et appareil associé

Country Status (5)

Country Link
US (1) US5742321A (enrdf_load_stackoverflow)
EP (1) EP0638429B1 (enrdf_load_stackoverflow)
DE (1) DE69414775T2 (enrdf_load_stackoverflow)
FR (1) FR2708525B1 (enrdf_load_stackoverflow)
NO (1) NO310218B1 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002417A (en) * 1998-01-23 1999-12-14 Eastman Kodak Company Method and apparatus for dynamically sizing and operating enable groups of thermal elements in a printer
DE10042227A1 (de) * 2000-08-28 2002-03-28 Siemens Ag Verfahren und Vorrichtung zur Überwachung einer Maschine
US6705697B2 (en) * 2002-03-06 2004-03-16 Xerox Corporation Serial data input full width array print bar method and apparatus

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4284876A (en) * 1979-04-24 1981-08-18 Oki Electric Industry Co., Ltd. Thermal printing system
FR2459591A1 (fr) * 1979-06-19 1981-01-09 Amicel Jean Claude Procede et dispositif de telecopie a sauts de blancs
JPS58175677A (ja) * 1981-11-09 1983-10-14 Toshiba Corp 感熱ヘツドの駆動方法
JPS6044371A (ja) * 1983-08-20 1985-03-09 Ricoh Co Ltd サ−マルヘツドの駆動方法
JPH0761117B2 (ja) * 1984-08-31 1995-06-28 富士ゼロックス株式会社 感熱記録方法および装置
JPS6342874A (ja) * 1986-08-08 1988-02-24 Fujitsu Ltd プリンタ
JP2575304B2 (ja) * 1987-03-06 1997-01-22 イーストマン・コダック アジア・パシフィック株式会社 熱転写印刷ヘツド用発熱体駆動装置
JPS63290768A (ja) * 1987-05-25 1988-11-28 Ricoh Co Ltd サ−マルヘッドの駆動方法
JPH02258355A (ja) * 1989-03-31 1990-10-19 Toshiba Corp 電子機器
JPH0379377A (ja) * 1989-08-23 1991-04-04 Seiko Instr Inc プリンタの印字率補正回路
US5053790A (en) * 1990-07-02 1991-10-01 Eastman Kodak Company Parasitic resistance compensation for thermal printers

Also Published As

Publication number Publication date
DE69414775T2 (de) 1999-05-27
FR2708525B1 (fr) 1995-10-20
NO942885L (no) 1995-02-06
DE69414775D1 (de) 1999-01-07
US5742321A (en) 1998-04-21
EP0638429A1 (fr) 1995-02-15
NO310218B1 (no) 2001-06-05
NO942885D0 (enrdf_load_stackoverflow) 1994-08-03
FR2708525A1 (fr) 1995-02-10

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