EP0638429B1 - Method for controlling the line head of a thermal printing apparatus and associated printer - Google Patents

Description

A thermal printing device, such as a fax machine, has a print head in which a plurality of elements resistive heaters can be activated to print a line.

Each heating element is connected to a power source and individually ordered to print or not a black dot. In one fax machine, generally, each heating element is supplied under 24 volts and has a resistance of about 3000 ohms.

Given their number, the total current consumption of heating elements, if they had to be activated simultaneously, would be very high. As an example, around 1,800 elements would consume about 15 amps. This is why, in many fax machines, the heating elements are grouped into four blocks, for example 450 heating elements approximately, activated successively.

The power supply must therefore only supply a maximum current limited to approximately 3.5 amps for printing a block of black dots. Such a source However, the supply is still too bulky and expensive.

To limit the current, JP 58-175 677 teaches to order successively, one by one, the heating elements.

Likewise, JP 63-42 874 teaches to count, in a row of points, the number of black dots to print to compare it to a maximum threshold determined from head temperature, estimated from number of previously printed dots and therefore cooling. In case of expected crossing of the threshold, the row of points is segmented, to make drop the current below. So this is how it works sequential by blocks indicated above.

The present invention aims to reduce the maximum supply current.

• on mémorise les positions des éléments chauffants à activer,
• on en sélectionne, en en repérant et mémorisant les positions, un nombre prédéterminé supérieur à l'unité, que l'on active,
• et, après désactivation, on répète l'étape précédente pour des points à imprimer de positions non encore repérées, et ce,
• jusqu'à impression de la totalité des points de la ligne à imprimer, avant de faire avancer le support d'impression.

To this end, it relates to a method for controlling a line head of a thermal printing apparatus, in which, for the printing of a line of dots on a printing medium, heating elements of the head, characterized by the fact that

• the positions of the heating elements to be activated are memorized,
• we select, by locating and memorizing the positions, a predetermined number greater than one, which we activate,
• and, after deactivation, the preceding step is repeated for dots to be printed from positions not yet identified, and this,
• until all the dots on the line to be printed have been printed, before feeding the printing medium.

Thus, one can choose the maximum current of the supply by a choice appropriate for the number of heating elements simultaneously activated. We note that this number can be very limited without necessarily restrict the average printing speed of a line, since it is activated at each time all the heating elements selected. In other words, the heating elements are no longer activated by size blocks predetermined, as in the printing devices of the prior art, but by variable size blocks of a predetermined maximum number heating elements activated and of an indeterminate and variable number inactive heaters. So instead of booking durations printing for blocks of predetermined size, this is the information to be print, i.e. the presence of black dots, which defines the size of the blocks and thus allows to optimize the impression, by "ignoring" the presence white people.

Preferably, the heating elements are grouped into size blocks predetermined, and, if the number of heating elements to activate a block is less than said predetermined number, before activation, the selection from the heating elements to be activated from another block.

The invention also relates to a thermal printing apparatus for placing implementing the method of the invention, comprising a line head, comprising a plurality of heating elements, an activation control register heating elements and a transfer register arranged to receive, storage means, activation control data and the transfer to the command register, and sequencing means for control the command register, and sequencing means for control the head transfer register, device characterized by the fact that the sequencing means are arranged to count the number heating elements whose activation is controlled, for controlling means for memorizing addresses of the positions of said elements heating and control of data storage means of command, and to inhibit the transfer register if said number exceeds a threshold greater than unity.

• la figure 1 est un schéma par blocs d'une tête d'impression à chargement parallèle dans la première forme de réalisation,
• la figure 2 est un diagramme des temps de signaux de commande de la tête d'impression de la figure 1,
• la figure 3 est un schéma simplifié par blocs de la tête d'impression ci-dessus et d'une logique de commande de cette tête,
• la figure 4 est un schéma plus détaillé que celui de la figure 3,
• la figure 5 est un schéma par blocs d'une tête d'impression à chargement série dans la seconde forme de réalisation et
• la figure 6 est un schéma par blocs de la tête d'impression de la figure 5 et d'un logique de commande de cette tête.

The invention will be better understood with the aid of the following description of two preferred embodiments of the line head thermal printing apparatus for implementing the method of the invention, with reference to the appended drawing in which :

• FIG. 1 is a block diagram of a print head with parallel loading in the first embodiment,
• FIG. 2 is a diagram of the times of control signals of the print head of FIG. 1,
• FIG. 3 is a simplified block diagram of the above print head and of a control logic for this head,
• FIG. 4 is a more detailed diagram than that of FIG. 3,
• FIG. 5 is a block diagram of a print head with serial loading in the second embodiment and
• Figure 6 is a block diagram of the print head of Figure 5 and a control logic of this head.

The thermal printing apparatus of the invention comprises, in its first embodiment, a thermal head 1 shown in Figure 1, including a row of 1728 heating elements printing, generally referenced 2, cooperates with a ribbon thermal transfer printing ink not shown, applied to a print medium consisting of paper, driven scrolling against the head 1. The printing elements 2, with a resistance of 3000 ohms, are connected to a wire power supply 3 at +24 volts and are controlled by individual amplifiers / switches 4, operating in inverters and absorbing the 8 milliamps passing through each printing element 2 when activated. Amplifiers 4 are each controlled by a memorized own activation bit in a memory point 6, here of the flip-flop type "D", of a register 5 print command buffer with inputs and outputs parallels comprising an ordered row of 1728 such points memory 6. A demultiplexer circuit 10 has eleven inputs address, referenced 11, and 1728 respectively linked outputs to 1728 clock inputs 7 belonging respectively to 1728 memory points 6.

The 1728 memory points 6 respectively comprise 1728 data bit inputs 8A connected to a common link 8. It an input 9 is here provided, connected to all the memory points 6, allowing the simultaneous reset of all, that is to say their forcing in the same predetermined state, here a logic level 0, says inactive, for which the heating elements 2 are not supplied with current through the amplifiers 4.

The flip-flops "D" of the memory points 6 can for example be realized by means of integrated circuits, in TTL technology or CMOS, of type 7474 while demultiplexer 10 can, from even, be realized by means of several integrated circuits of the type 74154 or 74HC154 and a logic of selection of only one of them, acting on an address entry then serving as an entry for validation, the corresponding outputs of circuit 74 (HC) 154 being then unused. JK type flip-flops could have been provided, divider by two, not flip-flops "D", which would have avoided the need for data link 8 since each addressing of such a divider would be enough to make it change state.

The above integrated circuits are available from TEXAS INSTRUMENTS or MOTOROLA companies.

To control the activation of a heating element 2, a corresponding address in the row is applied a short instant at address entries 11, link 8 having previously been upgraded to logic level 1 (Figure 2). Leaving the demultiplexer 10 connected to the clock input 7 of the memory point 6 of the heating element 2 considered provides a pulse during the duration of address application to address entries 11, which has to open an activation door, not shown heating element 2, which reads the logic level of the data link 8 and controls storage, in the point memory 6 concerned, of a bit having logic level 1 present on the data link 8.

The deactivation of a memory point 6 is carried out in the same way, the link 8 is then brought to logic level 0.

The bit contained in each memory point 6 is thus a bit activation of the heating elements 2, which can have two states, know an active state, here logic level 1, and an inactive state, here the logic level 0.

So in Figure 2, which is a time diagram of the signals above, the memory point 6 of address "one" is addressed, a short instant within a period T1 of a sequence Ti (i integer = 1 to P), by setting the least significant address bit A0 applied to the address entries 11, the other bits, not all of which are represented, being at level 0, which generates a pulse on the clock input 7 of memory point 6 of address "one", including the logic level, or state, is represented by signal 21.

During the following period T2, another memory point 6, here address "three", is addressed, the two address bits of weight weak, A0 and A1, passing to level 1 to provide the binary address 11, three in decimal. Signal 23 represents the logic level of the bit contained in the memory point of address "three". The states initials of memory points 6 have here been assumed to be state 0.

In this example, the address memory point "three" returns to 0 during the period T3, while the address memory point "one" returns to 0 during the period T4. There is thus simultaneous, or interleaved, management of several memory points 6, by sharing the time t into slices or periods Ti.

It will be understood that, for the sake of clarity, the impulses of order appearing from one period T1-T4 to the other pass to state 0, while in practice the data link 8 remains at the same level during each period T1-T4 and is read, by sampling, by an active edge, here falling, of the signal 7. As a result, the periods T1-T4 are limited to a few tens of nanoseconds, which makes it possible to order all of the memory points 6 in a much less time than the 10 milliseconds provided by the standards for printing of a line.

Figure 3 illustrates schematically how print register 5 is loaded Print register 5 includes, as indicated, 1728 data entries 8A of points memory 6 which, through doors 44 are connected to as many outputs of an input register 43 containing a series of signals binaries representing arranged numbers, encoded in this example, respectively representative of the gray intensities of points of a line to print.

A control circuit 41 is connected by means of a reading 42 of circuit 41, to input register 43 and command the opening of a determined number of doors 44, of position determined, this number of doors being a function of the numbers coded read in register 43, as explained below.

Hatched areas indicate blocks of bits transferred simultaneously, the position of the hatched areas of the register 43 corresponding to that of the hatched areas of the register 5, the presence of numbers other than zero, indicating gray, being marked by doubly blocks hatched. A coded number therefore corresponds to a bit of the same address of the printing register 5.

Figure 4 shows in more detail the diagram of Figure 3. The read circuit 42 is a multiplexer connected to the M outputs of the input register 43, with M = 1728 times the number of bits of each coded number.

As the numbers in register 43 are coded in this example, the output of the multiplexer 42 is connected to a transcoder circuit 47 which converts each coded number received into another number, not coded, of predetermined length, comprising bits at the head activation in state 1, in a number proportional to the intensity of the gray defined by the corresponding coded number, these non-coded numbers being stored in a memory 48. The memory 48 is here a buffer memory allowing the memorization of the bits representing several lines, these bits therefore being control data heating element activation 6. For clarity, memory 48 has not been shown in FIG. 3 and would therefore be interpose, with the transcoder circuit 47, between the outputs of the entry register 43 and doors 44.

The output of memory 48 also attacks a counter 49 which detects the presence of activation bits in 1 and emits a signal stop 50 when it reaches a predetermined threshold value N. The signal 50 has the effect of stopping an address counter 51 common driving the multiplexer 42 and the demultiplexer 10, connected output to the printing register 5 and here shown integrated into the circuit 41.

After complete writing of memory 48, a sequencer circuit 52 forces counter 51 to a determined address value, from value "a" at the beginning, and starts a cycle of a sequence of reading the first bits of each uncoded word from memory 48. If the bit read is in "1", this "1" is copied into the memory point 6 with the same address by addressing using the demultiplexer 10, and activation of the link 8 in the case, considered here, of use of type D flip-flops in the printing register 5. After N such copies, a decoder, or comparator, integrated at the output of the counter 49 emits the stop signal 50, which stops any new sending of "1" to the printing register 5, and the address AS of the last memory point 6 in "1" is memorized by the circuit sequencer 52 in an address memory 54 belonging here to the sequencer circuit 52. Circuit 52 then resets to "a" the counter 49 to start a new cycle, relating to second bits of the uncoded numbers of the memory 48 and, then, sends a command to deactivate memory points 6, address "one" to AS, for which the second bit of the number is not coded is in state 0.

Other following cycles, starting from the address "one", make it possible to process the following bits of the same uncoded numbers, which, at the end, deactivates the address heating elements 6 "a" to AS. Other such sequences of cycles, including the first starts at address AS + 1, determined from the address AS memorized by the sequencer circuit 52, used to control successively blocks of variable size (FIG. 3) comprising sets of N memory points 6 in the activated state, two of which are, as indicated, represented each time in FIG. 3, separated by any number of memory points 6 in the state inactive. The writing by the demultiplexer 10 is thus carried out under the controls addressing means (42, 49, 54) since it is the counter 49 which determines, by the stop signal 50, the addresses extremes of each block of bits.

The maximum instantaneous current is thus limited to N times 8 milliamps.

After writing the last black point of the line, the bits of the line next to be printed are read in the input register 43, to start a new printing, after advancing the support to to print.

• on mémorise, dans la mémoire 48, les positions des éléments chauffants 2 à activer,
• on en sélectionne, en en repérant et mémorisant les positions, un nombre N prédéterminé, que l'on active,
• et, après désactivation, on répète l'étape précédente pour des points à imprimer de positions non encore repérées, et ce,
• jusqu'à impression de la totalité des points de la ligne à imprimer, avant de faire avancer le support d'impression.

In summary, for printing a line of dots on the printing medium, heating elements 2 of the head 1 are activated, by carrying out the following steps:

• the positions of the heating elements 2 to be activated are stored in memory 48,
• we select, by locating and memorizing the positions, a predetermined number N, which we activate,
• and, after deactivation, the preceding step is repeated for dots to be printed from positions not yet identified, and this,
• until all the dots on the line to be printed have been printed, before feeding the printing medium.

In the second embodiment, shown in Figures 5 and 6, elements similar to or homologous to those of the first embodiment bear the same references, preceded by the hundred 1 and, if this is the case, by a dozen 1.

The print head 101 is a commercial head and the demultiplexer 10 is replaced, in this second form of realization, by a shift transfer register 110, here integrated at head 101, receiving in series the 1728 activation bits by sound data entry 111 at the rate of a clock signal 111B applied to a 111A clock serial input.

The buffer register 105 is logically divided into four blocks 112-115 of 432 memory points 106, each with a input for validating the outputs of memory points 106 connected in specific to a validation command link 116-119. An entrance clock 107 controls storage in all points memory 106. The validation command links 116-119 authorize the output of the bits contained in blocks 112-115 and, in the absence of validation, force at logic level 0 the outputs corresponding to amplifiers 104, which corresponds a lack of activation command of the heating elements 102.

The head 101 is controlled by a circuit 141, homologous to the circuit 41 and connected to the output of an input shift register 143. The input register 143 receives from the outside 1728 bits representing directly, in this example, the black or white dots of a line to be printed and transmits them to memory 148.

For transferring 1728 bits to the serial printing register 110, the operating principle of circuit 141 is similar to that of circuit 41, with the difference that it is each time transferred 1728 bits, including the N in the active state. To do this, the counter 151 receives from clock sequencer 153 the clock signal 111B, also applied, as shown, to shift register 110. The counter 151 systematically counts from 1 to 1728, without control by the stop signal 150, and is connected at output to sequencer 152.

The limit addresses of the areas of the line to be printed including the positions have already been processed by the sequencer 152 are memorized in a memory 154 of the sequencer 152 which thus acts as mask to determine the areas remaining to be treated.

A gate 153, here of the AND type, connects the output of memory 148 to entry 111 of shift register 110 and has two other inputs, control. The first control input is connected to the sequencer 152 and the second control input receives the signal 150, which is also applied to the sequencer 152 and which is memorized in counter 149 until it is reset to zero, in order to keep the door locked 153.

The operation of circuit 141 is as follows.

The 1728 bits of a line are transferred from memory 148 to entry 111 of shift register 110 through gate 153, at clock signal timing 111B. When counter 149 reaches the value N, the signal 150 locks the door 153, the output of which is blocks at logic level 0 until the end of the transfer of 1728 bits, which inhibits the transmission of activation bits in numbers excessive, at level "1". The signal 150 also controls the memorization by the sequencer 152, in the memory 154, of the AS address for which the bit transfer inhibition occurs of activation command in "1".

Thus, the heating elements 102 are individually activated by a serial transfer of activation commands and, for heating elements 102 which must remain inactive, we force, before transfer them, individual commands to an inactive state, 0.

After the counter 151 has reached the value 1728, the sequencer 152 controls, via a link 107A connected to the input 107 of the buffer register 105, the parallel loading of the bits of the register 110 in buffer register 105, when the duration necessary to print the previous points has passed. For the following printing, the sequencer 153 activates, here simultaneously, the four validation command links 116-119. A variant in the control of these connections is explained further.

After the above transfer cycle of 1728 bits including N in "1", another cycle is performed for N other activation bits. The counter 151 counts again from 1 to 1728. The sequencer 152 opens door 153 only from address AS + 1, calculated at from the content of memory 154, and signal 150 closes it then, as explained.

Thus, the transfer register 110 receives, from memory 148, activation command data and transfers it to the registry 105, and the sequencer 152 controls the transfer 110 and count, with the counter 149, the number heating elements 102 whose activation is controlled, for order its memory 154 for memorizing the addresses of heater positions 102 above and control the control data memory 148, and the sequencer 152 inhibits transfer register 110 if the above number exceeds the threshold N.

In an alternative embodiment, using the fact that the four validation command links 116-119 are separate there could be expected that the 149 activation bit counter transferred to register 110 performs such a count for each block 112-115. In this case, it would be transferred each time four times N activation bits, as long as they exist in one such number, to shift register 110 then to register buffer 105. The sequencer 153 would then activate successively, in any desired order, the validation command links 116-119. The number of transfers would thus be reduced by a factor of 4. In the event that less than N activation bits remain to be transferred towards a block 112-115, it could be expected that the counting of these bits "overflow" on one or more other blocks and that, by example, this count relates to two blocks 112-115, for which the individual validation command links 116-119 would then be simultaneously activated for printing.

In other words, the heating elements 102 are grouped in blocks of predetermined size and, if the number of elements heaters 102 to activate a block is less than the number predetermined N, before activation the selection is continued among the heating elements 102 to be activated from another block.

The transfer register 110, with the door 153, thus makes it possible to transfer line portions of sizes and positions respective predetermined and, in case of inhibition by the sequencer 152, it transmits to the command buffer register 105 print portions of white line.

Claims (6)

1. Method of controlling the line head of a thermal printing apparatus, in which, in order to print a line of dots on a printing medium, heating elements (2; 102) of the head (1; 101) are activated, characterised by the fact that

   the positions of the heating elements (2; 102) to be activated are memorised,

   from these are selected, their positions being located and memorised, a predetermined number (N) greater than the unit which are activated,

   and, after deactivation, the previous step is repeated for dots to be printed of positions not yet located, and this

   until all the dots of the lines to be printed have been printed, before advancing the printing medium.
2. Method according to claim 1, in which the heating elements (2; 102) are grouped in blocks (112-115) of predetermined size and, if the number of heating elements (2; 102) to be activated in one block is lower than said predetermined number (N), before activation, further selection is made from the heating elements (2; 102) to be activated in another block (112-115).
3. Method according to one of claims 1 and 2, in which the heating elements (2; 102) are activated individually by a serial transfer of activation controls and, for the heating elements (2; 102) which are to remain inactive, the individual controls are forced into an inactive state before being transferred.
4. Thermal printing apparatus to carry out the method of claim 1, having a line head (1; 101) comprising a plurality of heating elements (2; 102), a register (5; 105) for controlling the activation of the heating elements (2; 102) and a transfer register (10; 110) arranged to receive, from memorizing means (48; 148), activation control data and to transfer these data to the control register (5; 105), and sequencer means (51, 52, 151, 152, 153) for controlling the transfer register (10; 110) of the head (1; 101), apparatus characterised by the fact that the sequencer means (51, 52; 151, 152, 153) are arranged to count the number of heating elements (2; 102) whose activation is controlled, to control means (54; 154) for memorizing the addresses of positions of said heating elements (2; 102) and for checking the means for memorizing control data (48; 148), and to inhibit the transfer register (10; 110) if said number exceeds a threshold (N) higher than the unit.
5. Apparatus according to claim 4, in which the transfer register (110) is arranged to transfer line portions of respective predetermined sizes and positions and, where there is inhibition by the sequencer means (152, 153, 154), to transmit to the control register (105) portions of white line.
6. Apparatus according to one of claims 4 and 5, in which a memory buffer (48, 148) is provided for memorizing activation control data relating to several lines.

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