EP0638429A1 - Method for controlling the line head of a thermal printing apparatus and associated printer - Google Patents

Abstract

Method for controlling a line head of a thermal printing apparatus, in which, to print a line of dots on a printing support, heating elements (2; 102) of the head (1; 101) are activated, in which method - the positions of the heating elements (2; 102) to be activated are stored, - a predetermined number (N) is selected from these, with their positions being identified and stored, and is activated, - and, after deactivation, the preceding step is repeated for dots to be printed in positions not yet identified, this taking place - until all the dots of the line to be printed have been printed, before the printing support is advanced. Use in facsimile machines. <IMAGE>

Description

A thermal printing apparatus, such as a facsimile machine, has a printhead in which a plurality of resistive heating elements can be activated to effect printing of a line.

Each heating element is connected to a power source and individually controlled to print or not a black dot. In a fax machine, generally, each heating element is supplied at 24 volts and has a resistance of approximately 3000 ohms.

Given their number, the total current consumption of the heating elements, if they had to be activated simultaneously, would be very high. Still by way of example, around 1800 elements would consume around 15 amps. This is why, in many fax machines, the heating elements are grouped into four blocks, for example of approximately 450 heating elements, activated successively.

The power supply should therefore only supply a maximum current limited to approximately 3.5 amperes for printing a block of black dots. However, such a power source is still too bulky and expensive.

The present invention aims to reduce the maximum supply current.

• on mémorise les positions des éléments chauffants à activer,
• on en sélectionne, en en repérant et mémorisant les positions, un nombre prédéterminé, que l'on active,
• et, après désactivation, on répète l'étape précédente pour des points à imprimer de positions non encore repérées, et ce,
• jusqu'à impression de la totalité des points de la ligne à imprimer, avant de faire avancer le support d'impression.

To this end, it relates to a method for controlling a line head of a thermal printing apparatus, in which, for the printing of a line of dots on a printing medium, heating elements of the head, characterized by the fact that

• the positions of the heating elements to be activated are memorized,
• we select, by locating and memorizing the positions, a predetermined number, which we activate,
• and, after deactivation, the preceding step is repeated for dots to be printed from positions not yet identified, and this,
• until all the dots on the line to be printed have been printed, before feeding the printing medium.

Thus, the maximum supply current can be chosen by an appropriate choice of the number of simultaneously activated heating elements. Note that this number can be very limited without restricting the average printing speed of a line, since each selected heating element is activated. In other words, the heating elements are no longer activated by blocks of predetermined size, as in the printing apparatuses of the prior art, but by blocks of variable size with a predetermined maximum number of activated heating elements and an indeterminate and variable number of inactive heating elements. Thus, instead of reserving printing durations for blocks of predetermined size, it is the information to be printed, that is to say the presence of black dots, which defines the size of the blocks and thus allows 'optimize printing by "ignoring" the presence of blanks.

Preferably, the heating elements are grouped into blocks of predetermined size, and, if the number of heating elements to be activated in a block is less than said predetermined number, before activation, the selection is continued among the heating elements to be activated. another block.

The invention also relates to a thermal printing apparatus for implementing the method of the invention, comprising a line head, comprising a plurality of heating elements, a control register for activation of the heating elements and a transfer register arranged to receive, from storage means, activation control data and transfer them to the control register, and sequencing means to control the transfer register the head, an apparatus characterized in that the sequencing means are arranged to count the number of heating elements the activation of which is controlled, to control means for memorizing addresses of the positions of said heating elements and for controlling the memorizing means control data, and to inhibit the transfer register if said number exceeds a threshold.

• la figure 1 est un schéma par blocs d'une tête d'impression à chargement parallèle dans la première forme de réalisation,
• la figure 2 est un diagramme des temps de signaux de commande de la tête d'impression de la figure 1,
• la figure 3 est un schéma simplifié par blocs de la tête d'impression ci-dessus et d'une logique de commande de cette tête,
• la figure 4 est un schéma plus détaillé que celui de la figure 3,
• la figure 5 est un schéma par blocs d'une tête d'impression à chargement série dans la seconde forme de réalisation et
• la figure 6 est un schéma par blocs de la tête d'impression de la figure 5 et d'une logique de commande de cette tête.

The invention will be better understood with the aid of the following description of two preferred embodiments of the line head thermal printing apparatus for implementing the method of the invention, with reference to the appended drawing in which :

• FIG. 1 is a block diagram of a print head with parallel loading in the first embodiment,
• FIG. 2 is a diagram of the times of control signals of the print head of FIG. 1,
• FIG. 3 is a simplified block diagram of the above print head and of a control logic for this head,
• FIG. 4 is a more detailed diagram than that of FIG. 3,
• FIG. 5 is a block diagram of a print head with serial loading in the second embodiment and
• Figure 6 is a block diagram of the print head of Figure 5 and a control logic of this head.

The thermal printing apparatus of the invention comprises, in its first embodiment, a thermal head 1 shown in FIG. 1, of which a row of 1,728 printing heating elements, generally referenced 2, cooperates with an ink ribbon not shown thermal transfer printing, applied to a printing medium consisting of paper, driven against the head 1. The printing elements 2, having a resistance of 3000 ohms, are connected to a supply wire 3 in +24 volts and are controlled by individual amplifiers / switches 4, operating as inverters and absorbing the 8 milliamps passing through each printing element 2 when it is activated. The amplifiers 4 are each controlled by an own activation bit stored in a memory point 6, here of the flip-flop type "D", of a print control buffer register 5 with parallel inputs and outputs comprising an ordered row of 1728 such memory points 6. A demultiplexer circuit 10 comprises eleven address inputs, referenced 11, and 1728 outputs respectively connected to 1728 clock inputs 7 belonging respectively to 1728 memory points 6.

The 1728 memory points 6 respectively comprise 1728 data bit inputs 8A connected to a common link 8. An input 9 is provided here, connected to all the memory points 6, allowing all of them to be reset simultaneously, that is to say ie their forcing in the same predetermined state, here a logic level 0, called inactive, for which the heating elements 2 are not supplied with current through the amplifiers 4.

The flip-flops "D" of the memory points 6 can for example be produced by means of integrated circuits, in TTL or CMOS technology, of the type 7474 while the demultiplexer 10 can, likewise, be produced by means of several integrated circuits of the type 74154 or 74HC154 and a logic for selecting only one of them, acting on an address input then serving as a validation input, the corresponding outputs of circuit 74 (HC) 154 being then unused. It could have been provided for flip-flops of type JK, divider by two, and not flip-flops "D", which would have avoided the need for the data link 8 since each addressing of such a flip-flop divider would be enough to make it change d 'state.

The above integrated circuits are available from TEXAS INSTRUMENTS or MOTOROLA companies.

To control the activation of a heating element 2, a corresponding address in the row is applied for a short time to the address inputs 11, the link 8 having previously been set to logic level 1 (FIG. 2). The output of the demultiplexer 10 connected to the clock input 7 of the memory point 6 of the heating element 2 considered provides a pulse during the period of application of the address to the address inputs 11, which has for effect of opening a door, not shown, for individual activation of a heating element 2, which reads the logic level of the data link 8 and controls the storage, in the memory point 6 concerned, of a bit having the logic level 1 present on data link 8.

The deactivation of a memory point 6 is carried out in the same way, the link 8 then being brought to logic level 0.

The bit contained in each memory point 6 is thus an activation bit for the heating elements 2, which can have two states, namely an active state, here the logic level 1, and an inactive state, here the logic level 0.

Thus, in FIG. 2, which is a time diagram of the above signals, the memory point 6 of address "one" is addressed, for a short time within a period T1 of a sequence Ti (i integer = 1 to P), by setting the least significant address bit A0 applied to the address inputs 11 to 1, the other bits, not all of which are represented, being at level 0, which generates a pulse on the input clock 7 of memory point 6 of address "one", the logic level or state of which is represented by signal 21.

During the following period T2, another memory point 6, here of address "three", is addressed, the two least significant address bits, A0 and A1, passing to level 1 to provide the binary address 11, that is to say three in decimal. The signal 23 represents the logic level of the bit contained in the memory point of address "three". The initial states of memory points 6 have here been assumed to be state 0.

In this example, the address memory point "three" returns to 0 during the period T3, while the address memory point "one" returns to 0 during the period T4. There is thus simultaneous, or interleaved, management of several memory points 6, by sharing the time t into slices or periods Ti.

It will be understood that, for the sake of clarity, the control pulses appearing from one period T1-T4 to the other pass back to state 0, while in practice the data link 8 remains at the same level during each period T1-T4 and is read, by sampling, by an active edge, here falling, of the clock signal 7. As a result, the periods T1-T4 are limited to a few tens of nanoseconds, which makes it possible to control the whole memory points 6 in a much less time than the 10 milliseconds provided by the standards for printing a line.

FIG. 3 schematically illustrates the manner in which the printing register 5 is loaded. The printing register 5 comprises, as indicated, 1728 data entries 8A of memory points 6 which, through doors 44 are connected to as many outputs of an input register 43 containing a series of binary signals representing arranged numbers, coded in this example, respectively representative of the gray intensities of the points of a line to be printed.

A control circuit 41 is connected by means of a read circuit 42 of the circuit 41, to the input register 43 and controls the opening of a determined number of doors 44, of determined position, this number of doors being a function coded numbers read from register 43, as explained below.

The hatched areas indicate blocks of bits transferred simultaneously, the position of the hatched areas of the register 43 corresponding to that of the hatched areas of the printing register 5, the presence of numbers other than zero, indicating gray, being marked by double blocks. hatched. A coded number therefore corresponds to a bit of the same address of the printing register 5.

FIG. 4 shows in more detail the diagram of FIG. 3. The read circuit 42 is a multiplexer connected to the M outputs of the input register 43, with M = 1728 times the number of bits of each coded number.

As the numbers in register 43 are coded in this example, the output of the multiplexer 42 is connected to a transcoder circuit 47 which converts each coded number received into another, non-coded number, of predetermined length, comprising at the start activation bits in state 1, in a number proportional to the intensity of the gray defined by the corresponding coded number, these non-coded numbers being memorized in a memory 48. The memory 48 is here a buffer memory allowing the memorization of the bits representing several lines, these bits therefore being activation control data for the heating elements 6. For clarity, the memory 48 has not been shown in FIG. 3 and would therefore have to be interposed, with the transcoder circuit 47, between the outputs of the register entrance 43 and doors 44.

The output of memory 48 also drives a counter 49 which detects the presence of activation bits in 1 and sends a stop signal 50 when it reaches a predetermined threshold value N. The signal 50 has the effect of stopping a common addressing counter 51 controlling the multiplexer 42 and the demultiplexer 10, connected at output to the printing register 5 and here shown integrated into the circuit 41.

After complete writing of the memory 48, a sequencer circuit 52 forces the counter 51 to a determined address value, of value "one" at the start, and starts a cycle of a reading sequence of the first bits of each uncoded word from memory 48. If the bit read is at "1", this "1" is copied into memory point 6 with the same address by addressing by means of the demultiplexer 10, and activation of the link 8 in the case considered here, of use of type D flip-flops in the printing register 5. After N such copies, a decoder, or comparator, integrated at the output of the counter 49 emits the stop signal 50, which stops any new sending of "1 "to the printing register 5, and the address AS of the last memory point 6 at" 1 "is stored by the sequencer circuit 52 in an address memory 54 belonging here to the sequencer circuit 52. The circuit 52 then returns to "one" the counter 49 to start a new cycle, relating to the second bits of the non-coded numbers of the memory 48 and, then, sends a command to deactivate the memory points 6, of address "one" to AS, for which the second bit of the non-coded number is in the state 0.

Other following cycles, starting from the address "one", make it possible to process the following bits of the same uncoded numbers, which, in the end, ensures the deactivation of the heating elements 6 of address "one" at AS. Other such sequences of cycles, the first of which begins at the address AS + 1, determined from the address AS stored by the sequencer circuit 52, make it possible to successively control blocks of variable size (FIG. 3) comprising sets of N memory points 6 in the activated state, two of which are, as indicated, shown each time in FIG. 3, separated by any number of memory points 6 in the inactive state. The writing by the demultiplexer 10 is thus carried out under the controls addressing means (42, 49, 54) since it is the counter 49 which determines, by the stop signal 50, the extreme addresses of each block of bits.

The maximum instantaneous current is thus limited to N times 8 milliamps.

After writing the last black point of the line, the bits of the next line to be printed are read in the input register 43, to start a new printing, after advancing the medium to be printed.

• on mémorise, dans la mémoire 48, les positions des éléments chauffants 2 à activer,
• on en sélectionne, en en repérant et mémorisant les positions, un nombre N prédéterminé, que l'on active,
• et, après désactivation, on répète l'étape précédente pour des points à imprimer de positions non encore repérées, et ce,
• jusqu'à impression de la totalité des points de la ligne à imprimer, avant de faire avancer le support d'impression.

In summary, for printing a line of dots on the printing medium, heating elements 2 of the head 1 are activated, by carrying out the following steps:

• the positions of the heating elements 2 to be activated are stored in memory 48,
• we select, by locating and memorizing the positions, a predetermined number N, which we activate,
• and, after deactivation, the preceding step is repeated for dots to be printed from positions not yet identified, and this,
• until all the dots on the line to be printed have been printed, before feeding the printing medium.

In the second embodiment, represented in FIGS. 5 and 6, the elements similar or else homologous to those of the first embodiment bear the same references, preceded by the hundred 1 and, if this is the case, with a ten 1.

The print head 101 is a commercial head and the demultiplexer 10 is replaced, in this second embodiment, by a shift transfer register 110, here integrated at the head 101, receiving in series the 1728 activation bits by its data input 111 at the rate of a clock signal 111 B applied to a serial clock input 111A.

The buffer register 105 is logically divided into four equal blocks 112-115 of 432 memory points 106, each comprising an input for validating the outputs of the memory points 106 directly connected to a validation command link 116-119. A clock input 107 controls the storage in all the memory points 106. The validation command links 116-119 authorize the output of the bits contained in the blocks 112-115 and, in the absence of validation, force at logic level 0 the corresponding outputs connected to the amplifiers 104, which corresponds to a lack of activation command for the heating elements 102.

The head 101 is controlled by a circuit 141, homologous to the circuit 41 and connected to the output of an input shift register 143. The input register 143 receives from the outside 1728 bits representing directly, in this example, the black or white points of a line to be printed and transmits them to memory 148.

For the transfer of the 1728 bits to the printing serial register 110, the operating principle of the circuit 141 is similar to that of the circuit 41, with the difference that it is each time transferred 1728 bits, including the N to l active state. To do this, the counter 151 receives from the sequencer 153 the clock signal 111B, also applied, as indicated, to the shift register 110. The counter 151 systematically counts from 1 to 1728, without control by the stop signal 150, and is connected at output to the sequencer 152.

The limit addresses of the areas of the line to be printed whose positions have already been processed by the sequencer 152 are stored in a memory 154 of the sequencer 152 which thus acts as a mask to determine the areas remaining to be processed.

A gate 153, here of the AND type, connects the output of the memory 148 to the input 111 of the shift register 110 and includes two other inputs, for control. The first control input is connected to the sequencer 152 and the second control input receives the signal 150, which is also applied to the sequencer 152 and which is memorized in the counter 149 until it is reset to zero, in order to maintain door locking 153.

The operation of circuit 141 is as follows.

The 1728 bits of a line are transferred from memory 148 to input 111 of shift register 110 through gate 153, at the rate of clock signal 111B. When the counter 149 reaches the value N, the signal 150 locks the door 153, the output of which blocks at logic level 0 until the end of the transfer of the 1728 bits, which inhibits the transmission of activation bits in excessive number , at level "1". The signal 150 also controls the storage by the sequencer 152, in the memory 154, of the address AS for which the inhibition of the transfer of activation command bits at "1" occurs.

Thus, the heating elements 102 are individually activated by a serial transfer of the activation commands and, for the heating elements 102 which must remain inactive, the individual commands are forced, before transferring them, to an inactive state, 0.

After the counter 151 has reached the value 1728, the sequencer 152 commands, by a link 107A connected to the input 107 of the buffer register 105, the parallel loading of the bits of the register 110 in the buffer register 105, when the time necessary for the printing of the previous points has passed. For the following printing, the sequencer 153 activates, here simultaneously, the four validation command links 116-119. A variant in the control of these links is explained below.

After the above transfer cycle of 1728 bits including N in "1", another cycle is performed for N other activation bits. The counter 151 again counts from 1 to 1728. The sequencer 152 opens the door 153 only from the address AS + 1, calculated from the content of the memory 154, and the signal 150 then closes it, as explained.

Thus, the transfer register 110 receives, from memory 148, activation control data and transfers them to the control register 105, and the sequencer 152 controls the transfer register 110 and counts, with the counter 149, the number of heating elements 102 whose activation is controlled, to control its memory 154 for memorizing the addresses of positions of the heating elements 102 above and for controlling the memory 148 for control data, and the sequencer 152 inhibits register of transfer 110 if the above number exceeds the threshold N.

In an alternative embodiment, using the fact that the four validation control links 116-119 are separate, provision could be made for the counter 149 of activation bits transferred to the register 110 to carry out such a counting for each block 112- 115. In this case, it would be transferred each time N activation bits four times, insofar as they exist in such a number, to the shift register 110 then to the buffer register 105. The sequencer 153 would then activate successively, in any desired order, validation command links 116-119. The number of transfers would thus be reduced by a factor of 4. In the event that less than N activation bits remain to be transferred to a block 112-115, provision could be made for the counting of these bits "to overflow" on a or several other blocks and that, for example, this count relates to two blocks 112-115, for which the individual validation command links 116-119 would then be simultaneously activated for printing.

In other words, the heating elements 102 are grouped into blocks of predetermined size and, if the number of heating elements 102 to be activated by a block is less than the predetermined number N, before activation, the selection is continued among the heating elements. 102 to activate from another block.

The transfer register 110, with the gate 153, thus makes it possible to transfer portions of line of predetermined sizes and respective positions and, in the event of inhibition by the sequencer 152, it transmits to the buffer buffer for the print command 105 portions of white line.

Claims (6)

Method for controlling a line head of a thermal printing apparatus, in which, for printing a line of dots on a printing medium, heating elements (2; 102) of the head are activated (1; 101), characterized in that - the positions of the heating elements (2; 102) to be activated are memorized, - a predetermined number (N) is selected, by locating and memorizing the positions, which is activated, - and, after deactivation, the previous step is repeated for dots to be printed from positions not yet identified, and this, - until all the dots on the line to be printed have been printed, before advancing the printing medium. Method according to claim 1, in which the heating elements (2; 102) are grouped into blocks (112-115) of predetermined size and, if the number of heating elements (2; 102) to be activated by a block is less at said predetermined number (N), before activation, the selection is continued among the heating elements (2; 102) to be activated from another block (112-115). Method according to one of claims 1 and 2, in which the heating elements (2; 102) are individually activated by a serial transfer of activation commands and, for the heating elements (2; 102) which are to remain inactive, force, before transferring them, the individual commands to an inactive state. Thermal printing apparatus for implementing the method of claim 1, comprising a line head (1; 101), comprising a plurality of heating elements (2; 102), a control register (5; 105) activation of elements heaters (2; 102) and a transfer register (10; 110) arranged to receive, from storage means (48; 148), activation command data and transfer them to the command register (5; 105) , and sequencing means (51, 52; 151, 152, 153) for controlling the transfer register (10; 110) of the head (1; 101), apparatus characterized in that the sequencing means (51, 52; 151, 152, 153) are arranged to count the number of heating elements (2, 102) whose activation is controlled, to control means (54; 154) for memorizing addresses of the positions of said heating elements (2; 102) and control means for storing control data (48; 148), and for inhibiting the transfer register (10; 110) if said number exceeds a threshold (N). Apparatus according to claim 4, in which the transfer register (110) is arranged for transferring line portions of predetermined respective sizes and positions and for, in the event of inhibition by the sequencing means (152, 153, 154), transmit portions of white line to the control register (110). Apparatus according to one of claims 4 and 5, in which a buffer memory (48; 148) for storing activation control data relating to several lines is provided.

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