EP0638428B1 - Thermal printer with line-head - Google Patents

Abstract

Thermal printer with line head comprising a plurality of printing heating elements (2) designed, under the control of individual activation means (7, 8) and by means of memory dots (6; 46) of a printing register (5; 45), to print successive lines of dots on a support to be printed which is driven in transit against the head (1), the said printer being characterised in that it comprises means (10; 40) for the individual character addressing of the memory dots (6; 46). - Use in facsimile machines. <IMAGE>

Description

The present invention relates to a printing apparatus thermal line head, such as a fax machine or even a simple printer.

A "line" thermal print head is used for printing almost all the points of a line simultaneously, which achieves high print speed.

Used for example in a fax machine, the head has a large number of heating elements that print thermal under the command of as many activation bits. These bits are memorized, the time of printing a line, in a shift register with as many commanding outputs the heating elements individually. The points of the line could then be, if that is the case, be printed simultaneously, depending on the activation bits.

Like printing a large number of dots simultaneously would generate a current consumption which would exceed the authorized speed of the fax machine, the register controlling the heating elements is logically cut in blocks which are activated one after the other to print segments, or portions, of line together constituting the line to print.

Such an arrangement multiplies the printing time by one line, which harms the intended goal which is, by a line impression, to obtain a high printing speed.

The present invention aims to be able to increase this speed printing.

To this end, it relates to a thermal printing apparatus with line head comprising a plurality of heating elements printers arranged to print successive lines of dots on a print medium dragged against the head, the heating elements being, via points memories of a printing register, controlled by individual activation means, apparatus characterized by the fact that the memory points are arranged to be individually deactivated one by one by the addressing means.

It is thus possible, when the number of dots to be printed on a line is limited, print all the dots simultaneously, whereas, in the prior art, a fixed period was reserved for each control block, even if it had only one point to print.

In addition, the heating time of each heating element can be modulated, that is to say that the head allows to restore black dots whose size depends on this duration and which appear, with their edges remaining white, like grays adjustable intensity.

To minimize the number of addressing links, it is preferable that the write addressing means include a memory point addressing demultiplexer.

To print black dots smaller than that of a pixel (image element), equivalent to gray, the device may include means for controlling means write addressing arranged to receive input signals respectively representative of gray intensities of dots to print. But, for the same purpose, the means of addressing and activation command can be arranged to simultaneously manage the heating time settings for several printing elements.

• la figure 1 est un schéma par blocs de la tête d'impression dans la première forme de réalisation,
• la figure 2 est un diagramme des temps de signaux de commande de la tête d'impression de la figure 1,
• la figure 3 est un schéma par blocs de la tête d'impression ci-dessus et d'une logique de commande de cette tête,
• la figure 4 est un schéma par blocs de la seconde forme de réalisation,
• la figure 5 est un schéma plus détaillé que celui de la figure 4 et
• la figure 6 illustre l'évolution, en fonction du temps t, de l'état de points mémoire d'activation.

The invention will be better understood using the following description of two preferred embodiments of the line head thermal printing apparatus of the invention, with reference to the attached drawing in which:

• FIG. 1 is a block diagram of the print head in the first embodiment,
• FIG. 2 is a diagram of the times of control signals of the print head of FIG. 1,
• FIG. 3 is a block diagram of the above print head and of a control logic for this head,
• FIG. 4 is a block diagram of the second embodiment,
• Figure 5 is a more detailed diagram than that of Figure 4 and
• FIG. 6 illustrates the evolution, as a function of time t, of the state of activation memory points.

The thermal printing apparatus of the invention comprises, in its first embodiment, a thermal head 1 shown in Figure 1, including a row of 1728 heating elements printing, generally referenced 2, cooperates with a ribbon thermal transfer printing ink not shown, applied to a print medium consisting of paper, driven scrolling against the head 1. The printing elements 2 are connected to a supply wire 3 at +24 volts and are controlled by individual amplifiers / switches 4 each controlled by its own activation bit stored in a memory point 6 here of the flip-flop type "D", from a print buffer register 5 to parallel inputs and outputs with an ordered row of 1728 such memory points 6. A demultiplexer circuit 10 comprises eleven address entries, referenced 11, and 1,728 outputs respectively connected to 1728 clock inputs 7 belonging respectively at 1728 memory points 6.

The 1728 memory points 6 respectively comprise 1728 data bit inputs 8A connected to a common link 8. It an input 9 is here provided, connected to all the memory points 6, allowing the simultaneous reset of all, that is to say their forcing in the same predetermined state, here a logic level 0, says inactive, for which the heating elements 2 are not supplied with current through the amplifiers 4.

The flip-flops "D" of the memory points 6 can for example be realized by means of integrated circuits, in TTL technology or CMOS, of type 7474 while demultiplexer 10 can, from even, be realized by means of several integrated circuits of the type 74154 or 74HC154 and a logic of selection of only one of them, acting on an address entry then serving as an entry for validation, the corresponding outputs of circuit 74 (HC) 154 being then unused. JK type flip-flops could have been provided, divider by two, not flip-flops "D", which would have avoided the need for data link 8 since each addressing of such a divider would be enough to make it change state.

The above integrated circuits are available from TEXAS INSTRUMENTS or MOTOROLA companies.

To control the activation of a heating element 2, a corresponding address in the row is applied a short instant at address entries 11, link 8 having previously been upgraded to logic level 1 (Figure 2). Leaving the demultiplexer 10 connected to the clock input 7 of the memory point 6 of the heating element 2 considered provides a pulse during the duration of address application to address entries 11, which has to open an activation door, not shown heating element 2, which reads the logic level of the data link 8 and controls storage, in the point memory 6 concerned, of a bit having logic level 1 present on the data link 8.

The deactivation of a memory point 6 is carried out in the same way, the link 8 is then brought to logic level 0.

The bit contained in each memory point 6 is thus a bit activation of the heating elements 2, which can have two states, know an active state, here logic level 1, and an inactive state, here the logic level 0.

So in Figure 2, which is a time diagram of the signals above, the memory point 6 of address "one" is addressed, a short instant within a period T1 of a sequence Ti (i integer = 1 to P), by setting the least significant address bit A0 applied to the address entries 11, the other bits, not all of which are represented, being at level 0, which generates a pulse on the clock input 7 of memory point 6 of address "one", including the logic level, or state, is represented by signal 21.

During the following period T2, another memory point 6, here address "three", is addressed, the two address bits of weight weak, A0 and A1, passing to level 1 to provide the binary address 11, three in decimal. Signal 23 represents the logic level of the bit contained in the memory point of address "three". The states initials of memory points 6 have here been assumed to be state 0.

In this example, the address memory point "three" returns to 0 during the period T3, while the address memory point "one" returns to 0 during the period T4. There is thus simultaneous, or interleaved, management of several memory points 6, by sharing the time t into slices or periods Ti.

It will be understood that, for the sake of clarity, the impulses of order appearing from one period T1-T4 to the other pass to state 0, while in practice the data link 8 remains at the same level during each period T1-T4 and is read, by sampling, by an active edge, here falling, of the signal 7. As a result, the periods T1 -T4 are limited to a few tens of nanoseconds, which allows order all memory points 6 in good time less than the 10 milliseconds provided for by the standards for printing a line.

Setting the duration of activation of each heating element 2 can thus be carried out by sending an order activation followed, after the desired duration, by sending a deactivation command resetting the bit to 0 activation. Likewise, provision could have been made for amplifiers 4 or the memory points 6 are inverters, or although link 9 allows to force all the bits of the printing register 5. In this case, all the bits of the register 5 are simultaneously set to the active state at the start line printing, even if it means deactivating them individually almost instantly if they correspond to white dots, or, if not, after the desired printing time.

Setting the duration of activation of the heating elements 2 allows to choose the temperature reached by them, as well as the time of thermal diffusion to ink and time of transfer when the ink has melted.

Therefore, the adjustment of the activation time allows to modulate the amount of ink deposited on the paper at each point, i.e. get small black dots each surrounded of a remaining white area, which simulates grays, intensities independent from one point to another.

The circuit 31 of FIG. 3 ensures the control of the multiplexer 10 by issuing the desired addresses in a timely manner. For that, a reception link 32 provides a series of signals binaries representing numbers, coded in this example, arranged in the order of the dots to be printed, respectively representative of the gray intensities of the points from a line to to print.

In this example, each number is proportional to the intensity of gray desired, the number "zero" indicating the presence of a point white and the coding corresponds to the classic binary coding. The circuit 31 stores this sequence of numbers in a register with offset 33 with parallel outputs then reads them successively in one partial scanning cycle by means of a multiplexer 34, addressed by a counter 35 advancing at the rate of a time base 39 of period Ti, until finding a number other than zero, indicating a gray to print. The address of counter 35, which corresponds to the relative position of the number in the row, i.e. the position or address of memory point 6 considered, is applied to address inputs 11 of the demultiplexer 10, while the link 8 is set to level 1 by circuit 31, to activate the point corresponding memory 6, as explained above. The process continues until the last number. The moments activation of memory points 6, provided by the time base 39, could be stored with each number in register 33, but in this case, being very close, only the instant TA of the last activation is noted.

For deactivation of the heating elements 6, the multiplexer 34 continues partial scan cycles of register 33 and a arithmetic circuit 37 of circuit 31 subtracts the value TA memorized of the value tj of the current instant, provided by the base 39, and compare the result to the corresponding coded number from register 33. If this number is reached or exceeded, a deactivation command is issued, as explained above.

In the second embodiment shown schematically in FIG. 4, a printing register 45, controlling heating elements in the same way as the register 5 of the previous example, contains 1728 entries of memory point data 46 which through doors 44 are connected to as many outputs of an input register 43 containing, like register 33, a series of binary signals representing arranged numbers, also coded in this example, respectively representative of the gray intensities of the points a line to print.

A control circuit 41 is connected by means of a reading 42 of circuit 41, to input register 43 and command the opening of a determined number of doors 44, of position determined, this number of doors being a function of the numbers coded read in register 43, as explained below.

Hatched areas indicate blocks of bits transferred simultaneously, the position of the hatched areas of the register 43 corresponding to that of the hatched areas of the register 45, the presence of numbers other than zero, indicating gray, being marked by doubly blocks hatched. A coded number therefore corresponds to a bit of the same address of the printing register 45.

Figure 5 shows in more detail the diagram of Figure 4. The read circuit 42 is a multiplexer connected to the M outputs of the input register 43, with M = 1728 times the number of bits of each coded number.

As the numbers in register 43 are coded in this example, the output of the multiplexer 42 is connected to a transcoder circuit 47 which converts each coded number received into another number, not coded, of predetermined length, comprising bits at the head activation in state 1, in a number proportional to the intensity of the gray defined by the corresponding coded number, these non-coded numbers being stored in a memory 48. For clarity, the memory 48 has not been shown in FIG. 4 and would therefore be interpose, with the transcoder circuit 47, between the outputs of the entry register 43 and doors 44.

FIG. 6 represents three uncoded numbers, of five bits each, relating to three points 46-1, 46-2 and 46-5, the abscissa axis carrying the rank P of the memory points 46 and the ordinate axis carrying time t . Point 46-1 has only one bit in 1, so that gray will be light, while point 46-2, having a three-bit number in 1, will have a medium gray and point 46-5 , with 5 bits in 1, will be black because activated for the maximum duration X provided.

The output of memory 48 also attacks a counter 49 which detects the presence of activation bits in 1 and emits a signal 50 when it reaches a predetermined value N. Signal 50 has the effect of stopping a common addressing counter 51 driving the multiplexer 42 and a demultiplexer 40, equivalent to the demultiplexer 10, connected at output to the printing register 45.

After complete writing of memory 48, a sequencer circuit 52 forces counter 51 to a determined address value, from value "a" at the beginning, and starts a cycle of a sequence of reading the first bits of each uncoded word from memory 48. If the bit read is in "1", this "1" is copied into the memory point 46 of the same address through the demultiplexer 40. After N such copies, the counter 49 sends the stop signal 50, which stops any new sending of "1" to the printing register 45, and the AS address of the last 6 in 1 memory point is memorized by the circuit 52. Circuit 52 then resets counter 49 to "one" for start a new cycle, relating to the second bits of uncoded numbers from memory 48 and then sends a command to deactivate memory points 46, address "one" to AS, for which the second bit of the uncoded number is at state 0, which is the case for point 46-1.

Other following cycles, starting from the address "one", make it possible to process the following bits of the same uncoded numbers, which, at the end, deactivates the heating elements 46 address "one" to AS. Other such sequences of cycles, including the first starts at address AS + 1, allow to order successively blocks of variable size (FIG. 4) comprising sets of N memory points 46 in the activated state, two of which are, as indicated, represented each time in FIG. 4, separated by any number of memory points 46 in the state inactive. The writing by the demultiplexer 40 is thus carried out under the controls addressing means (42, 49) since it is the counter 49 which determines, by the stop signal 50, the addresses extremes of each block of bits.

After writing the last black point of the line, the bits of the line next to be printed are read in the input register 43, to start a new impression.

Claims (8)

1. Thermal printer with line-head comprising a plurality of heating printing elements (2) arranged in order to print successive lines of dots on a printing support moved against the head (1), heating elements being, through the intermediary of memory points (6; 46) of a printing register (5; 45), controlled by individual activation means (7, 8), which printer is characterised by the fact that the memory points (6; 46) are arranged in order to be individually deactivated one by one by the addressing means (10; 40).
2. Printer according to Claim 1, in which the writing addressing means comprise a demultiplexer (10; 40) for addressing memory points (6; 46).
3. Printer according to one of Claims 1 and 2, in which the printing register (5; 45) comprises an input (9) for controlling the forcing of memory points (6) into the same predetermined state.
4. Printer according to one of Claims 1 to 3, in which means (31; 41; 47, 48, 49, 51) are provided for controlling the writing addressing means (40) arranged to receive at the input signals respectively representative of the intensities of grey of the dots to be printed.
5. Printer according to one of Claims 1 to 3, in which means (31) are provided for controlling the writing addressing means (10) and the activation control means (7, 8) comprise a connection (8) connected to the memory points (6) of the register (5).
6. Printer according to one of Claims 4 and 5, in which the addressing and activation control means (31; 41) are arranged to simultaneously manage the regulations of the duration of heating of several printing elements (2).
7. Printer according to one of Claims 4 to 6, in which reading addressing means (42, 49, 51) are provided arranged for reading, in an input memory (43; 48), a predetermined number of activation bits at an active state of a line to be printed and the means (51; 52) for controlling the writing addressing means (40) are arranged in order to select said activation bits under the command of the reading addressing means (42, 49, 51) and for controlling the transfer of said activation bits, from the input memory (43) to the printing register (45).
8. Printer according to Claim 7, in which a counter (51) is provided for controlling the reading addressing means (42) and the writing addressing means (40) simultaneously.

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