EP0638428A1 - Thermal printer with line-head - Google Patents

Abstract

Thermal printer with line head comprising a plurality of printing heating elements (2) designed, under the control of individual activation means (7, 8) and by means of memory dots (6; 46) of a printing register (5; 45), to print successive lines of dots on a support to be printed which is driven in transit against the head (1), the said printer being characterised in that it comprises means (10; 40) for the individual character addressing of the memory dots (6; 46). - Use in facsimile machines. <IMAGE>

Description

The present invention relates to a line head thermal printing apparatus, such as a fax machine or even a simple printer.

A "line" thermal print head is used to print almost all of the dots on a line, thereby achieving high print speed.

Used for example in a fax machine, the head includes a large number of heating elements which carry out thermal printing under the control of as many activation bits. These bits are memorized, the time of printing a line, in a shift register with as many outputs individually controlling the heating elements. The points of the line could then, if this is the case, be printed simultaneously, according to the activation bits.

As the printing of a large number of dots simultaneously would generate a current consumption which would exceed the authorized speed of the fax machine power supply, the register controlling the heating elements is logically divided into blocks which are activated one after the other to print line segments, or portions, together constituting the line to be printed.

Such an arrangement correspondingly multiplies the printing time of a line, which is detrimental to the aim which is, by line printing, of obtaining a high printing speed.

The present invention aims to be able to increase this printing speed.

To this end, it relates to a line head thermal printing apparatus comprising a plurality of printing heating elements arranged for printing, under the control of individual activation means and by means of memory points of a printing register, successive lines of points on a printing medium driven in scrolling against the head, apparatus characterized in that it comprises means of '' individual writing of memory points.

It is thus possible, when the number of points to be printed on a line is limited, to simultaneously print all of the points, whereas, in the prior art, a fixed duration was reserved for each control block, even if it did not include only one point to print. It will further be noted that, in the event that an excessive number of dots is to be printed, the supply of individual control signals which would activate printing elements may be temporarily suspended until other heating elements return to idle .

In addition, the duration of heating of each heating element can be modulated, that is to say that the head makes it possible to restore black dots whose size depends on this duration and which appear, with their periphery remaining white, as adjustable intensity gray.

To minimize the number of addressing links, it is preferable for the write addressing means to include a memory point addressing demultiplexer.

In order to be able to print black dots of size smaller than that of a pixel (image element), equivalent to gray, the apparatus may include means for controlling write addressing means arranged to receive signals as input. respectively representative of gray intensities of the points to be printed. However, for the same purpose, the addressing and activation control means can be arranged to simultaneously manage the heating duration settings of several printing elements.

• la figure 1 est un schéma par blocs de la tête d'impression dans la première forme de réalisation,
• la figure 2 est un diagramme des temps de signaux de commande de la tête d'impression de la figure 1,
• la figure 3 est un schéma par blocs de la tête d'impression ci-dessus et d'une logique de commande de cette tête,
• la figure 4 est un schéma par blocs de la seconde forme de réalisation,
• la figure 5 est un schéma plus détaillé que celui de la figure 4 et
• la figure 6 illustre l'évolution, en fonction du temps t, de l'état de points mémoire d'activation.

The invention will be better understood using the following description of two preferred embodiments of the line head thermal printing apparatus of the invention, with reference to the attached drawing in which:

• FIG. 1 is a block diagram of the print head in the first embodiment,
• FIG. 2 is a diagram of the times of control signals of the print head of FIG. 1,
• FIG. 3 is a block diagram of the above print head and of a control logic for this head,
• FIG. 4 is a block diagram of the second embodiment,
• Figure 5 is a more detailed diagram than that of Figure 4 and
• FIG. 6 illustrates the evolution, as a function of time t, of the state of activation memory points.

The thermal printing apparatus of the invention comprises, in its first embodiment, a thermal head 1 shown in FIG. 1, of which a row of 1,728 printing heating elements, generally referenced 2, cooperates with an ink ribbon not shown thermal transfer printing, applied to a printing medium consisting of paper, driven against the head 1. The printing elements 2 are connected to a supply wire 3 in +24 volts and are controlled by individual amplifiers / switches 4 each controlled by its own activation bit stored in a memory point 6 here of the flip-flop type "D", of a print buffer register 5 with parallel inputs and outputs comprising an ordered row of 1728 such memory points 6. A demultiplexer circuit 10 has eleven address inputs, referenced 11, and 1,728 outputs respectively linked to 1728 clock inputs 7 belonging respectively to 1728 memory points 6.

The 1728 memory points 6 respectively comprise 1728 data bit inputs 8A connected to a common link 8. An input 9 is provided here, connected to all the memory points 6, allowing all of them to be reset simultaneously, that is to say ie their forcing in the same predetermined state, here a logic level 0, called inactive, for which the heating elements 2 are not supplied with current through the amplifiers 4.

The flip-flops "D" of the memory points 6 can for example be produced by means of integrated circuits, in TTL or CMOS technology, of the type 7474 while the demultiplexer 10 can, likewise, be produced by means of several integrated circuits of the type 74154 or 74HC154 and a logic for selecting only one of them, acting on an address input then serving as a validation input, the corresponding outputs of circuit 74 (HC) 154 then being unused. It could have been provided for flip-flops of type JK, divider by two, and not flip-flops "D", which would have avoided the need for the data link 8 since each addressing of such a flip-flop divider would be enough to make it change d 'state.

The above integrated circuits are available from TEXAS INSTRUMENTS or MOTOROLA companies.

To control the activation of a heating element 2, a corresponding address in the row is applied for a short time to the address inputs 11, the link 8 having previously been set to logic level 1 (FIG. 2). The output of the demultiplexer 10 connected to the clock input 7 of the memory point 6 of the heating element 2 considered provides a pulse during the period of application of the address to the address inputs 11, which has for effect of opening a door, not shown, of individual activation of a heating element 2, which reads the logic level of the data link 8 and controls the storage, in the point memory 6 concerned, of a bit having logic level 1 present on the data link 8.

The deactivation of a memory point 6 is carried out in the same way, the link 8 then being brought to logic level 0.

The bit contained in each memory point 6 is thus an activation bit for the heating elements 2, which can have two states, namely an active state, here the logic level 1, and an inactive state, here the logic level 0.

Thus, in FIG. 2, which is a time diagram of the above signals, the memory point 6 of address "one" is addressed, for a short time within a period T1 of a sequence Ti (i integer = 1 to P), by setting the least significant address bit A0 applied to the address inputs 11 to 1, the other bits, not all of which are represented, being at level 0, which generates a pulse on the input of clock 7 of memory point 6 of address "one", whose logic level, or state, is represented by signal 21.

During the following period T2, another memory point 6, here of address "three", is addressed, the two least significant address bits, A0 and A1, passing to level 1 to provide the binary address 11, that is to say three in decimal. The signal 23 represents the logic level of the bit contained in the memory point of address "three". The initial states of memory points 6 have here been assumed to be state 0.

In this example, the address memory point "three" returns to 0 during the period T3, while the address memory point "one" returns to 0 during the period T4. There is thus simultaneous, or interleaved, management of several memory points 6, by sharing the time t into slices or periods Ti.

It will be understood that, for the sake of clarity, the control pulses appearing from one period T1-T4 to the other pass back to state 0, while in practice the data link 8 remains at the same level during each period T1-T4 and is read, by sampling, by an active edge, here falling, of the clock signal 7. As a result, the periods T1-T4 are limited to a few tens of nanoseconds, which makes it possible to order all of the memory points 6 in much less time than the 10 milliseconds provided for by the standards for printing a line.

The setting of the duration of activation of each heating element 2 can thus be carried out by sending an activation command followed, after the desired duration, by sending a deactivation command returning to 0 the activation bit. It will be noted that the reset link 9 makes it possible, if desired, to simplify the sending of the commands from register 5, by providing for simultaneously deactivating all the activation bits, their activation instant being determined accordingly. Likewise, provision could have been made for the amplifiers 4 or the memory points 6 to be inverters, or even for the link 9 to force all the bits of the printing register to 1. In this case, all the bits of the printing register 5 could be simultaneously put into the active state at the start of line printing, even if it means deactivating them individually almost instantaneously if they correspond to white dots, or, if not, after the desired printing time.

The adjustment of the duration of activation of the heating elements 2 makes it possible to choose the temperature reached by them, as well as the time of the thermal diffusion towards the ink and the transfer time when the ink has melted.

Therefore, the adjustment of the activation time makes it possible to modulate the quantity of ink deposited on the paper at each point, that is to say to obtain black dots of reduced size each surrounded by an area. remaining white, which simulates gray, of independent intensities from one point to another.

The circuit 31 of FIG. 3 controls the multiplexer 10 by transmitting the desired addresses in a timely manner. For this, a reception link 32 provides a series of binary signals representing numbers, coded in this example, arranged according to the order of the dots to be printed, respectively representative of the gray intensities of the dots of a line to be printed.

In this example, each number is proportional to the desired gray intensity, the number "zero" indicating the presence of a white point and the coding corresponds to conventional binary coding. The circuit 31 stores this series of numbers in a shift register 33 with parallel outputs and then reads them successively in a partial scanning cycle by means of a multiplexer 34, addressed by a counter 35 advancing at the rate of a time base 39 of period Ti, until finding a number other than zero, indicating a gray to be printed. The address of the counter 35, which corresponds to the relative position of the number in the row, that is to say the position or address of the memory point 6 considered, is applied to the address inputs 11 of the demultiplexer 10, while the link 8 is brought to level 1 by the circuit 31, to activate the corresponding memory point 6, as explained above. The process continues until the last number. The instants of activation of the memory points 6, supplied by the time base 39, could be memorized with each number of the register 33, but in this case, being very close, only the instant TA of the last activation is noted.

For deactivation of the heating elements 6, the multiplexer 34 continues the partial scan cycles of the register 33 and an arithmetic circuit 37 of the circuit 31 subtracts the stored value TA from the value tj of the current instant, supplied by the time base 39, and compares the result with the corresponding coded number in register 33. In the event that this number is reached or exceeded, a deactivation command is issued, as explained above.

In the second embodiment shown diagrammatically in FIG. 4, a printing register 45, controlling the heating elements in the same way as register 5 of the previous example, comprises 1,728 memory point data entries 46 which, at through gates 44 are connected to as many outputs of an input register 43 containing, like register 33, a series of binary signals representing arranged numbers, also coded in this example, respectively representative of the gray intensities of the points a line to print.

A control circuit 41 is connected by means of a read circuit 42 of the circuit 41, to the input register 43 and controls the opening of a determined number of doors 44, of determined position, this number of doors being a function coded numbers read from register 43, as explained below.

The hatched areas indicate blocks of bits transferred simultaneously, the position of the hatched areas of the register 43 corresponding to that of the hatched areas of the printing register 45, the presence of non-zero numbers, indicating gray, being marked by double blocks. hatched. A coded number therefore corresponds to a bit of the same address of the printing register 45.

FIG. 5 shows in more detail the diagram of FIG. 4. The read circuit 42 is a multiplexer connected to the M outputs of the input register 43, with M = 1728 times the number of bits of each coded number.

As the numbers in register 43 are coded in this example, the output of the multiplexer 42 is connected to a transcoder circuit 47 which converts each coded number received into another, non-coded number, of predetermined length, comprising at the start activation bits in state 1, in numbers proportional to the intensity of the gray defined by the corresponding coded number, these non-coded numbers being stored in a memory 48. For clarity, the memory 48 has not been shown in FIG. 4 and would therefore have to be interposed, with the transcoder circuit 47, between the outputs of the input register 43 and the gates 44.

FIG. 6 represents three non-coded numbers, of five bits each, relating to three points 46-1, 46-2 and 46-5, the abscissa axis carrying the rank P of the memory points 46 and the ordinate axis bearing time t . Point 46-1 has only one bit in 1, so that gray will be light, while point 46-2, having a three-bit number in 1, will have a medium gray and point 46-5 , with 5 bits in 1, will be black because activated for the maximum duration X provided.

The output of memory 48 also attacks a counter 49 which detects the presence of activation bits in 1 and sends a stop signal 50 when it reaches a predetermined value N. The signal 50 has the effect of stopping a counter common addressing 51 controlling the multiplexer 42 and a demultiplexer 40, equivalent to the demultiplexer 10, connected at output to the printing register 45.

After complete writing of the memory 48, a sequencer circuit 52 forces the counter 51 to a determined address value, of value "one" at the start, and starts a cycle of a reading sequence of the first bits of each uncoded word from memory 48. If the bit read is at "1", this "1" is copied into memory point 46 of the same address through the demultiplexer 40. After N such copies, the counter 49 sends the stop signal 50 , which stops any further sending of "1" to the printing register 45, and the address AS of the last memory point 6 in 1 is memorized by the circuit 52. The circuit 52 then resets the counter 49 to "one" to start a new cycle, relating to the second bits of the non-coded numbers of the memory 48 and, then, sends a command to deactivate the memory points 46, of address "one" to AS, for which the second bit of the non-coded number is in state 0, which is the case for point 46-1.

Other subsequent cycles, starting from the address "one", make it possible to process the following bits of the same uncoded numbers, which, in the end, ensures the deactivation of the heating elements 46 of address "one" at AS. Other such cycle sequences, the first of which begins at the address AS + 1, make it possible to successively control blocks of variable size (FIG. 4) comprising sets of N memory points 46 in the activated state, two of which are , as indicated, shown each time in FIG. 4, separated by any number of memory points 46 in the inactive state. The writing by the demultiplexer 40 is thus carried out under the control of the addressing means (42, 49) since it is the counter 49 which determines, by the stop signal 50, the extreme addresses of each block of bits .

After writing the last black point of the line, the bits of the next line to be printed are read in the input register 43, to start a new printing.

Claims (8)

Line head thermal printing apparatus comprising a plurality of printing heating elements (2) arranged for printing, under the control of individual activation means (7, 8) and via memory points (6; 46) of a printing register (5; 45), successive lines of dots on a printing medium driven in scrolling against the head (1), apparatus characterized in that it comprises means (10; 40 ) individual write addressing of memory points (6; 46). Printing apparatus according to claim 1, in which the write addressing means comprise a demultiplexer (10; 40) for addressing the memory points (6; 46). Printing apparatus according to either of Claims 1 and 2, in which the printing register (5; 45) comprises an input (9) for controlling the forcing of the memory points (6) into the same predetermined state. Printing apparatus according to one of claims 1 to 3, in which there are provided control means (31; 41; 47, 48, 49, 51) write addressing means (40) arranged to receive in input of signals respectively representative of gray intensities of the dots to be printed. Printing apparatus according to one of Claims 1 to 3, in which means (31) for controlling write addressing means (10) are provided and the activation control means (7, 8) comprise a link (8) connected to the memory points (6) of the register (5). Printing apparatus according to either of Claims 4 and 5, in which the addressing and activation control means (31; 41) are arranged to simultaneously manage the heating duration settings of several printing elements ( 2). Printing apparatus according to one of Claims 4 to 6, in which read addressing means (42, 49, 51) are provided arranged to read, from an input memory (43 48), a number determined activation bits in an active state of a line to be printed, and the control means (51; 52) of write addressing means (40) are arranged to select said activation bits under the control of the reading addressing means (42, 49, 51) and for controlling the transfer of said activation bits, from the input memory (43) to the printing register (45). Printing apparatus according to claim 7, in which a counter (51) is provided for controlling both the read addressing means (42) and the write addressing means (40).

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