JPS6115469A - Thermal recorder - Google Patents

Abstract

PURPOSE:To obtain a picture with stable recording density at all times by calculating a stored energy of each heating resistor of a thermal head while referencing an existing line and plural preceding lines so as to decide the conducting pulse width to a head. CONSTITUTION:Each color picture signal from a CCD line sensor 2 is inputted to a parallel/serial converter 5 via amplifiers 3a-3c, A/D converters 4a-4c, where the signal is converted into a serial signal and stored in a line memory 6. Processings such as shading correction are conducted by a signal processing circuit 7, compared with each threshold circuit set at each color by a dither circuit 8 and binary-coding in response to the gradation of the input signal is attained. The data subject to binary-coding is written sequentially in frame memories 9a- 9d corresponding to each color and fed to a thermal head drive circuit 10. The thermal head drive circuit 10 calculates a storage energy of each heating resistor of the current line and the preceding line and sets the application pulse width based on the result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thermal recording device capable of stabilizing recording density.

[Technical background of the invention and its problems]

Thermal recording devices, typified by thermal transfer recording devices, are widely used as output terminal devices for various office automation equipment because they generate little noise during recording, have a simple mechanism, and are easy to maintain. Further, thermal recording devices are relatively easy to colorize and produce bright colors, so they are highly anticipated as color printers.

However, conventional thermal recording devices have a unique problem in that the recorded images become non-uniform due to the heat storage effect of the heating resistor that constitutes the thermal head. In other words, if the period of the energization cycle is shortened in order to improve the recording speed, when the heating resistor that was energized in the previous energization cycle is energized again, the heat generated in the previous energization cycle will not be sufficiently dissipated. When new electricity is applied, the temperature of the heating resistor continues to rise.

Therefore, when the energization cycle is repeated at such short intervals, the current temperature of each heating resistor differs depending on the past history of energization. If the heating resistors are energized at the same time in this condition,
For example, in the case of a thermal transfer recording device, the area on which the ink is softened on the ink film is different, and the area of the ink transferred onto the recording paper is also different, and in the case of thermal recording, the color density of the thermal paper is different. will change. For this reason, there is a problem that the image density of the recorded image becomes non-uniform. In particular, in a thermal transfer color printer, a color image is obtained by polymerizing translucent ink, so that the hue changes as the density of the image points changes. Furthermore, when characters or the like are recorded, ink is transferred to areas where there is actually no image data and should not be transferred, such as small gaps, for example, resulting in problems such as the characters being crushed.

In order to solve this problem, for example,
As shown in No. 631, for each heating resistor, when mark data arrives successively as image data, the head energization time is made shorter than when mark data arrives following space data. is proposed□
ing. That is, the energization FRIIl of the next energization cycle is switched between two stages depending on whether or not there was energization in the previous energization cycle. According to this method, the above-mentioned drawbacks are alleviated to some extent, but during high-speed recording, even if the pulse width is shortened by the above-mentioned control, the heat generated by the previous energization is It remains until the power is turned on.

For this reason, even if the image density is normal at the start of recording, it is gradually affected by the heat storage effect and the image gradually becomes darker.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a thermal recording device that can obtain images with stable recording density from the start of recording to the end of recording even during high-speed recording. It is about providing.

[Summary of the invention]

The present invention calculates the current stored heat energy of each heating resistor that constitutes a thermal head by referring to one or more lines before the current line, and also combines the calculated stored energy with the current recording line. The present invention is characterized in that the current energization pulse width of the thermal head is determined by referring to the image data of one or more recording lines thereafter.

〔Effect of the invention〕

According to the present invention, based on the data of the current recording line,
Since the image data of 1 or t plural recording lines before and after that is referenced, it is possible to determine the energization pulse width taking into account the current stored energy of each heating resistor, and also to The energization pulse width can be determined by taking into consideration the image points to be displayed. Therefore, unlike the conventional method, there are no problems such as collapse of white areas or gradual changes in image density, and it is possible to always obtain a recorded image with a stable density.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A thermal recording apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining a method for determining the energization pulse width in this embodiment. In the apparatus of this embodiment, a case will be described in which recording is performed using a line thermal head in which a large number of heating resistors are arranged in a line.

That is, for example, if the current line on which a recording pixel is to be formed is n lines, the energizing pulse width for forming the pixel P on the i-th line of n is n±2 lines and i±2 lines. image data, and n±2. n±
It is determined in one line and with reference to the first image data. The reason for referring to the image data of the lines (n-1, n-2) before the n line is to calculate the stored energy stored in the heating resistor that is currently recording the pixel P. For example, the further away from the pixel of interest P, the smaller the weighting is given.

Also, recording lines (n+1.
The reason for referring to the image data of line n+2 is as follows. That is, when the image data to be recorded from now on is not known, for example, when there is pixel data to be recorded after the current recording line as shown in FIG. As shown in (b), it is difficult to distinguish when there is no pixel data to be recorded subsequently. In this case, since no pixel has been formed in the past, the heating resistor is given the maximum width energizing pulse.

However, when the maximum width energizing pulse is applied to the heating resistor in this way, even if no pixel is formed later as shown in (b) of the same figure, one line is opened as shown in (a) of the same figure. If a pixel is formed later, the point Q that should be drawn out in white will be crushed due to the heat storage effect of the heating resistor when the pixel is formed later. Therefore, in this embodiment, as described above, the image data of the lines after the current recording line are referred to, and when a pixel is formed later, the energizing pulse width at the current recording line is controlled to be small. That's what I do.

Next, a specific example of the configuration of an apparatus that enables such recording will be explained using a thermal transfer color copying machine as an example.

FIG. 3 is a block diagram showing the configuration of the main parts of the thermal transfer color copying machine. That is, in FIG. 3, the reflected light from the document 1 irradiated by a light source (not shown) is
An image is formed on a photoelectric conversion element, for example, a CCD line sensor 2, through a color filter array consisting of green (G), yellow (Y), and cyan (C) color filters. Note that the configuration of the color filter array may use, for example, a pair of green, blue, and red. The CCD line sensor 2 converts the gray scale image information on the original 1 into an electrical signal and reads it into the system.

The image signals of each color from the CCD line sensor 2 are each amplified with a predetermined gain by amplifiers 38 to 3C, and then sent to the A/D
The signals are converted into digital signals by converters 4a to 4C. This digital signal is further converted into serial signals in the order of G, Y, and C by a parallel-to-serial converter 5, and then stored in a line memory 6. The line memory 6 is for temporarily storing gradation image signals for one line in the direction indicated by the arrow X in the figure of the original 1, that is, in the main scanning direction. Assuming that the resolution of the CCD line sensor 2 and the thermal head 11 described later is 12 dots/m,
It consists of a RAM with a capacity of 2560 x 3 x 8 bits. When one line of image information is written into the line memory 6, the CCD line sensor 2 scans the original 1 in the direction of arrow Y in the figure, that is, in the sub-scanning direction, for one line (1/12
m) and read the image information of the second line. Note that the line memory 6 is actually capable of storing two lines separately, and while the data of one line is being written, the data of the other line is being read. ing. The data thus read out is supplied to the signal processing circuit 7 and subjected to appropriate signal processing.

Hereafter, if this operation is performed for all lines, image information for one document will be taken into the system. For example, if the resolution in the sub-scanning direction is 1/12m,
If this process is repeated for about 3,500 lines of an A4 document, all image information will be captured.

The signal processing circuit 7 receives G input from the line memory 6,
After performing processing such as shading correction, γ-correction, and filtering on the Y and C image signals, the obtained signals are converted into the printer's primary colors of yellow (Y), magenta (M),
It is converted into three primary color signals of cyan (C) or each color signal of Yl, MlG and black (BL). This signal processing circuit 7
The image information having the density information converted into each color signal via is supplied to a dithering circuit 8 having a binarization function.

In the dithering circuit 8, the input Y, M, C or B
Each L image signal is compared with each threshold value of a dither matrix set in advance for each color, and binarization is performed according to the gradation of the input image signal. The data thus binarized is stored in frame memories 9a, 9b, 9 provided corresponding to each color of Y, M, C or BL for each line.
c, 9d are sequentially written (.

All image data for one frame is stored in the frame memory 98~
Once written to frame memory 9d, the data in frame memories 98 to 9d is sent to thermal head drive circuit 10. The thermal head drive circuit 10 determines the energization timing of the thermal head 11 according to input image data. An ink ribbon 12 is inserted between the thermal head 11 and the recording paper 13, and is formed by applying Y, M, C, and BL softening inks, for example, in a surface-sequential manner. Then, for example, a yellow image is transferred first, followed by magenta, cyan, and finally black images, and so on, and color recording is completed.

The image data of each color binarized by the dithering circuit 8 is supplied in parallel to the frame memories 98 to 9d corresponding to each color, and at the same time, the image data of each color is supplied to the thermal head drive circuit 10. are also supplied directly. Therefore, writing to the frame memories 98 to 9d and driving of the printer head are performed at the same time, and the recording time can be shortened accordingly.

Next, a specific example of the configuration of the thermal head drive circuit 10 will be described in detail.

The thermal head drive circuit 10, as shown in FIG.
Color selection section? ? , masking section 23, data resynthesizing section 14
, a thermal head interface section 25, and a timing controller 27 that manages these.

The color image data output from the frame memories 98 to 9d or the dithering circuit 8 is transferred to the color signal transmission line 21.
is supplied to the color selection section 22 via the color selector 22. The color selection unit 22 selects one type of color data. Next-stage masking section 23
Then, after extracting only the portion of the data selected by the color selection unit 22 that is desired to be output by the printer, the data is supplied to the data resynthesis unit 24, where it undergoes appropriate signal processing and then thermal processing. It is supplied to the Herad interface section 25. Here, data is rearranged in accordance with the thermal head 11 used. Thereafter, the output from the thermal head interface section 25 is supplied to the thermal head 11.

The color signal selection section 22 is configured as shown in FIG. 5, for example.

That is, each image data input via the color signal electrical circuit 21 is, for example, an 8-bit parallel signal, and these signals are divided into Y, M, C, BL by the logic of the color data generation section 34. Besides, Y-BL, M-B
The data is converted into L, C-BL, and BL (M-excluded signals) and supplied to the color data selection circuit 35. Note that when the color signal transmission path 21 is composed of only three systems, Y, M, and C, the color data generation section is configured as shown in FIG.
,M.

By configuring the circuit to generate a BL multiplied signal using the AND logic of C, the same function as the circuit described above can be achieved. The color data selection circuit 35 selects one color signal from the aforementioned eight types of signals in response to a color selection signal from a CPU (not shown) or the like. The color signal selected by the color data selection circuit 35 is then inverted or non-inverted by an inversion circuit 36. This designation is performed by the CPU or the like, and the output image becomes a negative or positive pattern based on this designation. Since the color data passing through the inverting circuit 36 is an 8-bit parallel signal, it is supplied to a shift register 37 and subjected to parallel-to-serial conversion.

The masking section 23 is configured as shown in FIG.

The masking unit 23 has a function of cutting out only the necessary part from the image data, for example, when printing an arbitrary part of the image data, or when the size of the recording paper is smaller than the original size. Used when printing to match recording paper.

That is, the counter 40 counts the shift clock of the shift register 37 described above and detects the currently recorded horizontal position. For example, 12 pieces/I
When a R1n thermal head is used, the total resistance of the thermal head is 2560, so the bit counter 40 is configured as a down counter that counts between 2560 and O. This counter 40 is reset by a horizontal synchronization signal. The left mask bit number register 43 and the right mask pit register 44 specify the number of bits to be masked on the right and left sides of one screen, respectively. The parameters stored here are specified by CPLI or the like. The value counted by the bit counter 40 is compared with the values set in the two registers 43 and 44 by comparators 45 and 46, thereby cutting out the portion of one line that is desired to be output.

The masking unit 23 is also provided with a line number counter 47 for counting horizontal synchronizing signals, and the count value of this counter 47 and the upper mask line number register 48 and the lower mask line number register 49 are set. Masking in the line direction is performed by comparing the calculated parameters with comparators 50 and 51. The line number counter 47 is reset each time printing of one color is completed. The mask signals generated by these comparators 45 and 46 and the comparators 50 and 51
A gate circuit 54 performs an AND logic on the mask signal generated by the gate circuit 54, and a gate circuit 55 performs an AND logic on the input image data and the output of the gate circuit 54 to extract only the necessary portions of the input image. Cutout output image data can be obtained.

By the way, if the thermal head 11 is directly driven by a signal from the masking section 23, as described above, the image density will change due to the heat storage effect of the thermal head 11. It is necessary to determine the pulse width.

As a circuit capable of determining the energization pulse width in this manner, the circuit shown in FIG. 8 can be considered.

That is, the masking unit 23 supplies the shift register 60 with color data in which only the portion of the input image that is desired to be masked is masked. This shift register 60
converts serially inputted image data into parallel data, extracts image data around the heating resistor of interest, and supplies it to the pulse width calculation section 61. On the other hand, the stored energy 211 section 62 stores data on the current amount of stored energy of each heating resistor calculated by the stored energy calculating section 64. In addition, the line buffer 63
Stores image data of lines subsequent to the currently recorded line. The pulse width calculation section 61 inputs the data stored in both of these storage means and sets the energization pulse width. Accumulated energy calculation unit 64
calculates how much energy will be stored until the heating resistor is energized next time when the heating resistor of interest is energized with the pulse width calculated by the pulse width calculation unit 61. and writes it into the stored energy storage section 62. This value is stored for use in calculating the pulse width and stored energy when recording the next line.This value is updated for each line. The image data passing through the register 60 and the line buffer 6
The data No. 3 is supplied to the data update section 65, where the currently read data is added to the previously stored data and the data is updated. Then, data is written to the line buffer 63 again. The line buffer 63 stores several lines of future image data including the currently recorded recording line.

It is also conceivable, for example, to further simplify the above circuit to have a circuit configuration as shown in FIG. In this case, instead of using the energy stored in the heating resistor from the start of recording to the present as the stored energy data, the method uses image data for several past lines. That is, to calculate the pulse width data, input image data for the past several lines, input image data for the recording line, and input image data for the future several lines are used. Therefore, the line buffer 67
Currently, 942 pieces of image data for future input image data are stored. In addition, the data update unit 66 adds the newly read data to the data stored in the line buffer 67, removes the oldest data, updates the data, and then adds the newly read data to the data stored in the line buffer 67. It would be good if it had a function to write to. Although Figures 8 and 9 are conceptually quite different, they can be made using the same hardware, for example by configuring each calculation section 61, 64, 65, 66 with ROM, etc. can do.

In this embodiment, the data resynthesizer 24 has a function isometric to that of the circuit shown in FIG.

FIG. 10 is a diagram showing the configuration of such a data resynthesizer 24. As shown in FIG.

That is, in FIG. 10, 69 is a shift register, and the serially supplied image data is transferred to, for example, 3
It has a function to output bits at a time, for example, the first
The 3-bit data supplied to the first heating resistor and the 1±1st heating resistor in the figure is extracted. In addition,
This data becomes the data on the (n+2)th line in FIG. The line buffer 171 stores the past 4 lines of input image data, and has 4 bits of R.
It is composed of AM. The output of this line buffer 11 is supplied to a pulse width calculation section 70 via three shift registers 72, 73, and 74 each consisting of a 4-pit latch. Note that the line buffer 71 stores data for the past four lines counting from the currently input data, but when actually used for thermal control,
The currently incoming data is the n+2th line in Figure 1, so the nth line data that is about to be recorded, the data of the past two lines (n-1, n-2 lines), and the future one line. This means that data for (n+1 lines) is stored. In this state, the pulse width calculation section 70 is supplied with input images of lines n-2 to n+2 of the 1st, i+1st, and i-1th heating resistors, respectively. As a result, a 3×5 matrix shown in FIG. 1 is extracted.

Therefore, the pulse width calculation section 10 calculates the energization energy from these input image data and outputs the result to the thermal head interface section 25.

At the same time, the pulse width calculation section 10 discards the oldest data of the data supplied from the line buffer 11, that is, the data on the (n-2) line, and replaces the currently input data on the (n+2) line. The appendix is added as the newest data, and the contents of the line buffer 71 are rewritten with that data.

In the case of this embodiment, since the pulse width data output as the calculation result and the data in the line memory are each 4 bits, the pulse width calculation unit 10 has 8 pits of RO.
I'm using M. With such a configuration, it is possible to stably supply the density of a recorded image.

Next, the operation of this data resynthesizer 24 will be explained in detail.

Note that the waveforms of each control signal described below are shown in FIG. 11.

The timing controller 27 has frame memories 98-
A memory read signal MR is output to 9d.

Frame memories 98 to 9d receive this MR multiplied signal,
Outputs 1 byte of data written in memory in advance. This data passes through each circuit of the color selection section 22 and is loaded into a shift register 37 for parallel-to-serial conversion within the color selection section 22. At this time, shift register 3
7 is supplied with the LD signal from the timing controller 27. Next, from the timing controller 27, 5
The RCLK signal is input to each CLK terminal of the shift register 37 and shift register 69. After the 8-bit data loaded into the shift register 37 is masked, the data is sequentially loaded into the shift register 69 one bit at a time.
is input. When the transfer of 8-bit data is completed, the timing controller 21 again outputs the MR multiplied signal in order to input the next 8-bit data. From then on,
This operation is repeated for one line (320 bytes). Further, the timing controller 27 outputs the ALATCH signal to the shift registers 72 to 14 at the same time as 5RCLK, and shifts the data for the past four lines output from the line buffer 71 to the shift registers 72 to 74 one after another. Further, the ALATCH signal increments the count value of the read address counter 76 and causes the line buffer? The read data from 71 is updated. In this way, the 4-bit pixel data from the shift registers 72 to 74 are output following the pixel data from the shift register 69, producing a total of 15 bits of pixel data.

The pulse width calculation section 70 examines the input pixel information of 15 pits, determines the energization pulse width so as to eliminate the influence of the heat storage effect, and outputs 4-bit energization pulse width data. This pulse width calculation section 70 is specifically constituted by a ROM, is addressed by the input 15-pit data, and outputs the corresponding pulse width data. If you use this hardware, you can set the position of the pixel of interest anywhere as shown in Figure 12, so you can pay attention to the position where thermal control is easier depending on the printer speed and the dither arrangement of the input image. Just set the pixels.

The contents of the ROM are determined according to the pixel pattern around the pixel P of interest. FIG. 13 shows this pulse width calculation section 70.
4-bit energization pulse width data supplied from the thermal to the RAD interface section 25 and the thermal head 11
The relationship between the energization pulse and the energization pulse is shown.

In this example, four energizing pulses ENs to EN4, each having a different energizing pulse width, are set as shown in FIG. There is a one-to-one correspondence between each bit of the pulse width data. For example, in the energization pulse width data, the most significant bit (MSB) in FIG. 13(a)
corresponds to the energization pulse ENI, the second bit corresponds to EN2, the third bit corresponds to ENa, and the fourth bit corresponds to EN
It corresponds to 4. The energizing pulse width to each heating resistor is
It is formed by selecting the energizing pulse corresponding to the bit whose data is 1'' among the 4 bits of the energizing pulse width data.For example, as shown in FIG. 13(b), the energizing pulse width data is "1". i o 1i”, ENl, EN
3 and EN4 are selected, and the heating resistor is energized for four time periods of T1+Ts+T4. By such a method, the width of the energizing pulse to each heating resistor is changed. In this case, the width of each pulse is 1=
If the ratio is 2:428, a maximum of 16 pulse widths can be selected.

The reason why the energizing pulse width is divided in this manner is that the thermal head 11 cannot arbitrarily determine the energizing pulse width for each multi-heating resistor due to its structure.

When the pulse width calculation unit 70 sets the energization pulse width to the thermal head 11, the pulse width calculation unit 70 calculates the past 4 pulse widths.
The oldest data is discarded from among the lines of input image data, and the data is updated using the current input data as the newest past data.

Further, the updated data is successively written to the line buffer 11 in FIG. 10. The writing timing is determined by the WRA signal output from the timing controller 27. This WRA signal is also input to the write address counter 75 at the same time. The write address counter 75 specifies the write address of the line buffer 71. The write address counter 75 and the read address counter 76 are switched by the selector 17 and selectively output their outputs to the line buffer 71. The reason why two address counters are provided in this manner is that the read address and write address are different. In other words, in order to calculate the energization pulse width,
Until the image data of the first resistor is shifted to the second bit from the bottom of the shift register 69, the input image data of the past four lines of the first resistor is shifted to the shift register 7.
This is because it must be shifted until it appears at the output of 3. When all data calculations for one line are completed in this way, all control signals are turned off until a synchronization signal is input to start reading the next line. Thereafter, the above process is repeated for all lines.

FIG. 14 shows the thermal head 11 used in this embodiment.
It is a figure showing a schematic structure of. This thermal head 11 is a line thermal head in which a large number of heating resistors R1 to R2560 are arranged in a line, and a 2560-bit heating resistor 80 is arranged on one line. Each heating resistor 80 is connected to an IC driver 81 for passing current through these resistors. And these are
It is integrated on one substrate.

The driver IC is capable of driving 32 pits of the heating resistor. Therefore, one head is equipped with 80 driver ICs. The driver IC is the first
As shown in Figure 5, 3 performs serial-to-parallel conversion.
2-bit shift register 82 and 32-bit latch 8
3, a gate 84 for controlling energization, and a resistor 80
A driver 85 supplies a predetermined level of current to the driver 85.

Data input to the input terminal SIN is sequentially transferred within the 32-pit shift register 82 by CLK. Once the 32-bit data has been transferred, the LATC
The data that has just been transferred is held in the 32-bit latch 83 by the H signal. Next, pulse width data EN
When , the output of the gate 84 goes high only when the data held in the latch 83 is 1, so the driver transistor 85 connected to the gate 84 turns on, and the driver 85 Current can be passed through the heating resistor connected to the Also, the first
As shown in FIG. 4, this thermal head 11 has driver ICs 81 arranged on both sides of a heating resistor. In other words, each 32-bit resistor is driven by drivers 81 which are alternately arranged with heating resistors in between. Furthermore, in order to speed up data transfer, this head has eight input terminals 5IN1 to 5IN8, one input terminal for inputting 320 bits of data. Therefore, one line of data can be transferred using 320 CLK signals, so when 4MH2 CLK signals are used, one line of data transfer is completed in 82 μsec. Also, data input terminal 5IN1
~SIt'18 is also provided with four on each side with the heating resistor 80 in between, and one input terminal receives input data that is supplied to the ten driver ICs lined up on one side of the heating resistor. It is now possible to do so. Also, signals such as CLK signal and LATCH signal are 401 on each side.
It is supplied to the driver IC 81 of il. In addition, the EN signal that determines the energization pulse width is
Each driver IC 81 is driven individually.

In order to drive the thermal head 11, the energization pulse data serially output from the data resynthesizer 24 needs to have its data arrangement order changed before being supplied to the thermal head. . The thermal head interface section 25 has such a function. FIG. 16 is a diagram showing a specific configuration of this thermal head interface section 25. As shown in FIG. That is, the 4-pit energization pulse width data output from the data resynthesizer 4 is stored in the buffers 911 to 918 or the buffer 9.
It is supplied to RAM 941-948 or RAM 951-958 through 21-92B. These buffers 901 to 90e 1921 to 928, RAM 941
-94B, 951-958 are each eight in one set, and correspond to the eight input terminals of the thermal head 11. For example, if there is one input port, only one buffer and RAM are required. Furthermore, the reason why the buffer and RAM are separated into two systems is to accommodate higher speeds. For example, RAM 941
While writing data to ~94B, RAM 95
Writing and reading are performed simultaneously, such as reading data from 1 to 958, thereby increasing the speed.

The thermal-to-rad interface section 25 configured as described above operates as follows. First, data resynthesis unit 2
The first 32 bits of data output from 4 are
It is written to RAM 941 via buffer 901. At this time, 32 bits of data are stored in the C8 terminal of the buffer 901 in the RAM 94. A signal that enables this buffer 901 is input only when writing to the memory. In other cases, the buffer 901 is disabled. Therefore, the data output from the data resynthesizer 24 is supplied only to the input terminal of the RAM 941, and the signal that enables the buffer 90,
In other words, the write signal to RAM941 RAMB11
Written into the RAM 941 by W R.

At this time, address data is supplied to the RAMs 941 to 94B from the address generator 98, and the address is incremented by one each time data for one pixel is written to the RAM. Outputs addresses from to 31. As can be seen from FIG. 15, one line of data is alternately supplied every 32 bits with heating resistors in between. Therefore, the next 32 bits of data must be supplied from the 5IN2 terminal, so they are written to RAM 942 (not shown). At this time, the RAM B 12W R signal is output from the timing controller 27, so
Only the buffer 902 (not shown) is enabled, and the pulse width data output from the data resynthesizer 24 is written only to the RAM 942. At this time as well, the address generator 98 outputs addresses 0 to 31. The next 32 bits of data are 5IN1 again.
RA from the timing cone controller 27 again.
The MB11WR signal is output, and the above data is stored in RAM
It is written to 941. At this time, addresses 31 to 63 are generated from the address generator 9B.

Furthermore, since the next 32-bit pulse width data must be supplied from the 5IN2 terminal, the timing controller 27 again outputs the signal of RAMB12WR and is sequentially written into the RAM 942.

At this time as well, addresses 31 to 63 are output from the address generator 98. Repeat this process,
640 dot image data is sequentially transferred to RAM 941 and R.
By alternately writing 32 bits to A M 942, all the data to be supplied from the terminals 5TNI and 5IN2 to the thermal head 11 can be written. Similarly, the next 641st to 1280th data are RAM
943 and RAM94+, ;t'ta 1281-1920
The second data is stored in RAM 945 and RAM 946. Furthermore, data from 1921st to 2560th is RAM 947
32 bits are alternately stored in each address of O1 to 319 of RAM 948, and as a result, 2560 dots of data for one line are all stored in RAM 941 to 948.
stored in

In this way, while writing pulse width data to RAM 941 to 948, data is written to RAM 951 to 95 at the same time.
From 8 onwards, 1 which has already been written during the processing of the previous line
The pulse width data before the line is read.

At this time, the RAMs 95s to 956 are in a read state, and the pulse width data stored at the address designated by the address generator 99 is output to their output data lines. The multiplexers 100 to 108 are
RAM 94. Of the 4-bit data each of the pulse width data output from RAMs 948 to 948 and the pulse width data output from RAMs 951 to 958, 1 bit of data from the RAM that is in the read state is selected, and the thermal head is 11 input terminals 5IN1 to 5IN8.

The timing of this selection is determined by the timing controller 27.
This is done by the multiplexer control signal MPC from. For example, when RAMs 951 to 958 are in the read state, the multiplexer outputs 4 from the RAMs 951 to 958 in the read state.
One bit is selected from among the bits of energization pulse width data. This output data is taken in by a CLK signal generated from the timing controller 27 into a shift register 82 in a driver IC 81 disposed on the thermal head. At the same time, the CLK2 signal is supplied from the timing controller to the address generation section 09, and the value of the address supplied in parallel to RAM'95r to RAM'958 is counted up by one. By repeating this operation 320 times, RAM 951~
All data of one line stored in 95B is taken into the thermal head. The data transferred to the shift register 82 is held in a latch in the driver IC 81 by the LATCH signal that is output afterwards, and then the data is transferred to the EN
The signal is used to drive the heating resistor 80.

The data is output from the data resynthesizer 24 and stored in the RAM 95. ~
The pulse width data written in 958 is composed of 4-bit data as described above. RAM951~9
58, the most significant bit (MSB) of the 4-bit data is inputted via a multiplexer. Then, in the first read, when all MS8 bits are taken into the thermal head, an energizing pulse EN with a width of T1 is applied.
t is supplied from the timing controller 27 to the driver IC. As a result, the first transfer is performed.

The timing controller 27 outputs CLK to the thermal head 11 and CLK2 to the address generation section 99 simultaneously with the above transfer. Also, multiplexer 1
00 to 108 are multiplexer control signals M
PC is output, RAM 95. multiplexers 100-108 such that the second bit in ~956 is selected.
control. When the data of the second pit is transferred to the thermal head 11 for one line, immediately after the first transfer is completed, the LATC)-1 signal for latching the second data is sent from the timing controller 27 to the driver IC.
81, and the data is latched. When the latch ends, the second pulse width signal EN2 is output, and the second transfer is performed. Repeat the same operation for the third time, 4
This is repeated in the second transfer, and the transfer operation for one line is completed.

In this way, one line of data is transferred,
Since the thermal head used in this embodiment has 2560 bits, a very large capacity power supply must be used to energize all of these heating resistors 80 at the same time. Therefore, as shown in FIG. 517, two signals AEN and BEN are used as transfer enable signals to divide the number of heating resistors 80 that can be driven simultaneously. That is, in this example, A E N , '
Since there are two B E Ns with a heating resistor 80 in between, the number of driver ICs that can be driven simultaneously is 20 (640 elements in terms of the number of heating resistors), and at least the capacity to drive this many resistors is sufficient. All you need to do is prepare the best power source. In addition, in this example, the two AEN%BEN are:
Since the same signal was used, half of all the elements were simultaneously driven to the maximum in one line transfer. Therefore, it is RAM 651~ that records all the data of one line.
From 658, eight read operations are required, and
Transfer will also be performed eight times. In other words, the first read operation is AENt, the second is AEN2, and the third is AEN! , from the 4th time, AEN4. From the 5th time, BEN
The transfer operation for one line is completed by performing reading and transfer a total of eight times, t, . . . . These E.N.
The signal must be equal in length to AEN and BEN for each bit of 4-bit data read from RAM. In the case of the winding of this embodiment, if the lengths are different, there will be a difference in transfer density between the right half and the left half. Therefore, in this embodiment, four different CR product values are used.
AEN and BE
The lengths of N were made equal. The operation of the thermal-to-rad interface section 25 described above, the output from the timing controller 27, etc. are shown in FIG.

When the transfer operation for one line is completed, the transfer operation for the next line is performed. At this time, the data written in the RAM groups 641 to 648 is transferred to the data input terminal 5 of the thermal head.
Control signals are supplied from timing controllers 0 to 527 to input data to IN1 to IN1 to IN8, and then write newly input data to RAM 651 to 658. Transcription takes place. Thereafter, the above process is repeated to complete the transfer of one screen.

Since the image recorded in this way is data of only one color selected by the color selection section 22, in the case of a color copying machine like this embodiment, the transfer operation of the second color is performed next. must be done. Therefore, the CPLI detects what color the next ink will be, and instructs the color selection unit 22 as to the color to be transferred next. Of course, if the order of colors to be transferred is known in advance, the color information stored in the CPU may be provided to the color selection section 22. In this way, each color of ink can be transferred to obtain a color image output.

As described in detail above, according to this embodiment, the current energization pulse is determined by referring to the 3×5 pixel data around the pixel of interest, so that an image with stable density can be obtained. be able to. In other words, it is possible to provide a color copying machine that is less affected by the heat storage effect.

Note that the present invention is applicable not only to thermal transfer printers but also to thermal printers.

[Brief explanation of the drawing]

1 and 2 are schematic diagrams for explaining the principle of a thermal recording device according to an embodiment of the present invention, and FIGS. 3 to 17 are schematic diagrams for explaining a color copying machine to which the same device is applied. FIG. 3 is a block diagram showing the overall configuration,
FIG. 4 is a block diagram showing the configuration of the thermal head drive circuit, FIG. 5 is a block diagram showing the configuration of the color selection section, FIG. 6 is a block diagram showing a modification thereof, and FIG. 7 is the configuration of the masking section. 8 and 9 are block diagrams showing the configuration of the thermal control circuit, FIG. 10 is a block diagram showing the configuration of the data resynthesizer, and FIG. 11 is a waveform diagram for explaining its operation. , FIG. 12 is a schematic diagram showing a modified example of the pixel of interest in the data resynthesizing section, FIG. 13 is a diagram for explaining the pulse width control method, and FIG. 14 is a block diagram showing the configuration of the thermal head. , FIG. 15 is a block diagram showing the main parts of the thermal head. 16 is a block diagram showing the configuration of the thermal-to-rad interface section, and FIG. 17 is a waveform diagram for explaining its operation. 1... Original, 2... CCD line sensor, 11...
・Thermal head, 12... Ink ribbon, 13...
-Recording paper, 22...Color selection section, 23...Masking section, 24...Data resynthesis section, 25...Thermal head interface section, 27...Timing controller, P...Pixel point . Applicant's agent Patent attorney Takehiko Suzue i-1i i+1 Figure 2 (a) (b) O○ Figure 6 Figure 8

Claims (1)

[Claims] means for calculating the heat storage energy of each heating resistor constituting the thermal head by referring to image data of one or more recording lines preceding the current recording line currently recorded by the thermal head; 1 after the line
Alternatively, a thermal recording apparatus comprising means for determining the current pulse width of the current to the thermal head by referring to the image data of a plurality of recording lines and the stored energy.