KR930006805B1 - High-speed printing circuit in video color printer - Google Patents

Abstract

The high speed printing circuit in a video colour printer comprises first and second memories (58,59) converting R,G,B signal of video colour to Y,M,C, recording Y,M,C signal separately according to even and odd field, and outputting while reading; an address counter (60) generating address data for memorizing into the first and second memory; first and second comparators (61,62) comparing the output value from the first and second line memories according to a counting value; and first and second TPHs (74,75) of multiple TPHs (21,22) heating paper.

Description

High Speed Printing Circuits for Video Color Printers

1 is a conventional circuit diagram.

2 is a block diagram of a conventional drum (1) and TPH (2).

3 illustrates a conventional line memory storage method.

4 is a flow chart of the conventional TPH 2;

5 is a circuit diagram according to the present invention.

Figure 6 illustrates a line memory storage method in accordance with the present invention.

7 is a block diagram of a drum (1) according to the invention and two first, 2TPH (74, 75).

8 is a printing flow chart according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing circuit in a video color printer, and more particularly to a high speed printing circuit in a video color printer that can realize high speed printing using two TPHs.

In general, a video color printer refers to an apparatus for converting an image signal into a digital signal, storing the image signal in a memory such as a field memory or a frame memory, and accessing the image signal to output the printer.

Such video printer apparatuses are being developed gradually in response to the need to record image signals by momentary capturing of image signals or to reproduce or print images obtained through recording apparatuses such as still cameras on a monitor. There is a trend.

Note that the video printing apparatus is described in detail in the patent applications Nos. 89-4467 and 89-14204 filed by the same applicant.

The prior art related to the present invention will be described with reference to FIGS. 1 to 4 as follows.

The image data through the data input terminal D1 is converted into digital data according to the sampling signal generated by the system controller 150 and input to the line memory 120.

When data is input to the line memory 120, the data is stored in the line memory 120 in the form of FIG. 3 under the control of the system controller 150.

The image data pre-stored in the line memory 120 is read and input to the comparator 130 under the control of the system controller 150. The comparator 130 compares the output value of the line memory 120 with the data generated by the gray scale counter 160 under the control of the system controller 150.

The output value of the comparator 130 is printed on the sublimation photo paper through the drum 1 and the TPH 2 by driving the TPH 2 of FIG. 1 under the control of the system controller 150 as shown in FIG. 4. .

As shown in FIG. 1, 512 lines are written to the line memory 120 as shown in FIG. 3 for processing in one TPH 2, and it takes about 16 ms to heat by one TPH 2, so that Y, M, It took about 27 seconds (16ns x 512 lines x 3) to print all three colors of C. That is, the signal stored in the line memory 120 is controlled by the system controller 150 and the comparator 130 is compared with the data of the gradation counter 160 to input the compared gradation value to the TPH 140 to perform the procedure of FIG. 4. Print as

It takes 9 seconds (16ns (1 line) x 512 lines) to print one color in printing, but it takes about 27 (3 × 9) seconds to realize this because 3 colors of Y, M, and C are printed in full color. It took time and there was a problem in high speed printing.

It is therefore an object of the present invention to provide a circuit capable of printing images at high speed in a video color printer.

Another object of the present invention is to provide a circuit that allows printing using two TPH.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a circuit diagram according to the present invention. In FIG. 5, the RGB separation unit 51, the A / D conversion unit 52, the R, G, and B frame memory units 53, the RGB switch 54, and the color converter are shown in FIG. (55), the configuration, function and operation relationship of the gradation counter 80, the system controller 57 has been described and filed in the various embodiments of the present invention other than the application No. 89-20086 by the same applicant of the present patent, detailed description Omit.

The present invention describes an example in which a predetermined portion of the R, G, and B frame memories of the R, G, and B frame memory sections 58 is processed as shown in FIG. 6A. For this purpose, among the ones recorded in the R, G, and B frame memory units 58 by the control of the system controller 57, the R, G, and B switches 54 are sequentially selected. Similarly, when the value is selected as the R value, when the value is input to the color converter 55, the color converter 55 is converted to cyan (C) and input to the gradation ROM 80. The output value of the gradation ROM 80 is controlled by the system controller 57 to control the first and second line memories 58 and 59 to increase the read / write and sampling values, and to control the first and second lines by controlling the address counter 60. The storage location of the output value of the gradation 80 is designated as the two-line memory 58 and 59, starting with Yo, 1 and Yo, 257 under the control of the first and second line memories 58 and 59. The recording value is controlled to be selectively recorded as (6B, 6C) while increasing the sampling value. The recorded values of the first and second line memories 58 and 59 are controlled by the output enable stage OE of the system controller 57 and the control of the address counter 60. Read each first line (Yo, 1 to Y512.1) and (Yo.257 to Y512.267) of 58, 59) at the same time and output the value output from the gradation counter 63 and 512 dots of one line component. Two comparators 61 and 62 are used to compare 512 dots of one line component output from the first gray level counter 63 and the first and second line memories 58 and 59 in the gray scale counter 63, respectively. The first and second TPH (74, 75) is heated at the same time. When the processing of the first gradation value is finished, the gradation counter value is increased in the next gradation counter 63. When the processing of the first gradation value is completed, the gradation counter value is increased in the next gradation counter 63 when the processing of the first line value is completed. The gradation value is again compared with 512 dots of the first line component in the second comparators 61 and 62 and simultaneously heated by the control of the system controller 57 in the first and second TTPs 74 and 75 according to the comparison result. This is done. That is, the heating is performed 256 times in the first and second TPHs 74 and 75 as compared with the 256 gray levels output from the 512-bit grayscale counter 63 of one line.

Accordingly, in FIG. 5, first and second line memories 58 and 59 are connected to the output terminal of the gray-scale 80 for dividing and reading data such as FIG. 6A by line. The two-line memories 58 and 59 are connected to receive the write enable end WE and the output enable end OE signals generated from the system controller 57. The first and second line memories 58 and 59 are connected to each other. The output stage of the address counter 60, which counts 512 times when writing and 256 times when reading, is designated to designate a position to write / read data of the first and second line memories 58,59. Connected to an address bus, the address counter 60 controls the counting start time according to a control signal generated from the system controller 57, and informs the system controller 57 when 512 or 256 counting is completed. Control the operation, and the first and second line memories 58 and 59 In order to compare the read output value with the 256 gray level counter 63, the address counter 60 counts 512, and after writing is completed, the gray level counter 63 is enabled to generate 1 to 256 gray counting values. It is connected to be input to the comparators (61, 62). The first and second comparators 61 and 62 compare the outputs of the first and second line memories 58 and 59 with the values of the gray scale counter 63 256 times per line, and compare the comparison results with the first and second TTPs 74. 75), the control is performed such that the heating is performed 256 times per line by the control of the system controller 57.

Assuming that Fig. 6A is a predetermined one frame data as described above, (6B, 6C) shows an example of writing of the first and second line memories 58,59. FIG. 7 illustrates an example of a configuration relationship between the first and second TPHs 74 and 75 of FIG. 5, and FIG. 8 illustrates an example of printing on actual photo paper.

Therefore, an embodiment of the present invention will be described in detail with reference to Figs. 5 to 8, the RG separation unit 51 receives the NTSC, S-video and RGB color image signals and separates each of R, G, and B. Each of R, G, and B separated by the R, G, and B separation units 51 may be respectively formed by the first to third A / D conversion units (A / D1 to A / D3) of the A / D conversion unit 52. The sampling signal generated by the system controller 57 is converted into digital data.

The data output from the A / D converter 52 is stored in the R, G, B frame memories of the R, G, and B frame memory units 53 by the control of the system controller 57 in units of frames. The R, G, and B frame memory storage data of the R, G, and B frame memory units 53 are read by the control of the system controller 57, and R, G, and B frames are stored in accordance with the switching of the R, G, and B switches 54. Is selected for each B and input to the color converter 55.

The color converter 55 converts R, G, and B into C, M, and Y and sequentially inputs them to the grayscale 80. The data processed by the gradation ROM 80 are read in the screen configured as shown in FIG. Note that the processing up to is the same as the conventional processing method and function. In the embodiment of the present invention, it is assumed that the state stored in the R frame memory is stored as shown in FIG. 6A. Referring to the example of the present invention, the data in the R frame memory configured as shown in FIG. To write the first and second line memories 58 and 59 to the first and second line memories 58 and 59 as shown in FIGS. 6B and 6C. Is generated, and address data for specifying a position to be written in the address counter 60 is generated. To this end, the system controller 57 controls the R, G, and B switches 54, and then calculates enough time to be processed and output from the gradation ROM 80. Then, the first and second line memories 58, 59 and The address counter 6C is controlled.

When the data sufficiently processed by the gradation ROM 80 is output, the system controller 57 is enabled by the output of the write enable stage WE of the first line memory 50, and the address counter 60 is activated. Control the first line first data to be recorded. That is, Yo.1 of FIG. 6A (6A) is recorded like FIG. 6C (6C). At this time, the specified data of the line L1 is generated in the address counter 60, and when the sampling value is increased by reaching the predetermined value, the write mode of the first line memory 58 is released and the second line memory 59 is written to the write mode. The data at the point of time when the sampling is reached is written to the same address of the first memory 58 of the second memory 59. That is, the Yo.257 data of FIG. 6 (6A) is recorded as (6C). The system controller 57 again increases the internal sampling, releases the second line memory 59 from the write mode when the predetermined value is reached, and writes the first line memory 58 to the address counter 60. ), The address is increased, and the value of Y1.1 in FIG. 6A is written in the first line memory 58. That is, it records as FIG. 6 (6B). When the internal sampling of the system controller 57 is increased to reach a predetermined value, the write mode of the first line memory 58 is canceled, and the second line memory 59 is set to the write mode. Record Y1 and Y257 as shown in FIG. 6 (6C).

The above operation is repeated to write the data of FIG. 6A to the first and second line memories 58 and 59 as shown in (6B and 6C). That is, the address counter 60 counts 512 and writes the data of (6A) to the first and second line memories 58 and 59. When all of the 512 is counted, the data of (6A) is recorded in the first and second line memories 58 and 59, and the system controller 57 transmits a signal thereof. The system controller 57 receives the signal and sets the write / output enable stage WE / OE of the first and second line memories 58 and 59 to the "low" mode to enter the read mode, and then sets the address counter 60. Control to generate address data. The address data is designated data for reading the stored data from the first and second line memories 58 and 59 as shown in FIG. 6 (6B and 6C).

Meanwhile, the address counter 60 controls the gray scale counter 63 at the time when the count of 512 is completed, and starts from the first gray scale value.

In order to read the stored data as shown in Figs. 6B and 6C from the first and second line memories 58 and 59, address data is generated at the address counter 60 and simultaneously inputted. You will read YO.257 in 1 and 6C together. Then we read Y1.1 in (6B) and Y1.257 in (6C) and read one line vertically in this way. The data read from the first and second line memories 58 and 59 is compared with the gray count value output from the gray scale counter 67. The 512 bits of one line component are output from the gray counter 63 for each bit. The first and second comparators (61, 62) are sequentially compared with the first to second grayscale values from the first grayscale value, and when the first grayscale comparison is completed, the respective comparison result values are input to the first and second TTPs (74 and 75) and heated on the photo paper. .

Then, the second gray level value of the gray scale counter 63 is compared with the output values of the first and second line memories 58 and 59 again, and the above process is repeated to heat the first and second TPHs 74 and 75. Since the output value of the gradation counter 63 is 256 gradations, it is 256 times compared to 512 bits per line and is heated 256 times.

In order to heat the values of the first and second comparators 61 and 62 in the first and second TPHs 74 and 75, the system controller 57 is controlled.

Since the first and 2TPHs 74 and 75 are installed as shown in FIG. 7, they are simultaneously lowered as shown in FIG. The data of the first and second line memories 58 and 59, such as (6B and 6C), which are compared and output from the first and second comparators 61 and 62, are input to the first and second TTPs 74 and 75, and the system controller ( Under the control of 57), the first and second comparators 61 and 62 perform 256 times of heating per line with 1 to 256 gradation data. That is, it takes about 4 seconds because 256 lines are formed by two first and 2TPHs 74 and 75 to print one color.

It takes about 13 seconds (3 × 4) to process all three colors (16 × 256) Y, M, and C.

Although the embodiment of the present invention is based on the NTSC processing method, those skilled in the art can process video signals and video signals including R, G, and B in the same manner without departing from the same definition of the present invention. Make it possible.

As described above, since two TPHs are used, the printing time of Y, M, and C colors can be reduced by half, so that printing can be performed at high speed.

Claims (1)

In the printing circuit of a video color printer, a first and second line memory which converts image color R, G, and B signals into Y, M, and C, records them separately according to the even and odd fields, and records them at the same time. (58,59), an address count (60) for generating address data for storage in the first and second line memories (58, 59), and an output value of the first and second line memories (58,59). The first and second TPHs of the first and second comparators 61 and 62 to compare according to the counting value, and the plurality of TPHs 21 and 22 that are heated on the photo paper by the output data of the first and second comparators 61 and 62. High speed printing circuit in a video color printer, characterized in that (74,75).