JPS58158275A - Heat-sensitive recorder - Google Patents

Heat-sensitive recorder

Info

Publication number
JPS58158275A
JPS58158275A JP57041072A JP4107282A JPS58158275A JP S58158275 A JPS58158275 A JP S58158275A JP 57041072 A JP57041072 A JP 57041072A JP 4107282 A JP4107282 A JP 4107282A JP S58158275 A JPS58158275 A JP S58158275A
Authority
JP
Japan
Prior art keywords
blocks
block
dots
boundary
dot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57041072A
Other languages
Japanese (ja)
Inventor
Jun Kakizaki
柿崎 純
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57041072A priority Critical patent/JPS58158275A/en
Publication of JPS58158275A publication Critical patent/JPS58158275A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
    • B41J2/355Control circuits for heating-element selection

Landscapes

  • Fax Reproducing Arrangements (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce the occurrence of small white lines in the boundary of blocks by lenthening the electrification time for dots in the boundary of adjacent blocks of different print timings in the heating resistor row of facscimile, etc. CONSTITUTION:The output time for outputs from the 2nd to the 31st, among picture signals of dots of a block 32 stored in a shift register 4, is controlled by signals from a terminal 3 after the output is given to AND gates 7-1-7-30. Also, the 1st and 32nd dot outputs to be the boundary of the blocks are directly given to a dot driver 6. When all black is printed in designated blocks by the driver 8, the 1st and 32nd dot outputs become high level during the time T2, and on the other hand, the dot outputs from the 1st to 32nd become high level during the time T1. Thus, on the basis of T2>T1, the lowering of temperature in the boundary of the blocks is compensated and the occurrence of white small lines is reduced.

Description

【発明の詳細な説明】 本発明はファクシミリ、プリンタなどの感熱記録装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal recording device such as a facsimile or a printer.

ファクシミリ、プリンタなどの熱印字用発熱抵抗体列に
おいて、発熱抵抗体の全数に対して電力を同時に印加す
ることは、回路構成上複雑わるいは高価と危るので、発
熱抵抗体列をN個(Nは2以上の整数)のブロックに分
割し1ラインを多くともN個のタイミングに分割して印
字するのが通常である。第1図は5分割され九ブロック
を5回のタイミングで印字する様子と各ブロックに対応
し先金黒印字時の発熱抵抗体の平均温度分布を示すもの
であるeJI1図において各ブロックの境界で平均温度
が低く表っているのは、例えば、第3ブロツクを印字し
ているときには、第2ブロツクと第4ブロツク鉱印字を
行なっていないので、第2ブロツクと#I3プaツクの
境界及び第3プロツ/と@420ツクの境界付近では第
3ブロツクの内部に較べ熱が発散し易く、シたがって温
度が低くなることによるものである。この印字タイミン
グの差によって生じるブロックの境界における平均温度
分布の低下に起因して、印字タイミングの異なるブロッ
クの境界において印字濃度が低下し、白い#1IIi!
が残ってしまうという欠点があった。
In heating resistor arrays for thermal printing in facsimile machines, printers, etc., applying power to all of the heating resistors at the same time may be complicated or expensive due to the circuit configuration, so N heating resistor arrays ( Normally, one line is divided into blocks (N is an integer of 2 or more) and printed by dividing it into at most N timings. Figure 1 shows how 9 blocks divided into 5 are printed at 5 timings, and the average temperature distribution of the heating resistor when printing black on the tip corresponding to each block. The reason why the average temperature appears low is because, for example, when the third block is being printed, the second and fourth blocks are not printed, so the boundary between the second block and #I3 block and the This is because heat dissipates more easily near the boundary between the third block / and @420 block than inside the third block, and therefore the temperature becomes lower. Due to a decrease in the average temperature distribution at the boundaries of blocks caused by this difference in print timing, the print density decreases at the boundaries of blocks with different print timings, resulting in white #1IIi!
The disadvantage was that it left behind.

本発明は従来の上記欠点を除去する為になされたもので
ToTE1従って本発明の目的は、上記のような発熱抵
抗体の相隣)合うブロックの印字タイミンクの差に起因
する各ブロックの境界における白い細線の発生を軽減し
た感熱記録装置を提供することKある。
The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology.Accordingly, an object of the present invention is to eliminate the problems at the boundaries of each block due to the difference in printing timing between adjacent blocks of heating resistors as described above. It is an object of the present invention to provide a heat-sensitive recording device in which the occurrence of thin white lines is reduced.

前記目的を達成する恵めに、本発明による感熱記録装置
は、熱印字用発熱抵抗体列の駆動回路における全発熱抵
抗体をN個(Nは2以上の整数)のブロックに分割し、
各ブロックの全ドツトを同一タイミングで印字し、lラ
インを多くともN個のタイ〉ングに分けて印字する感熱
記録装置において、互いに隣シ合いかつ印字タイミング
の異なるブロックの境界のドツトの通電時間が長くなる
ように制御することによジブロックの境界における白い
細線の発生を軽減できる。
To achieve the above object, the thermal recording device according to the present invention divides all the heating resistors in the drive circuit of the heating resistor array for thermal printing into N blocks (N is an integer of 2 or more),
In a thermal recording device that prints all dots in each block at the same timing and prints one line by dividing it into at most N timings, the energization time of dots at the boundaries of blocks that are adjacent to each other but have different printing timings By controlling the distance so that it is long, it is possible to reduce the occurrence of thin white lines at the boundaries of diblocks.

以下、本発明をその良好な実施例について添付図面を参
照しながら具体的に説明する。
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

第2図を参照すると本発明の第1の実施例は2値画信号
の記録に関するもので、画信号入力端子1、ラッチパル
ス入力端子2.制御信号入力端子3吟の信号入力の他に
、ラッチ付き32ビットシフトレジスタ4.1728ビ
ツトの発熱抵抗体を32ビツトずつ54ブロツクのマト
リックス状に結線したサーマルヘッド5、サーマルヘッ
ド5の各ブロック32ビツトに対しラッチ付32ピツト
シフトレジスタ4のHighに対応するドラ)K1m流
を流すドツトドライバ6、アンドゲート7−1〜30サ
ーマルヘツド5の各ブロックに選択的に電圧を印加する
ブロックドライバ8を含む。
Referring to FIG. 2, the first embodiment of the present invention relates to recording a binary image signal, including an image signal input terminal 1, a latch pulse input terminal 2. In addition to the signal input from the control signal input terminal 3, there is also a 32-bit shift register with a latch, a thermal head 5, each block 32 of the thermal head 5, which has 1728-bit heating resistors connected in a matrix of 54 blocks each with 32 bits. A dot driver 6 that flows the latched 32-pit shift register 4 corresponding to the high level of the latched 32-pit shift register 4, and a block driver 8 that selectively applies voltage to each block of the AND gates 7-1 to 30 and the thermal head 5. including.

シフトレジスタ4に記憶された1ブロツク32ドツトの
画信号のうちブロックの境界以外の第2ドツト〜第31
ドツトの出力はANDゲート7−1〜30に接続されて
お少、制御信号入力端子3よシ入力される制御信号によ
って出力される時間を制御できる構成となっている。ま
たブロックの境界に尚る741ドツト及び第32ドツト
の出力はANDゲートを介することなく直接ドツトドラ
イバ6に接続されている。ラッチパルス入力端子2よp
入力されるシフトレジスタ4のラッチタイミングを指示
するラッチパルス、制御信号入力端子3よp入力される
制御信号、及びドツトドライバの入力信号を第3図に示
す。いま第2図のブロックドライバ8によって指定され
たブロックにおいて全黒を印字するとき即ちシフトレジ
スタ4の出力が全てHighのときブロックの境界に轟
る第1ドツト及び第32ドツトのドツトドライバ入力信
号Fi第3図のよりにT2の関Hjgbとなる。一方ブ
ロックの境界以外の第2ドツト〜第31ドツトのドツト
ドライバ入力は第3図に示すようにTlQ間Highと
なる。このようにしてブロックの境界のドツトへの通電
時間をそれ以外のドツトより長くする仁とによシ、クロ
ックの境界における温度低下を補ない、ブロックの境界
における白い細線の発生を軽減できる。
Of the image signals of 32 dots per block stored in the shift register 4, the 2nd to 31st dots other than the block boundaries
The outputs of the dots are connected to AND gates 7-1 to 7-30, so that the output time can be controlled by a control signal inputted through the control signal input terminal 3. Further, the outputs of the 741st dot and the 32nd dot at the block boundaries are directly connected to the dot driver 6 without going through an AND gate. Latch pulse input terminal 2 p
FIG. 3 shows the input latch pulse instructing the latch timing of the shift register 4, the control signal input from the control signal input terminal 3, and the input signal of the dot driver. When printing all black in the block designated by the block driver 8 in FIG. 2, that is, when all the outputs of the shift register 4 are High, the dot driver input signal Fi of the 1st dot and the 32nd dot is generated at the boundary of the block. According to the equation shown in FIG. 3, the function Hjgb of T2 is obtained. On the other hand, the dot driver inputs of the 2nd to 31st dots other than the block boundaries become High during TlQ as shown in FIG. In this way, by making the energization time longer for the dots at the block boundaries than for the other dots, it is possible to compensate for the temperature drop at the clock boundaries and reduce the occurrence of white thin lines at the block boundaries.

第4図は本発明の第2の実施例のブロック図で、中間調
の記録に対応するものであシ、書き込みりpツク発生回
路11.読み出しクロック発生回路12、クロック選択
用データセレクタ13及び14゜RAM15及び161
画信最大力端子17.データ選択用データセレクタ1g
、階調指定回路19゜ROM選択用デー タセvり/2
0.#!lit指定用ROM21及び22.ブロック熾
検出回路23.ラッチ付きシフトレジスタ24.ドツト
ドライノく25゜サーマルヘッド26.ブロックドライ
バ27よ構成る。
FIG. 4 is a block diagram of a second embodiment of the present invention, which corresponds to halftone recording. Read clock generation circuit 12, clock selection data selectors 13 and 14° RAM 15 and 161
Picture credit maximum power terminal 17. Data selector 1g for data selection
, gradation designation circuit 19° ROM selection data set/2
0. #! ROM 21 and 22 for lit specification. Block detection circuit 23. Shift register with latch 24. Dot Drinoku 25° thermal head 26. It consists of a block driver 27.

RAM15及び16はそれぞれ画信号lブロク2分を記
憶する容量をもってお夛、一方が画信号入力端子17か
ら入力される画信号を読み込んでいるときは、もう一方
は直前に読み込んだ画信号を読み出してデータ選択用デ
ータセレクタ18に送るといった動作を交互に行なう。
The RAMs 15 and 16 each have a capacity to store two blocks of image signals, and when one is reading the image signal input from the image signal input terminal 17, the other reads the image signal read immediately before. The operation of sending the data to the data selector 18 for data selection is performed alternately.

階調制御MAMに記憶されている画信号を繰フ返し読み
出し階調指定回路19においてそれぞれの読み出しにあ
たシ、画信号上階調指定用ROM21又は22より出力
される階調指定データを比較し、画信号〉階調指定デー
タのとき階調指定回路19の出力をHi g hとし、
それ以外のときLowとすることにより画信号に応じて
電圧印加時間を変化させることで行なう0階調指定RO
M22は21に較べ各階調において電圧印加時間が長く
々る様な階調指定データが格納しである。念だし、電圧
印加時間がO即ち白印字に対応するデータは同じものと
する。いま、ブロックト2イパ27で指定されたブロッ
クの印字を行なうときブロック端検出回路23によって
ブロックの境界を検出し、該ブロックの境界のドツトに
対する階調制御を階調指定ROM22で行ない、それ以
外のドツトの階調制御を階調指定ROM21で行なうこ
とにより、ブロックの境界のドツトへの電圧印加時間が
同じ階調におけるブロックの境界以外のドツトへの電圧
印加時間に較べて長くな力、ブロックの境界における白
い細線の発生を軽減することができる。
The image signal stored in the gradation control MAM is read out repeatedly in the gradation designation circuit 19 for each readout, and the gradation designation data output from the image signal upper gradation designation ROM 21 or 22 is compared. Then, when the image signal>gradation specification data, the output of the gradation specification circuit 19 is set to High,
At other times, 0 gradation designation RO is performed by changing the voltage application time according to the image signal by setting it to Low.
M22 stores gradation designation data such that voltage application time is longer for each gradation than M21. As a reminder, the data corresponding to the voltage application time of O, that is, white printing, are the same. Now, when printing a block specified by the block 2 printer 27, the block edge detection circuit 23 detects the boundary of the block, and the gradation control for the dots at the boundary of the block is performed by the gradation specifying ROM 22. By controlling the gradation of the dots in the gradation specifying ROM 21, the voltage application time to the dots at the block boundaries is longer than the voltage application time to the dots other than the block boundaries at the same gradation. It is possible to reduce the occurrence of thin white lines at the boundaries of

以上説明したように本発明は互いに隣シ合い、かつ印字
タイξングの異なるブロックの境界のドツトの通電時間
が長くなるよう制御することにより、ブロックの境界に
おける白い細線の発生を軽減する効果がある。
As explained above, the present invention has the effect of reducing the occurrence of thin white lines at the boundaries of blocks by controlling the energization time to be longer for the dots at the boundaries of blocks that are adjacent to each other and have different printing timings. be.

【図面の簡単な説明】[Brief explanation of drawings]

第4図は従来の1ラインを5つのブロックに分割し5回
のタイ建ングで印字する様子と各ブロックに対応し先金
黒印字時の発熱抵抗体の平均温度分布を表わす図、第2
図は本発明第1の実施例のブロック図、第3図はそのタ
インングチャート、第4図は本発明#!2の実施例のブ
ロック図である。 l・・・・−画信号入力端子、2・・・・・・ラッチパ
ルス入力端子、3・・・・・・制御信号入力端子、4・
・・・・・ラッチ付キシフトレジスタ、5・・・・・・
サーマルヘッド、6・・・・・・ドツトドライバ、7−
1〜30−・−・ANDゲ−)、11・・・・・・書き
込みクロック発生回路、12・・・・・・読み出しクロ
ック発住回路、13及び14・・・・・・クロック選択
用データセレクタ、15及び16・・・・・・RAM%
 17・・・・・・画信号入力端子、18・・・・・・
データ選択用データセレクタ、19・・・・・・階調指
定回路、20・・・・・・ROM選択用データセレクタ
、21及び22・・・・・・階調指定用ROM、23・
・・・・・ブロック端検出回路、24・・・・・・ラッ
チ付きシフトレジスタ、25・°・・・・ドツトドライ
バ、  26−・・−サーマルヘッド。 年 をIV う・・ノTハ・ノLス −ff−丁り−一一隼3I21 手続補正書(方式) 特許庁長官 殿 1、事件の表示   昭和57年 特許  願第410
72号2、発明の名称  感熱記鍮装置 3、補正をする者 事件との関係       出 願 人東京都港区芝五
丁目33番1号 (423)   日本電気株式会社 代表者 関本忠弘 4、代理人 〒108  東京都港区芝五丁目37番8号 住人三田
ビル5゜補正命令の日付 昭和57年6月29日(発送日) 6、補正の対象 明細書中の項目名 7、補正の内容 明細書第1頁13行目の「本発明は」の前に「3、発明
の詳細な説明」を挿入する。
Figure 4 shows the conventional method of dividing one line into five blocks and printing with five tie-ups, and the average temperature distribution of the heating resistor when printing black tip metal corresponding to each block.
The figure is a block diagram of the first embodiment of the present invention, FIG. 3 is a tinging chart thereof, and FIG. 4 is a block diagram of the first embodiment of the present invention. FIG. 2 is a block diagram of the second embodiment. l...-image signal input terminal, 2...latch pulse input terminal, 3...control signal input terminal, 4...
...Ki shift register with latch, 5...
Thermal head, 6... Dot driver, 7-
1 to 30---AND game), 11---Write clock generation circuit, 12---Read clock generation circuit, 13 and 14---Clock selection data Selector, 15 and 16...RAM%
17... Image signal input terminal, 18...
Data selector for data selection, 19... Gradation specification circuit, 20... Data selector for ROM selection, 21 and 22... ROM for tone specification, 23.
...Block end detection circuit, 24 ... Shift register with latch, 25 ... Dot driver, 26 ... Thermal head. IV U...ノThaノLS -ff-Chori-11 Hayabusa 3I21 Procedural amendment (method) Director General of the Patent Office 1, Indication of the case 1982 Patent Application No. 410
No. 72 No. 2, Title of the invention: Thermal brass device 3, Relationship to the amended person's case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent Address: 5-37-8 Shiba 5-chome, Minato-ku, Tokyo 108 Resident Mita Building 5゜Date of amendment order: June 29, 1980 (shipment date) 6. Name of item in the specification subject to amendment 7, Details of the contents of amendment ``3. Detailed description of the invention'' is inserted before ``the present invention'' on page 1, line 13 of the book.

Claims (1)

【特許請求の範囲】[Claims] 熱印字用発熱抵抗体列をN個(Nは2以上の整数)のブ
ロックに分割し、各ブロックの全ドツトを同一タイミン
グで印字を行ない、1ライ/を多くともN個のタイミン
グで印字する感熱記録装置において、互いに隣シ合い、
かつ印字タイ2ングの異なるブロックの境界のドツトの
通電時間を長くする制御手段を含むことを特徴とする感
熱記録装置。
Divide the heating resistor array for thermal printing into N blocks (N is an integer of 2 or more), print all dots in each block at the same timing, and print 1 line/at most N blocks. In a thermal recording device, adjacent to each other,
A thermal recording apparatus characterized in that the apparatus further comprises a control means for lengthening the energization time of the dots at the boundaries of different blocks of printing tying.
JP57041072A 1982-03-16 1982-03-16 Heat-sensitive recorder Pending JPS58158275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57041072A JPS58158275A (en) 1982-03-16 1982-03-16 Heat-sensitive recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57041072A JPS58158275A (en) 1982-03-16 1982-03-16 Heat-sensitive recorder

Publications (1)

Publication Number Publication Date
JPS58158275A true JPS58158275A (en) 1983-09-20

Family

ID=12598235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57041072A Pending JPS58158275A (en) 1982-03-16 1982-03-16 Heat-sensitive recorder

Country Status (1)

Country Link
JP (1) JPS58158275A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224772A (en) * 1985-03-29 1986-10-06 Rohm Co Ltd Printing method for thermal printing head
JPS63197667A (en) * 1987-02-13 1988-08-16 Mitsubishi Electric Corp Method and apparatus for driving thermal head

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224772A (en) * 1985-03-29 1986-10-06 Rohm Co Ltd Printing method for thermal printing head
JPS63197667A (en) * 1987-02-13 1988-08-16 Mitsubishi Electric Corp Method and apparatus for driving thermal head

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