Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
  • H10D18/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
  • H10D18/60—Gate-turn-off devices 
  • H10D18/65—Gate-turn-off devices  with turn-off by field effect 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
  • H10D62/148—Cathode regions of thyristors

Definitions

• the invention relates to a GTO-thyristor of the kind defined in the preamble of Claim 1.
• the invention also relates to a method for the manufacture of GTO-thyristors according to the preamble of Claim 7.
• a known type of GTO-thyristor is comprised of a silicon disc based on n-conductive silicon which is provided on its underside with a p-doped layer and an aluminium anode electrode and from the opposite side of which there is diffused into the disc a p-conductive layer against which n-conductor fingers lie at the top of the disc and are connected to a cathode electrode. Lying between these fingers are elongated gate-electrodes through which gate trigger current and gate turn-off current can be supplied and which are electrically insulated from the fingers of n-conductors but are able to deliver and remove charge carriers via the p-layer in relation to the n-p-junction between the fingers and the p-layer.
• a first object of the invention is to provide an improved cathode structure which is intended to reduce the resistance particularly for the turn-off currents from the gate electrodes. Another object is to enable the manufacture of thyristors with small linear tolerances, particularly by reducing the number of masks that must be used with a registering precision that corresponds to the small linear tolerances.
• the cathode structure in the manner set forth in the characterizing clause of Claim 1.
• the inventive structure is not restricted to a cathode structure, since the n-doped and p-doped regions may, just as well, be p-conducting and n-conducting regions with complementary construction in relation to what is described here and in the following. Because the two alternatives are mutually equivalent, the alternative embodiment will not be described here but is considered as claimed.
• the cathodes are small islands that are collected in segments with the islands distributed regularly in a quadratic network or in some other way, for instance in quincuncial distribution, with the gate arranged in the form of a network therebetween.
• a large number of such, equivalent segments may be distributed uniformly over the surface of a silicon disc in a component. These segments can then be checked individually in manufacture and should any segment be found faulty, this segment need not be connected to the common cathode electrode.
• the islands may have varying heights and the height of an island is normally at most 20 ⁇ m, although the islands may sometimes have heights in the order of fractions of a ⁇ m.
• the islands in the following exemplifying embodiment have a quadratic shape, it is possible to give the islands some other shape, for instance a poly-gonal, circular, ring or star-like shape. Neither is it necessary for the islands to be the same size.
• the islands may also be different, with different segment configurations over the component surface. For instance, in order to further decrease the voltage drop in the gate current supply, it may be beneficial to provide an island distribution factor which increases outwardly towards the edges when the gate-electrode is supplied with current from the centre, and also to space the segments successively further apart inwardly towards the centre, for the same purpose.
• the invention also relates to a method for manufacturing GTO-thyristors which is particularly advantageous in the case of small-patterned details, in that the number of masks required herefor is greatly reduced and, in the case of one advantageous embodiment, only one fine- pattern mask need be used.
• This is achieved with the features set forth in Claim 9.
• the method is based on the concept that subsequent to using a fine-pattern mask an etching or like process will result in raised, small islands with steep edges. Subsequent method steps can then be controlled by this three-dimensional, geometric topographical structure, particularly in combination with known anisotropically acting treatment stages.
• Figure 1 illustrates a GTO-thyristor
• Figure 2 illustrates a segment of one GTO-thyristor.
• Figure 3 is a scanning electron microscope image of part of a segment under manufacture.
• Figure 4 is, similarly, a scanning electron microscope image of a single cathode element of a GTO-thyristor.
• Figures 5a-i are cross-sectional views illustrating schematically the manufacturing stages of a GTO-transis- tor in accordance with an exemplifying embodiment.
• Figure 1 is a top view of a GTO-thyristor, and shows the thyristor roughly in its natural size.
• the thyristor has on its undersurface (not shown) an anode electrode which essentially covers said underside.
• an opening 1 Located in the centre of the thyristor is an opening 1 which extends to a gate layer, and the periphery of the upper surface nearest thereto is a metalized annular zone which is in contact with the thyristor gate electrodes.
• Surrounding the opening is a quadratic cellular structure having segments 2, which are covered on the upper side with metal electrodes which form cathode electrodes.
• a sunken insulated gate conductor network is provided between the segments, this network branching further through the segments and being intended to fire and extinguish the thyristor.
• FIG. 2 illustrates schematically one such segment 2, with the exclusion of the aforesaid covering metal electrode.
• Each such segment 2 includes a large number of small island-like silicon cathode elements 3 which are n- conducting and rest on a p-conducting base layer, which in turn rests on an n-conducting layer.
• the branch gate- electrode network is disposed in the corridors between these cathode elements 3. Because the distances between the gate electrodes and the centre of the n-p-junction between the cathode elements and the base layer beneath the islands is small, the turn-off efficiency in particular is greatly improved.
• Figure 3 illustrates cathode elements 3 during manufac ⁇ ture of the thyristor, these cathode elements having the form of islands upstanding over an exposed surface of base material.
• the mutual spacing between the islands is roughly 60 micrometers and the islands are quadratic having a side measurement of about 40 ⁇ m.
• Figure 4 illustrates one single island, from which it will be seen that said islands have extremely steep edges. The images shown in Figures 3 and 4 have been produced with the aid of a scanning electron microscope.
• the thyristor contained 176 segments with 100 cathode islands per segment, i.e. a total of 17,600 cathode islands. There is nothing to prevent, however, the dimensions of the islands being reduced and the islands packed more dense ⁇ ly, which would further improve the effect.
• the proposed inventive method of manufacture namely enables the registering problems and other problems to be reduced, which in the case of miniaturization otherwise quickly lead to reduced yield of manufacture.
• the number of cathode islands per segment can thus vary within wide limits, e.g. 1-10,000, and the size of the elementary cells may be from 100 x 100 ⁇ m, as in the case of the illustrated embodiment, down to 20 x 20 ⁇ m and smaller. This is because the islands can be produced with the aid of only one single mask.
• the connection of the islands of the elementary cells with a common conducting layer for each segment requires a mask which requires considerably less registering precision.
• the various segments can then be tested individually and those segments which do not function satisfactorily can be eliminated, by etching away the cathode contact of such segments.
• Figure 5a is a cross-sectional view of part of a silicon disc having a thickness of about 0.5 mm.
• a p-doped layer has been provided on the underside of the disc. This layer may also include a short circuiting pattern con ⁇ sisting of n-doped regions.
• An aluminium layer is then provided on the underside thereof.
• the disc is initially N-doped.
• a P-layer 51 has been doped-in from the top of the disc, whereafter a N - doped layer 52 has been formed on top of the P-layer 51.
• Islands such as those illustrated in Figures 3 and 4 are produced in the layer 52. This is achieved by the steps of applying a photo-resist layer 53, exposing said layer with a mask and developing the layer, and then anisotro- pically etching the silicon, down to a small distance beneath the boundary 54 between the layers 51 and 52. This results in the cross-sectional configuration shown in Figure 5b.
• the silicon surfaces are now oxidized to form an oxide layer 55, which is made relatively thin between the islands (anisotropic process) .
• This oxide layer is etched away partially in an aniso ⁇ tropic process, thereby exposing the interspaces between the islands while leaving the islands with their steep edges oxide-coated.
• the exposed surfaces are provided with a thin p -layer 56, for instance by ion implantation.
• the oxide-coated surfaces are therewith only slightly influenced, and a con- figuration according to Figure 5d is obtained.
• a metal layer e.g. an aluminium layer 57
• a photo-resist layer 58 is spun over the aluminium layer.
• some other product such as an insulating polymer. The resultant configuration is shown in Figure 5e.
• the spun photo-resist layer 58 is then etched down partially, so as to leave a resist layer 59 which covers the aluminium layer 57 between the islands. This results in the configuration shown in Figure 5f. All of the exposed aluminium is then etched away, in ⁇ cluding the aluminium which borders sideways on the residual photo-resist layer 59, while leaving the alumi ⁇ nium layer 60 which is protected by the photo-resist layer 59. The photo-resist is then removed, resulting in the configuration shown in Figure 5g, with the remaining aluminium layer 60 which is bordered on the steep edges of the islands by a gap 61.
• a polyimide solution is then spun onto the transistor and allowed to dry, whereafter the spun polyimide is etched down, roughly the same as the layer 58 in Figure 5e, until only the interspaces between the islands are filled with insulating polyamide 61, preferably to a level corresponding to the N-silicon upper surface 52 of the islands. This results in the configuration shown in Figure 5h.
• That part of the oxide layer 55 which covers the upper surfaces of the islands is now etched away and the whole is covered with a metal contact layer 62, such as an aluminium contact layer.
• a metal contact layer 62 such as an aluminium contact layer.
• the main thyristor current can now flow from the contact layer 62 to the N-layer 52 of the cathode island, via the base layer 51 down into the N-base layer to the anode connection layer 50.
• the surrounding gate conductors 60 are included in a conductor network structure which surrounds all cathode islands and segments and is insulated from the contact layer 62 by the polyamide layer 61 and has good contact with the P-base layer 51 via the P -layer 56.
• the proposed method is character- i- zed by the fact that it avoids the use of more than one sole small scale mask with the aid of a self-registering principle.
• the mask required to obtain contact layer 62 has a completely different and larger scale, which is on the section standard and not on the individual standard of the small cathodes.

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• 1991
  • 1991-07-01 SE SE9102042A patent/SE470226B/sv not_active IP Right Cessation
• 1992
  • 1992-06-25 JP JP5501764A patent/JPH06511601A/ja active Pending
  • 1992-06-25 WO PCT/SE1992/000472 patent/WO1993001620A1/en not_active Application Discontinuation
  • 1992-06-25 EP EP92915295A patent/EP0592587A1/en not_active Withdrawn

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