EP0559093B1 - Récepteur radio mobile digital - Google Patents

Récepteur radio mobile digital Download PDF

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Publication number
EP0559093B1
EP0559093B1 EP93103062A EP93103062A EP0559093B1 EP 0559093 B1 EP0559093 B1 EP 0559093B1 EP 93103062 A EP93103062 A EP 93103062A EP 93103062 A EP93103062 A EP 93103062A EP 0559093 B1 EP0559093 B1 EP 0559093B1
Authority
EP
European Patent Office
Prior art keywords
output
gain
converter
digital signal
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP93103062A
Other languages
German (de)
English (en)
Other versions
EP0559093A1 (fr
Inventor
Kazuya C/O Nec Corp. Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0559093A1 publication Critical patent/EP0559093A1/fr
Application granted granted Critical
Publication of EP0559093B1 publication Critical patent/EP0559093B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H03D3/008—Compensating DC offsets
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0025—Gain control circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/005—Analog to digital conversion

Definitions

  • the present invention relates to a digital mobile radio receiver, especially a receiver using a limiter amplifier.
  • a receiving unit of a conventional digital mobile receiver comprises the intermediate frequency filter 1 to restrict a band, the limiter amplifier 2 to amplify and restrict an amplitude for the output of the intermediate frequency filter 1, the orthogonal detector 3 orthogonally detecting and outputting I and Q components, the low pass filters 4 and 5 removing useless waves from I and Q components, the A/D converters 6 and 7 converting an output of the low pass filters to a digital value, and the digital signal processing unit 8 regenerating a received signal.
  • the intermediate frequency filter 1 restricts a band for the intermediate frequency signal IF 0 and outputs the output IF 1 as the intermediate frequency filter 1.
  • the limiter amplifier 2 amplifies the output IF 1 and restricts the amplitude thereof, and outputs the output IF 2 as the limiter amplifier 2.
  • the orthogonal detector 3 orthogonally detects the output IF 2 and outputs I 0 as the I component and Q 0 as the Q component. Continuously these outputs I 0 and Q 0 come to be the outputs I 1 and Q 1 of the low pass filters 4 and 5 after useless waves thereof are respectively removed by the low pass filters 4 and 5.
  • the A/D converters 6 and 7 convert these outputs I 1 and Q 1 to the digital values from the analog values and output the outputs I 2 and Q 2 as the outputs of the respective A/D converters, and the outputs I 2 and Q 2 are given the digital signal process by the digital signal processing unit 8 to be regenerated
  • the limiter amplifier 2 is saturated by the interfering wave and outputs IF 2 without amplifying sufficiently the amplitude of the desired wave. And when the output IF 2 of the limiter amplifier 2 is inputted to the detector 3 with this state, if the detector 3 is of a linear type, the desired wave component of the outputs I 0 and Q 0 of the detector 3 receives more deterioration for the insertion loss.
  • US-A-5 001 776 discloses a communication system with adaptive transceivers to control intermodulation distortion.
  • the object of this invention is to offer a digital mobile radio receiver with improved a deterioration of a receiving characteristic.
  • the digital mobile radio receiver has a head amplifier able to vary a gain installed between a low pass filter and an A/D converter, and by controlling the gain for this head amplifier according to the command from the digital signal processing unit, the input level of the A/D converter can be always made steady, and the deterioration of the effective resolution of the receiving can be improved.
  • FIG.1 is a block diagram with necessary parts of an embodiment of the digital mobile radio receiver of the present invention.
  • FIG.2 is a circuit diagram showing a circuit comprising a head amplifier able to vary a gain and a gain control unit.
  • FIG.3 is a figure to describe an operation of the embodiment in FIG.1.
  • FIG.4 is a flowchart diagram showing an operation of the digital signal processing unit in FIG.1.
  • FIG.5 is a figure showing an example of a maximum value of an input level into an A/D converter.
  • FIG.6 is a block diagram with necessary parts of a conventional digital mobile radio receiver.
  • Figs.1 to 5 show an embodiment of a digital mobile radio receiver by the present invention.
  • Fig.1 shows a block diagram with necessary parts of an embodiment of a digital mobile radio receiver of the present invention
  • Fig.2 shows a circuit diagram showing a circuit comprising a head amplifier able to vary a gain and a gain control unit
  • Fig.3 is a diagram to definitely describe an operation of the embodiment in Fig.1
  • Fig.4 is a flowchart showing an operation of a digital signal processing unit
  • Fig.5 is a figure showing an example of a maximum value of an input level to an A/D converter.
  • 21 is an intermediate frequency filter
  • 22 is a limiter amplifier
  • 23 is an orthogonal detector
  • 24 and 25 are low pass filters
  • 26 and 27 are A/D converters.
  • 30 is a digital signal processing unit
  • 31 and 32 are head amplifiers
  • 33 is a gain control unit.
  • the characteristic of this embodiment is that the head amplifier 31 able to vary a gain is installed between the low pass filter 24 and the A/D converter 26, and also the head amplifier 32 able to vary a gain is installed between the low pass filter 25 and the A/D converter 27, respectively.
  • the digital signal processing unit 30 commanding the gain control unit 33 to provide the gain information of the head amplifiers 31 and 32 and the gain control unit 33 controlling the gain of the head amplifiers 31 and 32 according to the command from the digital signal processing unit 30 are installed.
  • the circuit A comprising the head amplifiers 31 and 32 and the gain control unit 33 is comprised of the operational amplifier 41 and the variable resistor 42, to be able to restrict a gain of the operational amplifier by the variable resistor 42.
  • the digital signal processing unit 30 is comprised of a digital signal processor memorizing in the memory a program to estimate a maximum value of the input to the A/D converters 26 and 27 based on the output level of the A/D converters 26 and 27, decide whether the input level to the A/D converters 26 and 27 is adequate or not based on the maximum value of the input, and command the gain control unit 33 to provide the adequate gain information according to the decision information.
  • the digital signal processor has the excellent high speed performance, and the advantage to be able to easily change the count number and so on of the digital signal processing unit 30 by modifying the program as described as below.
  • the outputs I 2 and Q 2 of the A/D converters 26 and 27 are respectively read by the digital signal processing unit 30.
  • the digital signal processing unit 30 estimates a maximum value of the input to the A/D converter by the outputs I 2 and Q 2 of the A/D converters 26 and 27, decides, based on the maximum value of the input, whether the levels of the inputs I 1 ' and Q 1 ' to the A/D converters 26 and 27 are adequate or not. If the levels are not adequate the digital signal processing unit 30 commands the gain control unit 33 to provide the adequate information about the gain.
  • the gain control unit 33 controls the gain of the head amplifiers 31 and 32 based on the command from the digital signal processing unit 30. And the outputs I 1 and Q 1 of the low pass filters 24 and 25 are inputted to the head amplifiers 31 and 32, amplified at an adequate level, and outputted as the outputs I 1 ' and Q 2 ', so that the level of the inputs I 1 ' and Q 2 ' to the A/D converters 26 and 27 are always and adequately kept.
  • Fig.3A shows a case to input the output IF 1 of the intermediate frequency filter with only the desired wave to the limiter amplifier 22
  • Fig.3B shows another case to input the output IF 1 of the intermediate frequency filter with the interfering wave of which amplitude is bigger than the desired wave to the limiter amplifier 22.
  • I component is shown after orthogonally detection
  • D shows the desired wave spectrum
  • U shows the interfering wave spectrum, respectively.
  • Fig.3A only the desired wave exists in the output IF 1 of the intermediate frequency filter, so that the limiter amplifier 22 is saturated by the desired wave. Therefore the output IF 2 of the limiter amplifier 22 is outputted with the state that the desired wave is amplified up to the amplitude restriction. After that the output IF 2 of the limiter amplifier 22 is inputted to the orthogonal detector 23 and comes to be the output I 0 of the orthogonal detector 23, and further the output I 0 of the orthogonal detector 23 is inputted to the low pass filter 24 and comes to be the output I 1 of the low pass filter 24.
  • the interfering wave component is not involved in the output I 0 of the orthogonal detector 23, so that the output I 1 comes to be same in wave form as the output I 0 of the orthogonal detector 23, and also receives the amplitude attenuation only for the insertion loss of the low pass filter 24.
  • the output I 1 of the low pass filter 24 is an ideal signal and also not necessarily amplified by the head amplifier 31, so that this state is made as a standard and the gain of the head amplifier 31 is made 1.
  • the limiter amplifier 22 if inputting the output IF 1 of the intermediate frequency filter containing an interfering wave of which amplitude is bigger than the desired wave, the limiter amplifier 22 is saturated by the interfering wave. Therefore the output IF 2 of the limiter amplifier 22 is outputted without amplified sufficiently for the desired wave.
  • the desired wave spectrum D and interfering wave spectrum U in the output IF 2 of the limiter amplifier in Fig.3B show a figure of said state (one unable to amplify sufficiently for the desired wave).
  • the output IF 2 of the limiter amplifier 22 is inputted to the orthogonal detector 23 with this state and comes to be the output I 0 of the orthogonal detector 23, the interfering wave component is removed by the low pass filter 24, and the output I 1 of the low pass filter 24 with only the desired wave component is obtained.
  • the level of the output I 1 of the low pass filter 24 is more attenuated than the insertion loss of the low pass filter 24 compared with the level of the output I 0 of the orthogonal detector 23. Therefore the amplitude of the output I 1 of the low pass filter 24 gets smaller compared with the case of Fig.3A.
  • the gain of the head amplifier 31 is made bigger than 1 by the indication cf the gain control unit 33, and the output I 1 ' having an amplified amplitude of the output I 1 of the low pass filter 24 is outputted from the head amplifier.
  • N is a variable counting the number of data reading the outputs I 2 and Q 2 of the A/D converter inputted to the digital signal processing unit 30, No is a number of the reading data that has been predetermined, n is integer, A is the input range of the A/D converter, and a and b are real numbers.
  • the digital signal processing unit 30 reads the outputs I 2 and Q 2 of the A/D converters 26 and 27, calculates I 2 2 +Q 2 2 based on the outputs I 2 and Q 2 of the A/D converters 26 and 27, and stores the result in the memory. This operation is repeated No times.
  • a head amplifier able to vary a gain is installed between a low pass filter and an A/D converter, further more by installing a gain control unit to control a gain of the head amplifier according to a command from a digital signal processing unit, an input level of the A/D converter can be kept steady.
  • the present invention even if a limiter amplifier is saturated by an interfering wave the received signal can be detected and regenerated by the same resolution as the case without any interfering waves.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Noise Elimination (AREA)
  • Mobile Radio Communication Systems (AREA)

Claims (3)

  1. Récepteur radio mobile numérique comprenant un amplificateur limiteur (22) amplifiant un signal à fréquence intermédiaire, un détecteur orthogonal (23) détectant de façon orthogonale un signal de sortie de l'amplificateur limiteur (22) pour délivrer des composantes I et Q, un filtre passe-bas (24, 25) éliminant, desdites composantes I et Q, les ondes inutiles, un convertisseur A/N (26, 27) convertissant un signal de sortie du filtre passe-bas (24, 25) en une valeur numérique, et une unité de traitement de signal numérique (30) recevant un signal de sortie du convertisseur A/N (26, 27), et comprenant :
    un préamplificateur (31, 32) capable de faire varier un gain et installé entre ledit filtre passe-bas (24, 25) et ledit convertisseur A/N (26, 27) ; et
    une unité de commande de gain (33) commandant un gain dudit préamplificateur (31, 32) en fonction d'une commande délivrée par ladite unité de traitement de signal numérique (30).
  2. Récepteur radio mobile numérique selon la revendication 1, comportant un circuit composé du préamplificateur capable de faire varier un gain et l'unité de commande de gain comprenant :
    un amplificateur opérationnel (41) ; et
    une résistance variable (42).
  3. Récepteur radio mobile numérique selon la revendication 1 ou 2, dans lequel l'unité de traitement de signal numérique (30) comprend :
    un processeur de signal numérique mémorisant dans une mémoire un programme pour estimer une valeur maximale d'un signal d'entrée dans un convertisseur A/N sur la base d'un niveau de sortie du convertisseur A/N, décider si le niveau d'entrée du convertisseur A/N est adéquat ou non sur la base de la valeur maximale d'un signal d'entrée et commander l'unité de commande de gain de manière à délivrer une information de gain adéquate selon l'information de décision.
EP93103062A 1992-02-29 1993-02-26 Récepteur radio mobile digital Expired - Lifetime EP0559093B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4079275A JP2773524B2 (ja) 1992-02-29 1992-02-29 ディジタル移動無線受信機
JP79275/92 1992-02-29

Publications (2)

Publication Number Publication Date
EP0559093A1 EP0559093A1 (fr) 1993-09-08
EP0559093B1 true EP0559093B1 (fr) 1998-12-02

Family

ID=13685320

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93103062A Expired - Lifetime EP0559093B1 (fr) 1992-02-29 1993-02-26 Récepteur radio mobile digital

Country Status (4)

Country Link
US (1) US5465407A (fr)
EP (1) EP0559093B1 (fr)
JP (1) JP2773524B2 (fr)
DE (1) DE69322299T2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548594A (en) * 1993-12-28 1996-08-20 Nec Corporation Compact AGC circuit with stable characteristics
DE19805547C1 (de) * 1998-02-11 1999-09-09 Siemens Ag Digitaler Empfänger mit automatischer Verstärkungsregelung
US6052030A (en) * 1998-05-04 2000-04-18 Lucent Technologies Inc. Low voltage variable gain amplifier with feedback
JP3214463B2 (ja) * 1998-10-21 2001-10-02 日本電気株式会社 無線通信装置
JP2002026750A (ja) * 2000-07-07 2002-01-25 Pioneer Electronic Corp 受信機
GR1003688B (el) * 2000-07-14 2001-10-05 Ιντρακομ Α.Ε. Ελληνικη Βιομηχανια Τηλεπικοινωνιων Και Συστηματ... Μηχανισμος διορθωσης τασης εκτροπης και ενισχυτης ελεγχομενου κερδους σε δεκτες αμεσης μεταδοσης.
SE521838C2 (sv) * 2001-02-16 2003-12-09 Nat Semiconductor Corp Metod och anordning för automatisk förstärkningsreglering
US6793632B2 (en) * 2001-06-12 2004-09-21 Lifescan, Inc. Percutaneous biological fluid constituent sampling and measurement devices and methods
US7400870B2 (en) * 2001-10-30 2008-07-15 Texas Instruments Incorporated Hardware loop for automatic gain control
US20040052320A1 (en) * 2002-02-20 2004-03-18 Lennen Gary R. Point-to-multipoint burst modem automatic gain control
GB2404257B (en) * 2003-07-24 2006-07-19 Univ Cardiff High frequency circuit analyser

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK163699C (da) * 1986-02-11 1992-08-17 Poul Richter Joergensen Fremgangsmaade til automatisk forstaerkningsstyring af et signal samt et kredsloeb til udoevelse af fremgangsmaaden
US4829570A (en) * 1987-05-22 1989-05-09 Recoton Corporation Wireless remote speaker system
US5001776A (en) * 1988-10-27 1991-03-19 Motorola Inc. Communication system with adaptive transceivers to control intermodulation distortion
US5163159A (en) * 1990-07-30 1992-11-10 Motorola, Inc. Dual mode automatic frequency control

Also Published As

Publication number Publication date
DE69322299T2 (de) 1999-04-29
US5465407A (en) 1995-11-07
EP0559093A1 (fr) 1993-09-08
JPH05244025A (ja) 1993-09-21
JP2773524B2 (ja) 1998-07-09
DE69322299D1 (de) 1999-01-14

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