EP0558654B1 - Cellule de memoire associative a double acces et reseau matriciel forme par de telles cellules - Google Patents

Cellule de memoire associative a double acces et reseau matriciel forme par de telles cellules Download PDF

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Publication number
EP0558654B1
EP0558654B1 EP92901523A EP92901523A EP0558654B1 EP 0558654 B1 EP0558654 B1 EP 0558654B1 EP 92901523 A EP92901523 A EP 92901523A EP 92901523 A EP92901523 A EP 92901523A EP 0558654 B1 EP0558654 B1 EP 0558654B1
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Prior art keywords
cells
data
signal
bit
cam
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English (en)
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EP0558654A1 (fr
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David Chin-Chung Lee
Jeffery Lee Easley
Ashgar Kamal Malik
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Unisys Corp
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Unisys Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

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  • This disclosure pertains to content addressable memories which can execute a search-compare operation in conjunction with a Read operation in the same clock cycle.
  • a key feature in the use of computer systems is an available memory which can provide the requisite data needed by the processing unit in the system.
  • a special application of memory is used in many computer systems which provide a cache memory unit which is closely associated with the central processing unit (CPU) in order to provide frequently used memory data rapidly to the CPU without requiring the added delay of having to address and access the main memory unit.
  • CPU central processing unit
  • the content addressable memory or CAM is a structure which uses associative memory circuits in order to do memory searches.
  • the conventional content addressable memory is generally constructed in very large scale integrated circuits (VLSI) by using a memory latch coupled with a comparison circuit.
  • VLSI very large scale integrated circuits
  • CAM content addressable memory
  • the content addressable memory circuitry has many applications often in cache designs where it is desired to store recently used memory addresses in combination with the associated data that corresponds to these addresses. These associated data are stored locally near the processor in a random access memory (RAM).
  • RAM random access memory
  • the CAM can store a recently used data address which then can be used to point to a local memory location (in RAM) holding the associated data.
  • the CAM search results in a "match” then faster access to the local storage RAM is performed instead of the longer time and slower fetch period required to access the main memory.
  • FIG. 1A shows a typically standard content addressable memory in block diagram form.
  • the content addressable memory CAM 200 is a latticed array composed of CAM cells 300.
  • a diagram of the format of the conventional CAM cell 200 is shown in FIG. 2.
  • FIG. 1B illustrates a 4 X 4 array of CAM cells forming a CAM.
  • FIG. 1A is used to show how each one of the CAM cells is connected and operated.
  • the CAM cell 300 (as one example of the many CAM cells involved) is provided with a word line 202 which carries an address. As seen in FIG. 1B, there is a word address lines 202a, 202b, 202c, 202d for each row of CAM cells (which carry a data word). Also the CAM cell 300 has a match "hit" line 204 which exits through a first output 205 in FIG. 1A.
  • a set of hit lines 204a - 204d exits from each row of CAM cells.
  • the search key/data-in is a set of digital input lines in FIG. 1A and represented by line 222, Fig. 1A, and which are applied, after splitting, by means of inversion, into bit line 206 and bit line 208, Fig. 1A, to provide an input to the CAM 300 (and all of the other CAM cells involved) in a given row.
  • these inputs are shown as D1, D2, D3, D4.
  • the "search” is initiated by an activator signal on line 220, Fig. 1A, 1B, through the OR gate 228 which also has an input from the Write activating signal 218, FIG. 1B.
  • the Read signal on line 216 FIG. 1A is used to activate Transistors Td 1 and Td 2 in order to enable the sense amplifier 224 to output data on line 226.
  • the Read activating line 216, Fig. 1A is also seen to feed into OR gate 214 whose output is then sent as one input to the AND gate 212.
  • the address decoder 210 provides address data input into AND gate 212 which provides for selection of the word line 202.
  • the OR gate 228, Fig. 1A receives inputs from the Write line 218 and from the Search activating line 220 such that only one of these lines 218 and 220, Fig. 1A, will activate the output of the OR gate 228.
  • the Search activating line 220 when operative through the OR gate 228 will activate the transistors Ts 1 and Ts 2 so that the search key data may enter on the data-in line 222 and be conveyed on the bit lines 206 and 208 up to the CAM cell 300.
  • FIG. 1B is a more detailed view of FIG. 1A in order to indicate how line 202 of FIG. 1A is really a group of word lines 202 a , 202 b , 202 c , 202 c , in FIG. 1B.
  • the Data In/Search Key line 222 of FIG. 1A is actually a set of multiple lines D 1 , D 2 , D 3 , D 4 of FIG. 1B.
  • the conventional CAM block diagram of FIG. 1A is expressed only in schematic form since there are a multiplicity of the CAM cells 300 and there is also a multiplicity of input address lines, data input/search key lines and also a multiplicity of data output lines.
  • FIG. 1B there is indicated a more realistic representation of a conventional content addressable memory or CAM.
  • an array of CAM cells such that the first row of CAM cells are designated Cll, C12, C13, and C14. This represents the cell positioning in row 1 and the sequence in the CAM array to show which numbered position in the cell rests.
  • the second row of CAM cells is designated C21, C22, C23, C24 which last unit represents the CAM cell in the second row and in the fourth column.
  • FIG. 1B there are a series of word address line inputs designated 202 a , 202 b , 202 c , and 202 d . Each of these lines is an address input which can access one row of CAM cells. Thus if line 202 b is being activated, it will access the CAM cells C21, C22, C23, C24 which represents 4 bits of data holding a 4 bit word.
  • FIG. 1B there are seen a set of "match" lines designated 204 a , 204 b , 204 c , and 204 d .
  • Each of these lines is an output line which represents the first word in the first row, the second word in the second row, the third word in the third row, and the fourth word in the fourth row such that when one of these match lines is activated, it indicates that the particular data bit word (4 bit word) in that particular row has been matched by input search-key data which has been applied to the input lines D 1 , D 2 , D 3 , and D 4 .
  • the input lines D 1 through D 4 should represent the bits 1001
  • the same data of 1001 is also residing in the second row of CAM cells (C21 through C24) then there is a match or "hit" which is accomplished so that the output line 204 b will be activated and will convey a signal to the logic unit L i which will tell the logic unit which particular address was found to contain the data that matched the input lines D 1 , D 2 , D 3 , and D 4 .
  • a Read line 216 which is used to activate a set of 4 groups of transistors designated R1a, R1b, R2a, R2b, R3a, R3b, and R4a, R4b. These transistors are activated by the Read line 216 so that if an address for the word line 202 c is activated, then the data residing in cells C 31 , C 32 , C 33 , C 34 will be transmitted through the sense Amplifiers A 1 , A 2 , A 3 , A 4 to the Data Out lines D01, D02, D03 and D04.
  • each "column" of CAM cells will have a "pair" of output lines (which pass through the Read line transistors R 1 a, R 1 b) for example, which connect to the output lines 206 a1 and 206 b1 which are the output lines for the first column of CAM cells.
  • the output data signals will pass through the sense amplifiers A1, A2, A3, A4 in order to provide the data out signal on lines D01, D02, D03, D04.
  • the chief operating function of the content addressable memory is the ability to search the data in the various rows of words, which in this example of FIG. 1B shows that there are 4 rows of words and each word has a content of 4 bits.
  • the search-key input lines D1, D2, D3, and D4 and enabling the transistors SW for each of the columns the bit data on lines D1 through D4 will be transmitted up through each column of the series of data words in the content addressable memory 200.
  • the match or hit line 204 c would be activated in order to send a signal to the logic L i which would indicate that the address residing in the third word line, that is to say, row 3 of CAM cells C31 through C34, is the address being read out on lines DO, through DO4.
  • This improved condition can be realized by the architecture of the CAM system described hereinafter.
  • the "standard type" of CAM cell 300 is seen in FIG. 2 as being composed of transistors having certain functions.
  • the area of transistors marked TC is the conventional flip-flop set of transistors in which one pair of transistors involves the "set mode" while the other pair of transistors involves the "reset mode".
  • the area marked C1 involves 2 transistors which provide the conventional compare operation for the "reset mode” while the area marked C2 provides for 2 transistors which provide the conventional compare operation for the "set mode”.
  • bit lines 206 and 208 are the input/output lines for the reading-in and writing-out of data.
  • the word line address line WL is designated as 202 in order to provide an output address while the match line 204 is the hit line which is output as 205.
  • FIG. 3 the timing operation for a Search and for a Read of the content addressable memory, CAM, (shown in FIGS. 1A and 2) will be observed.
  • the first line of FIG. 3 shows the clock signal with the first clock being designated as T1 and the second clock being designated as T2.
  • the activity of the Search-key occurs in the area of the first clock with a slight overlap into the second clock.
  • the execution of the "match" operation occurs toward the end of the first clock mainly into the second clock.
  • the word line address on line 202 (FIG. 1A) is seen to function shortly after the beginning of the second clock in that the read lines signal activation occurs shortly after the initiation of the second clock. It will be noted that the Data-Out on line 226 of FIG. 1A does not occur till the end portion of the second clock and on outward into the third clock. Thus it is seen that more than 2 clock periods are necessary in order to provide the functions of search-compare, match ("hit") operation; and then the action of the word line address with Read activation and Data readout, then takes additional clock time.
  • operation requires that there first be a search compare operation to see if a particular data word exists in the CAM. And then there is the need to read the contents of the CAM, (assuming that a hit or match has occurred), resulting in a second operation for read out of the word which requires an additional system clock.
  • the Search key data is sent through the bit lines (106, 108) to be compared with the contents of a selected address. If the Search key data matches the contents of a selected address, this results in a match or hit signal coming out through line 104 of Fig.4 (comparable to output 205 on line 204, FIG. 1A).
  • An object of the present invention is to obviate the extended time-loss period and eliminate need for multiple clock cycles in accomplishing the Search-compare and data Read actions by permitting the execution of a Search-Compare-Read operation in the very same cycle.
  • a memory cell for use in a content addressable memory array comprising first transistor means for holding a set bit signal and its complement reset bit signal, second transistor means for comparing an input search signal bit and its complement, respectively, with said set bit signal and said reset bit signal, write line means, when activated, for enabling said first transistor means during a Write operation to insert said set bit signal and said reset bit signal, first port means for inserting said set bit signal and said reset bit signal into said first transistor means or applying said search signal bit to said second transistor means and match line means for output of a match signal when said search signal bit corresponds to the set bit signal residing in said first transistor means, characterized by second port means for output of said set bit signal from said first transistor means during a Read operation, said second port means being separate from said first port means.
  • An enhanced architecture is provided for a content addressable memory which permits a considerable shortening of operation time in that the compare/read operation can be accomplished in the same clock cycle.
  • a dual ported content addressable memory which includes a first and second word line and a READ circuitry unit (sense amplifier) which permits the near simultaneous operation for the compare and read operation to occur within one clock cycle.
  • a newly organized CAM cell is provided with separate lines for Data-In/Search operation and for Data-Out Operation such that Data-In and Data-Out can occur concurrently within the same clock cycle.
  • An additional word line for addressing the CAM array on "Read Operations” is provided so that a first word line addresses the CAM array for "Write” operations and second word line addresses the CAM array for "Read” Operations.
  • the two ports, Data-In and Data-Out, are separate so that no sharing or interference occurs between the two ports and so that the Search-Compare action and the Read action can occur concurrently in the same clock cycle.
  • FIG. 4 shows a schematic drawing of the improved CAM array 101.
  • the architecture of the CAM cell array 101 permits the use of two different addresses which are decoded by the Write decoder 110 w and the Read decoder 110 r .
  • Control line 114 which feeds AND gate 112 insures that the Write address and the Read address do not occur at the same instant where a conflict might occur.
  • the first port via line 122 is the Data-In/Search port.
  • the second port is the line 126 which is the Data-Out port.
  • the incoming data will be compared with the data in each row of cells. If a "match" occurs, then the hit line 104 (for that particular row of data) will be activated to inform an external logic unit that a hit has occurred.
  • the improved architecture for the dual port content addressable memory cell 100 refers to the standard set and reset flip-flops.
  • the areas designated C1 and C2 represent the standard comparison circuitry.
  • the write word line 102 is seen connected to the set and reset flip-flops in the area TC.
  • the match (hit) line 104 is seen connected to the comparison circuitry of C1 and C2 to provide an output on 104.
  • the Read word line 116 provides for addressing a row of CAM cells during the Read operation.
  • the transistors Q1 and Q2 are added to each of the memory cells of the array which forms the content addressable memory.
  • the transistors Q1 and Q2 form a DATA-OUT port for Read-Out and this is labeled as the second port 126.
  • the gates of the transistors Q1 and Q2 are controlled, respectively, by the contents of the flip-flop transistor cells and the Read word line 116 (READ-WL).
  • the transistors Q1 and Q2 operate as pull-down devices of the read bit line 126 (READ-BIT).
  • the capacitance of the read-bit line 126 cannot affect the contents of the cells or the gate capacitance of Q1.
  • the READ function is a very stable operation.
  • the Data-In port, line 122 of FIG. 4, and the data-out port 126 are seen to be separate ports which do not have any sharing function or interfering functions between the two of them.
  • the dual port content addressable memory shown therein is capable of having separate decoders for the Write enable selection and for the Read enable selection. These are shown as the Write Decoder 110 w and Read Decoder 110 r .
  • FIGS. 4 & 5 which indicate the CAM cell 100 (FIG. 5) and the content addressable memory 101 array of Fig. 4 which uses a multiple lattice of CAM cells, (rows of CAM cells) it will be seen that the contents of a selected memory address is read out on the Data-out line 126.
  • the Search key data is sent on in through the Data-In lines 122 FIG. 4 (through the bit lines 106 and 108 FIG. 4) to be compared with the contents of a selected address residing in some row of the content addressable memory 101. If a match occurs, to develop a "true” signal, this means that the Search key data input on line 122 and the contents of one row of the content addressable memory 101, are "identical", therefore aborting the evaluation but activating the hit line 104 for that particular row of CAM cells. On the other hand, if the match on line 105 is false, then a "miss" condition signal is indicated.
  • the Data-Out-Line 126 (Read Bit, Fig. 5) operates to allow data to be output and during this time, the Search-Key of line 122 (FIG. 4) and bit lines 106 and 108 (FIG. 5) operate to enable the match (hit) line 104 (through C1 and C2) so that the Search-key and the match lines are functioning through most of the first clock cycle, T1, enabling the Data-Out-Line 126 to output the required data throughout the first clock cycle.
  • Write enable signal (Write WL102) and input port bit line 106 (and its complement 108) can operate concurrently in one clock cycle to write data into the memory array.
  • search input signal on the input port bit line 106 (and its complement 108) can operate concurrently in one clock cycle, to search data in the memory and activate the match line 104 to designate a "hit" (coincidence of memory data).
  • the Read enable signal (Read WL 116) can operate concurrently with the output port line (126, FIGS. 4 and 5), in one clock cycle, to Read-out the data residing in an addressed row of cells.
  • the dual ported content addressable memory array using the newly organized CAM cells described herein can be especially efficacious when used as a cache unit in a processor such that address-data residing in the array can be used to directly access information data in an associated RAM which becomes immediately available to the processor without the relatively long delays involved in accessing the information -data from an associated main memory.

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Abstract

L'invention se rapporte à une cellule de mémoire associative améliorée, qui comporte deux lignes d'adresse exploitables indépendamment pour une opération de lecture ou pour une opération d'écriture. La cellule est en outre pourvue de deux portes d'accès, dont la première permet soit une entrée de données pour les opérations d'écriture soit une entrée de données pour les opérations de recherche-comparaison, et dont la seconde porte d'accès (sortie de données) est connectée séparément pour permettre l'extraction des données résidant dans la cellule. Chacune des cellules de mémoire associative comporte également une sortie (obtention de correspondance) de ligne de coïncidence, pour indiquer le moment où un bit ou un mot de recherche d'entrée coïncide avec les données résidentes contenues dans la cellule de mémoire associative. Ces cellules de mémoire associative sont disposées en un réseau matriciel de 'm' rangées, chacune de ces rangées étant longue de 'n' bits pour pouvoir contenir un mot de 'n' bits. Ainsi exploitée, la mémoire associative permet d'effectuer à la fois des opérations de lecture et des opérations de recherche-comparaison en un seul cycle d'horloge plutôt que les trois à quatre cycles d'horloge habituellement requis.

Claims (13)

  1. Cellule de mémoire destinée à être utilisée dans un réseau de mémoire associative comportant des premiers moyens de transistor (TC) pour bloquer un signal de bit établi (BIT) et son signal de bit réinitialisé de complément (BITB),
    des seconds moyens de transistor (C1, C2) pour comparer un bit de signal de recherche d'entrée et son complément, respectivement, avec ledit signal de bit établi et ledit signal de bit réinitialisé,
    des moyens de ligne de lecture (102), lorsqu'activés, pour permettre auxdits premiers moyens de transistor pendant une opération d'Ecriture d'insérer ledit signal de bit établi et ledit signal de bit réinitialisé,
    des premiers moyens d'accès (122) pour insérer ledit signal de bit établi (BIT) et ledit signal de bit réinitialisé (BITB) dans lesdits premiers moyens de transistor (TC) ou appliquer ledit bit de signal de recherche auxdits seconds moyens de transistor (C1, C2), et
    des moyens de ligne de correspondance (104) pour émettre un signal de correspondance lorsque ledit bit de signal de recherche correspond au signal de bit établi résidant dans lesdits premiers moyens de transistor,
       caractérisée par des seconds moyens d'accès (126) pour émettre ledit signal de bit établi provenant desdits premiers moyens de transistor (TC) pendant une opération de Lecture, lesdits seconds moyens d'accès (126) étant séparés desdits premiers moyens d'accès (122).
  2. Cellule de mémoire selon la revendication 1, dans laquelle des signaux situés sur lesdits premiers moyens d'accès (122) et lesdits seconds moyens d'accès (126) peuvent agir concurremment dans un cycle d'horloge.
  3. Cellule de mémoire selon la revendication 2, dans laquelle ledit bit de signal de recherche d'entrée peut rechercher une correspondance avec le bit de signal résidant dans ladite cellule de mémoire (100) et émettre aussi, pendant ledit un cycle d'horloge, un signal de présence lorsqu'une correspondance survient.
  4. Cellule de mémoire selon la revendication 1, dans laquelle lesdits premiers moyens d'accès (122) peuvent agir pour écrire dans un signal de bit établi dans lesdits premiers moyens de transistor.
  5. Cellule de mémoire selon la revendication 1, dans laquelle lesdits premiers moyens d'accès (122) peuvent introduire ledit bit de signal de recherche alors que lesdits seconds moyens d'accès (126) fournissent un bit de signal de sortie et lesdits moyens de ligne de correspondance (104) émettent un bit de signal de présence/absence concurremment pendant un seul cycle d'horloge.
  6. Mémoire selon l'une quelconque des revendications précédentes, ayant de multiples rangées de cellules de mémoire (100) destinées à contenir des bits de données et dans laquelle chaque rangée de cellules peut contenir un mot de données numériques,
       comportant de plus :
    des premiers moyens d'adressage pour adresser une rangée sélectionnée de cellules ayant une opération ECRIRE,
    des seconds moyens d'adressage pour adresser une rangée sélectionnée de cellules ayant une opération LIRE,
    des troisième moyens pour rechercher chacune desdites multiples rangées de cellules afin de trouver une correspondance entre un mot de données de recherche d'entrée et un mot résidant dans l'une des rangées de cellules, dans laquelle chacun desdits premiers et deuxièmes et troisièmes moyens exécute ses fonctions concurremment et dans un cycle d'horloge.
  7. Mémoire selon la revendication 6, dans laquelle lesdits troisièmes moyens comportent :
       des moyens (C1, C2, 104) pour engendrer un signal de coïncidence vers un circuit extérieur lorsque ledit mot de données de recherche d'entrée coïncide avec un mot de données situé dans une rangée quelconque de cellules.
  8. Mémoire selon la revendication 6, dans laquelle de plus, dans chacune desdites cellules (100) lesdits moyens de ligne d'Ecriture (102) sont agencés pour adresser une rangée sélectionnée dedites cellules pendant une opération ECRIRE,
    des moyens de ligne de lecture (107) sont agencés pour adresser une rangée sélectionnée dedites cellules pendant une opération LIRE,
    lesdits premiers moyens d'accès (122) sont agencés pour activer une recherche desdites rangées de cellules pour voir si ces données coïncident avec des données d'entrée sur lesdits premiers moyens d'accès (122), et lesdits moyens de ligne de correspondance (104) sont tout d'abord agencés pour indiquer une correspondance des données dans ladite rangée de cellules avec lesdites données d'entrée.
  9. Mémoire selon la revendication 6, dans laquelle chacune desdites cellules (100) a des lignes de mots d'adresse séparées (102, 116), pour des opérations LIRE et ECRIRE.
  10. Mémoire selon la revendication 6 ou 7, dans laquelle lesdites cellules de mémoire forment un réseau de cellules CAM (100) agencées selon "m" rangées et chaque rangée ayant "n" cellules de telle sorte que chaque rangée de "n" cellules peut contenir des bits de données formant un mot à n bits, lesdits premiers moyens d'adressage sont agencés pour sélectionner une rangée donnée de cellules CAM pendant une opération ECRIRE pour placer un mot de données d'entrée dans ladite rangée sélectionnée de cellules CAM,
    lesdits deuxièmes moyens d'adressage sont agencés pour sélectionner une rangée donnée de cellules CAM pendant une opération LIRE pour transférer vers l'extérieur le mot de données résidantes à partir de la rangée sélectionnée de cellules CAM, et
    lesdits troisièmes moyens d'adressage sont agencés pour chercher chacune desdites "m" rangées de cellules pour trouver la coïncidence (correspondance) entre un mot de données de recherche d'entrée et un mot de données résidant dans une rangée de cellules CAM.
  11. Mémoire selon la revendication 10, dans laquelle lesdits deuxièmes moyens d'accès comportent
       des premiers moyens logiques (Q1, Q2) pour valider des bits de données à extraire de chaque cellule CAM adressée pendant une opération LIRE.
  12. Mémoire selon la revendication 10, dans laquelle lesdits premiers moyens d'accès comportent
       des seconds moyens logiques pour valider l'entrée d'écriture de mots de données dans une rangée adressée de cellules CAM pendant une opération ECRIRE.
  13. Mémoire selon la revendication 12, dans laquelle lesdits seconds moyens logiques comportent des seconds moyens de transistor (C1 ,C2) pour valider un mot de données de recherche d'entrée pour comparaison avec les mots de données résidant dans lesdites "m" rangées de cellules CAM.
EP92901523A 1990-11-19 1991-11-18 Cellule de memoire associative a double acces et reseau matriciel forme par de telles cellules Expired - Lifetime EP0558654B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US615941 1984-05-31
US07/615,941 US5226005A (en) 1990-11-19 1990-11-19 Dual ported content addressable memory cell and array
PCT/US1991/008580 WO1992009086A1 (fr) 1990-11-19 1991-11-18 Cellule de memoire associative a double acces et reseau matriciel forme par de telles cellules

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EP0558654A1 EP0558654A1 (fr) 1993-09-08
EP0558654B1 true EP0558654B1 (fr) 1997-03-26

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US (1) US5226005A (fr)
EP (1) EP0558654B1 (fr)
JP (1) JP3142870B2 (fr)
DE (1) DE69125393T2 (fr)
WO (1) WO1992009086A1 (fr)

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EP0558654A1 (fr) 1993-09-08
DE69125393T2 (de) 1997-09-04
US5226005A (en) 1993-07-06
WO1992009086A1 (fr) 1992-05-29
JP3142870B2 (ja) 2001-03-07
JPH06502737A (ja) 1994-03-24

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