EP0549168A2 - Transistor fabrication method - Google Patents

Transistor fabrication method Download PDF

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Publication number
EP0549168A2
EP0549168A2 EP92311092A EP92311092A EP0549168A2 EP 0549168 A2 EP0549168 A2 EP 0549168A2 EP 92311092 A EP92311092 A EP 92311092A EP 92311092 A EP92311092 A EP 92311092A EP 0549168 A2 EP0549168 A2 EP 0549168A2
Authority
EP
European Patent Office
Prior art keywords
silicide
layer
refractory metal
metal silicide
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92311092A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0549168A3 (enrdf_load_stackoverflow
Inventor
Kuo-Hua Lee
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0549168A2 publication Critical patent/EP0549168A2/en
Publication of EP0549168A3 publication Critical patent/EP0549168A3/xx
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/034—Diffusion of boron or silicon

Definitions

  • This invention relates to methods for semiconductor integrated circuit fabrication.
  • CMOS integrated circuits utilize n+ gate material for both PMOS and NMOS devices.
  • CMOS integrated circuits utilize n+ gate material for both PMOS and NMOS devices.
  • P+ gate PMOS transistors i.e., surface channel devices
  • P+ NMOS gate transistors have also been found satisfactory in various CMOS applications.
  • p+ gates are formed by depositing a polysilicon layer which is doped.
  • the polysilicon is typically doped with boron or BF2.
  • the dopant species boron
  • the polysilicon is doped by ion implantation with boron, the dopant species (boron) may penetrate through the polysilicon (a phenomenon termed "channeling") into the substrate and cause changes in the threshold voltage.
  • the polysilicon is doped with BF2 (a larger species) channeling is less likely to occur.
  • the presence of fluorine in the polysilicon seems to enhance boron diffusion through the gate oxide into the substrate during subsequent thermal treatments. Thus, the threshold voltage is again adversely affected.
  • N+ gates are typically formed from polysilicon doped with phosphorous. Since phosphorous atoms are bigger than boron atoms, channeling is a less serious problem for devices with n+ gates (assuming that the same thickness of polysilicon is employed).
  • Some manufacturers of comparatively thin n+ gates cover the polysilicon with tungsten silicide and then with a silicon dioxide layer.
  • the silicon dioxide layer is formed at a temperature high enough to cause crystallization of the tungsten silicide.
  • the gate is implanted with an n type dopant such as phosphorous.
  • applicants' invention includes: forming a polysilicon layer overlying a substrate; forming an amorphous refractory metal silicide layer over the polysilicon layer; directing a p-type dopant species at the refractory metal silicide; performing an anneal at a temperature high enough to cause a substantial amount of the p species to move to the polysilicon layer.
  • Another embodiment includes forming a dielectric over the amorphous refractory metal silicide.
  • the dielectric is formed at a temperature low enough to prevent significant crystallization of the amorphous refractory metal silicide.
  • the Figure is a cross-sectional view which schematically aids in understanding an illustrative embodiment of the present invention.
  • reference numeral 11 denotes a substrate which may, typically, be silicon, epitaxial silicon, or doped silicon.
  • substrate refers to a body having a surface upon which other materials may be formed.
  • Reference numeral 13 denotes an oxide layer which, typically, may be 100 ⁇ thick. However, other thicknesses may also be used.
  • Reference numeral 15 denotes an undoped polysilicon layer having a thickness of approximately 1000 ⁇ , although other thicknesses (typically between 300 ⁇ and 3000 ⁇ ) may also be employed.
  • tungsten silicide layer 17 Formed upon polysilicon layer 15 is tungsten silicide layer 17. Other silicides such as tantalum silicide, or cobalt silicide, may also be used.
  • Layer 17 is desirably formed by sputtering at a temperature between room temperature and approximately 400°C. The sputtering process produces a comparatively amorphous layer which does not exhibit grain boundaries which might promote channeling of later-implanted dopants.
  • the thickness of layer 17 is 1000 - 1200 ⁇ , although other thicknesses may also be employed. (Generally, a range of 300 - 3000 ⁇ is acceptable.)
  • Layer 19 is formed upon layer 17.
  • Layer 19 may be any dielectric formed at a sufficiently low temperature to prevent crystallization of silicide layer 17.
  • layer 19 may be an oxide formed by the plasma-enhanced deposition of TEOS (PETEOS) or, layer 19 may be a nitride layer formed by plasma-enhanced chemical vapor deposition (PECVD nitride).
  • PETEOS plasma-enhanced deposition
  • PECVD nitride plasma-enhanced chemical vapor deposition
  • Layer 19 may also be a low temperature oxide (LTO) or a spin-on-glass (SOG).
  • LTO low temperature oxide
  • SOG spin-on-glass
  • the deposition temperature of 720°C for layer 19 is generally too high because it promotes granularization of silicide 17. In general, deposition temperatures of less than approximately 600°C are believed suitable. Typically, the thickness of layer 19 may be 1200 ⁇ . (Generally, a range of 300 - 2000 ⁇ is acceptable.) Furthermore, the low deposition temperature helps to prevent bubbling or flaking of silicide 17.
  • Reference numeral 23 denotes an implantation species which may be, typically, elemental boron or BF2.
  • An exemplary elemental boron implantation may be performed at 40 KEV and 5E15 dosage for a 1200 ⁇ PETEOS layer 19. Other thicknesses or materials may require different energies.
  • 50 KEV, 5E15 may be used directly into an amorphous silicide layer 17 (without an overlying dielectric 19-- or else with approximately 200 ⁇ of dielectric 19). Both boron and BF2 produce equally acceptable transistors in terms of current drive, threshold voltage control, and threshold voltage thermal stability.
  • an annealing step typically 30 minutes at approximately 900°C, is performed.
  • the annealing step drives boron dopant from silicide 17 into polysilicon layer 15.
  • concentration of boron between 5E19 and 7E19 in both layer 17 and layer 15.
  • Subsequent processing such as gate patterning may commence at this point.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
EP92311092A 1991-12-23 1992-12-04 Transistor fabrication method Withdrawn EP0549168A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US814981 1985-12-31
US07/814,981 US5278096A (en) 1991-12-23 1991-12-23 Transistor fabrication method

Publications (2)

Publication Number Publication Date
EP0549168A2 true EP0549168A2 (en) 1993-06-30
EP0549168A3 EP0549168A3 (enrdf_load_stackoverflow) 1994-04-13

Family

ID=25216528

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92311092A Withdrawn EP0549168A2 (en) 1991-12-23 1992-12-04 Transistor fabrication method

Country Status (3)

Country Link
US (1) US5278096A (enrdf_load_stackoverflow)
EP (1) EP0549168A2 (enrdf_load_stackoverflow)
JP (1) JPH05251376A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0643417A3 (en) * 1993-09-08 1995-10-04 At & T Corp Method for installing the door.
DE19626386A1 (de) * 1995-06-30 1997-01-02 Hyundai Electronics Ind Verfahren zur Herstellung eines Halbleiterelements

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2847031B2 (ja) * 1993-05-03 1999-01-13 現代電子産業株式会社 半導体素子の配線製造方法
KR0135166B1 (ko) * 1993-07-20 1998-04-25 문정환 반도체장치의 게이트 형성방법
US5395799A (en) * 1993-10-04 1995-03-07 At&T Corp. Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide
US5536684A (en) * 1994-06-30 1996-07-16 Intel Corporation Process for formation of epitaxial cobalt silicide and shallow junction of silicon
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method
US5614428A (en) * 1995-10-23 1997-03-25 Lsi Logic Corporation Process and structure for reduction of channeling during implantation of source and drain regions in formation of MOS integrated circuit structures
JP3770954B2 (ja) * 1995-11-13 2006-04-26 エイ・ティ・アンド・ティ・コーポレーション 装置の製造方法
US5665611A (en) * 1996-01-31 1997-09-09 Micron Technology, Inc. Method of forming a thin film transistor using fluorine passivation
TW396646B (en) 1997-09-11 2000-07-01 Lg Semicon Co Ltd Manufacturing method of semiconductor devices
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
US6174807B1 (en) * 1999-03-02 2001-01-16 Lucent Technologies, Inc. Method of controlling gate dopant penetration and diffusion in a semiconductor device
DE10021871A1 (de) * 2000-05-05 2001-11-15 Infineon Technologies Ag Verfahren zum Herstellen einer Barriereschicht in einem elektronischen Bauelement und Verfahren zum Herstellen eines elektronischen Bauelements mit einer Barriereschicht
US6867087B2 (en) 2001-11-19 2005-03-15 Infineon Technologies Ag Formation of dual work function gate electrode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782033A (en) * 1985-11-27 1988-11-01 Siemens Aktiengesellschaft Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate
KR930004295B1 (ko) * 1988-12-24 1993-05-22 삼성전자 주식회사 Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법
US5089432A (en) * 1990-08-17 1992-02-18 Taiwan Semiconductor Manufacturing Company Polycide gate MOSFET process for integrated circuits
US5130266A (en) * 1990-08-28 1992-07-14 United Microelectronics Corporation Polycide gate MOSFET process for integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0643417A3 (en) * 1993-09-08 1995-10-04 At & T Corp Method for installing the door.
DE19626386A1 (de) * 1995-06-30 1997-01-02 Hyundai Electronics Ind Verfahren zur Herstellung eines Halbleiterelements

Also Published As

Publication number Publication date
US5278096A (en) 1994-01-11
JPH05251376A (ja) 1993-09-28
EP0549168A3 (enrdf_load_stackoverflow) 1994-04-13

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