EP0518714B1 - An kurzzeitige Ausgangspannungschwankungen angepasste Stromquelle - Google Patents

An kurzzeitige Ausgangspannungschwankungen angepasste Stromquelle Download PDF

Info

Publication number
EP0518714B1
EP0518714B1 EP92401404A EP92401404A EP0518714B1 EP 0518714 B1 EP0518714 B1 EP 0518714B1 EP 92401404 A EP92401404 A EP 92401404A EP 92401404 A EP92401404 A EP 92401404A EP 0518714 B1 EP0518714 B1 EP 0518714B1
Authority
EP
European Patent Office
Prior art keywords
current
transistor
current source
resistor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92401404A
Other languages
English (en)
French (fr)
Other versions
EP0518714A1 (de
Inventor
Gilles Masson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne e2v Semiconductors SAS
Original Assignee
Thomson SCF Semiconducteurs Specifiques
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson SCF Semiconducteurs Specifiques filed Critical Thomson SCF Semiconducteurs Specifiques
Publication of EP0518714A1 publication Critical patent/EP0518714A1/de
Application granted granted Critical
Publication of EP0518714B1 publication Critical patent/EP0518714B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only

Definitions

  • the present invention relates to a current source which supports rapid variations in voltage on its output without passing them on to the current output. This source owes this characteristic partly to its structure and partly to its production in NPN type transistors.
  • a current source is by definition a circuit which must supply a stable current to another electronic circuit. But in fact, during operation, it happens that this second circuit, by changes of states, undergoes rapid variations in current, which are reflected on the output of the current source.
  • the current source has a low impedance, it can supply the necessary current, but due to the low impedance there is a reaction which destabilizes the output current. If, on the contrary, the current source is at high impedance, it is more stable but cannot respond to rapid variations.
  • FIG. 1 The diagram of a current source according to the known art is given in FIG. 1. It is very simple and includes a current mirror formed by the transistors Q1 and Q2 and by the current source Q3: this is controlled at starting from a reference voltage which is established at the terminals of a resistor Rref, and temperature controlled by the standard V BG and by the transistor Q ref The transistor Q4 is mounted in mirror with the transistor Q3.
  • This architecture has the advantage of being very simple, of requiring only a few transistors and of having a low consumption. It is improved in that the current mirror Q1 + Q2, in NPN transistors, which ensures the amplification makes it possible to overcome variations in current gain in transistor Q3, which is a PNP.
  • PNP transistors In fact, in fast bipolar technology, PNP transistors generally have more dispersion. gain than NPN transistors.
  • PNP transistors such as Q3 and Q4 have much lower dynamic performance than NPN transistors such as Q1 and Q2, because the stray capacitances of a PNP are greater than those of an NPN. Under these conditions, a rapid variation of the output current I S (or of the voltage V S at output) is not transmitted instantaneously on the basis of PNP Q3, because of its parasitic collector base capacity, and Q3 does not react. fast enough to correct this variation.
  • the invention relates to a current source adapted to rapid variations in voltage on its output, comprising as the cone of EP-A-0 219 682 on the one hand a branch generating the output current formed by a first transistor in series with a first resistor and on the other hand a reference branch formed by a reference voltage source in series with a second resistor and with a second transistor, the bases of the first and second transitors being joined together and biased across a resistor connected to a power supply, a third and a fourth transistor being mounted as a differential amplifier, the current source according to the invention being characterized in that, in order to keep constant the potential difference across the first resistance, the third transistor has its collector connected to the positive power supply and its base connected to the output of the current source, while the e fourth transistor has its collector connected to the common point "high” at the bases of the first and second transistors and to its base connected to the common point "low” between the second resistor and said reference voltage source, the collectors of the first and second transistors being connected to positive power.
  • FIG. 2 gives the electrical diagram of the source, of current according to the invention.
  • the branch which supplies a reference current I ref is substantially the same as that of FIG. 1: a transistor Q ref and a resistor R ref , controlled by temperature by a voltage source V BG , control the current flowing through a transistor Q6, in series with a resistor R6 located between the emitter of Q6 and the collector of Q ref .
  • the branch which constitutes the current source proper comprises a transistor Q5, connected to the + V DC power supply , in series with a resistor R5, the free end of which constitutes the output terminal of the circuit.
  • the bases of the transistors Q5 and Q6 are joined together, and polarized from V CC by a resistor R8.
  • the basis of the invention is to maintain a constant potential difference across the resistor R5, which ensures a constant flow current I S whatever the output potential V S.
  • This is obtained by means of a differential amplifier, formed by the transistors Q7 and Q8.
  • the transistor Q7 has its base joined at the low point V S , free end of the resistance R5 and its collector connected to the power supply.
  • the transistor Q8 has its base joined at the low point V B of the resistor R6, and its collector joined at the point V H common to the resistor R8 and at the bases of the transistors Q5 and Q6.
  • the transmitters of the differential amplifier Q7 + Q8 are connected to a bias source, which draws a current I pol towards the supply -V EE .
  • the reference current source Q ref + R ref ensures a constant potential difference V H - V B across the resistor R6 (at a junction close), and, at equilibrium, the voltage at point V B is controlled by the output voltage at point V S , or voltage at the "low" point of R5.
  • the curves of FIGS. 3 to 5 illustrate the advantage of the NPN transistors, and of the circuit according to the invention, compared with the known art.
  • the curve of figure 3 represents the form of tension which one forces on the exit V S : it varies from 2 V in 1 ns, that is to say a variation of 2000 V / ⁇ S, better known under the name of "slew-rate"
  • the current source reacts in the two cases of variation, rising edge and falling edge.
  • the quasi-straight line 1 gives the reaction of the reference current I ref , amplified to be brought to the level of the output current I S.
  • the current I ref is very constant, but the output current in curve 2 undergoes two rebounds, better known under the name of "overshoot", one on the rising edge, the other on the falling edge.
  • the overshoot reaches 115%, and it takes 4.8 ns for the circuit to return to equilibrium + 5%.
  • Curves 3 and 4 in FIG. 5 give the correspondents of the preceding curves, but for the current source according to the invention.
  • the reference current curve 3
  • the output current curve 4
  • the overshoot is limited to 9% and the disturbance lasts only 1.5 ns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Claims (3)

  1. An kurze Schwankungen der Spannung (VS) an ihrem Ausgang angepaßte Stromquelle mit einerseits einem Zweig zum Erzeugen des Ausgangsstroms (IS) aus einem ersten, in Serie mit einem ersten Widerstand (R5) geschalteten Transistor (Q5) und andererseits einem von einer Referenzspannungsquelle (Qerf+Rerf+VBG) in Serie mit einem zweiten Widerstand (R6) und einem zweiten Transistor (Q6) gebildeten Zweig, wobei die Basisanschlüsse des ersten und des zweiten Transistors (Q5, Q6) verbunden und über einen Widerstand (R8) an eine Versorgungsspannung (+VCC) gelegt sind, wobei ein dritter und ein vierter Transistor (Q7, Q8) als Differenzverstärker geschaltet sind, wobei die Stromquelle dadurch gekennzeichnet ist, daß zum Konstanthalten der Potentialdifferenz an den Klemmen des ersten Widerstandes (R5) der dritte Transistor (Q7) mit seinem Kollektoranschluß an die positive Versorgungsspannung (+VCC) und mit seinem Basisanschluß an den Ausgang (VS) der Stromquelle angeschlossen ist, während der vierte Transistor (Q8) mit seinem Kollektoranschluß an dem gemeinsamen "hohen" Punkt (VH) mit den Basisanschlüssen des ersten und zweiten Transistors (Q5, Q6) und mit seinem Basisanschluß an den gemeinsamen "niedrigen" Punkt (VB) zwischen dem ersten Widerstand (R6) und der Referenzspannungsquelle (Qerf) angeschlossen ist, wobei die Kollektoranschlüsse des ersten und des zweiten Transistors mit der positiven Versorgungsspannung verbunden sind.
  2. Stromquelle nach Anspruch 1, dadurch gekennzeichnet, daß die Transistoren NPN-Transistoren sind.
  3. Stromquelle nach Anspruch 1, dadurch gekennzeichnet, daß die Änderungen der Ausgangsspannung (VS) durch die Differenzverstärker (Q7, Q8) am gemeinsamen "niedrigen" Punkt (VB) des Referenzzweigs sowie am gemeinsamen "hohen" Punkt (VH) nachgebildet werden, wobei die Potentialdifferenz an den Klemmen des ersten Widerstandes (R5) konstant gehalten wird.
EP92401404A 1991-06-14 1992-05-22 An kurzzeitige Ausgangspannungschwankungen angepasste Stromquelle Expired - Lifetime EP0518714B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9107320 1991-06-14
FR9107320A FR2677781B1 (fr) 1991-06-14 1991-06-14 Source de courant adaptee a des variations rapides de tension de sortie.

Publications (2)

Publication Number Publication Date
EP0518714A1 EP0518714A1 (de) 1992-12-16
EP0518714B1 true EP0518714B1 (de) 1996-06-26

Family

ID=9413872

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92401404A Expired - Lifetime EP0518714B1 (de) 1991-06-14 1992-05-22 An kurzzeitige Ausgangspannungschwankungen angepasste Stromquelle

Country Status (4)

Country Link
US (1) US5391981A (de)
EP (1) EP0518714B1 (de)
DE (1) DE69211779T2 (de)
FR (1) FR2677781B1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3125821B2 (ja) * 1992-05-08 2001-01-22 ソニー株式会社 電源供給回路
JPH07202593A (ja) * 1993-12-29 1995-08-04 Matsushita Electric Ind Co Ltd 電圧電流変換回路
US5483151A (en) * 1994-09-27 1996-01-09 Mitsubishi Denki Kabushiki Kaisha Variable current source for variably controlling an output current in accordance with a control voltage
WO1996010865A1 (en) * 1994-10-03 1996-04-11 Motorola Inc. Method and apparatus for providing a low voltage level shift
KR100735440B1 (ko) * 1998-02-13 2007-10-24 로무 가부시키가이샤 반도체장치 및 자기디스크장치
IT1302276B1 (it) * 1998-09-25 2000-09-05 St Microelectronics Srl Circuito a specchio di corrente con recupero, ad elevata impedenza diuscita
US7265620B2 (en) * 2005-07-06 2007-09-04 Pericom Semiconductor Corp. Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads
FR2917557A1 (fr) 2007-06-15 2008-12-19 Commissariat Energie Atomique Dispositif de demodulation d'un signal comportant des informations transitant par modulation de la phase d'une porteuse
US9547324B2 (en) * 2014-04-03 2017-01-17 Qualcomm Incorporated Power-efficient, low-noise, and process/voltage/temperature (PVT)—insensitive regulator for a voltage-controlled oscillator (VCO)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319179A (en) * 1980-08-25 1982-03-09 Motorola, Inc. Voltage regulator circuitry having low quiescent current drain and high line voltage withstanding capability
US4578633A (en) * 1983-08-31 1986-03-25 Kabushiki Kaisha Toshiba Constant current source circuit
US4628248A (en) * 1985-07-31 1986-12-09 Motorola, Inc. NPN bandgap voltage generator
US4642551A (en) * 1985-10-22 1987-02-10 Motorola, Inc. Current to voltage converter circuit
JPH065493B2 (ja) * 1986-02-25 1994-01-19 株式会社東芝 定電流供給回路
US4879524A (en) * 1988-08-22 1989-11-07 Texas Instruments Incorporated Constant current drive circuit with reduced transient recovery time
US5049807A (en) * 1991-01-03 1991-09-17 Bell Communications Research, Inc. All-NPN-transistor voltage regulator

Also Published As

Publication number Publication date
FR2677781B1 (fr) 1993-08-20
DE69211779T2 (de) 1996-11-28
DE69211779D1 (de) 1996-08-01
US5391981A (en) 1995-02-21
FR2677781A1 (fr) 1992-12-18
EP0518714A1 (de) 1992-12-16

Similar Documents

Publication Publication Date Title
EP0518714B1 (de) An kurzzeitige Ausgangspannungschwankungen angepasste Stromquelle
EP0680140B1 (de) Differenzverstärker mit Gleichtaktregelung
FR2566146A1 (fr) Circuit de reference de tension de bande interdite perfectionne
EP0619647B1 (de) Verstärkerarchitektur und Anwendung zu einem Bandabstandsspannungsgenerator
EP0052040B1 (de) CMOS-integrierter AB-Verstärker
FR2561471A1 (fr) Circuit de commande de commutation d'un transistor de puissance
EP0649079B1 (de) Geregelter Spannungsquellengenerator der Bandgapbauart
EP0675422A1 (de) Regelschaltung zur Erzeugung einer temperatur- und versorgungsspannungsunabhängigen Referenzspannung
EP1647091B1 (de) Spannungsverstärker mit niedrigem verbrauch
EP0524294B1 (de) Verstärkerschaltung mit exponentieller verstärkungssteuerung
EP0564341A1 (de) Videoverstärker mit Verstärkungs- und Ausrichtsteuerung
FR2688905A1 (fr) Circuit miroir de courant a commutation acceleree.
EP0292071B1 (de) Stromspiegel mit hoher Ausgangsspannung
FR2579045A1 (fr) Transducteur optoelectronique
FR2881850A1 (fr) Circuit de generation d'une tension de reference flottante, en technologie cmos
EP0533230B1 (de) Differenzverstärker, Oszillator und Mischer
WO1994005079A1 (fr) Etage amplificateur a faible distorsion thermique
FR2634604A1 (de)
EP0353808B1 (de) Stromausgleichsschaltung
EP0242304B1 (de) Folgeverstärker mit grosser Anstiegsgeschwindigkeit
EP0111980B1 (de) Verfahren und Anordnung zur Schwarzpegelregelung eines Videofrequenzsignals
FR2519211A1 (fr) Etage de sortie pour circuit integre a reseau de portes de la technique ecl regule vis-a-vis des variations liees aux temperatures de fonctionnement
EP0479377B1 (de) Stromquelle mit bestimmtem Verhältnis zwischen Eingangs- und Ausgangsströmen
FR2681961A1 (fr) Generateur de courant precis.
FR2483705A1 (fr) Etage amplificateur symetrique a transistors

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE GB IT NL

17P Request for examination filed

Effective date: 19930113

17Q First examination report despatched

Effective date: 19940719

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE GB IT NL

ITF It: translation for a ep patent filed

Owner name: JACOBACCI & PERANI S.P.A.

REF Corresponds to:

Ref document number: 69211779

Country of ref document: DE

Date of ref document: 19960801

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19960905

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19970416

Year of fee payment: 6

Ref country code: GB

Payment date: 19970416

Year of fee payment: 6

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19970417

Year of fee payment: 6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980522

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19981201

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19980522

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19981201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990302

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050522