EP0518039B1 - Dispositif électronique de traitement d'entrées/sorties ayant un contrÔle de la tension d'alimentation - Google Patents

Dispositif électronique de traitement d'entrées/sorties ayant un contrÔle de la tension d'alimentation Download PDF

Info

Publication number
EP0518039B1
EP0518039B1 EP92107188A EP92107188A EP0518039B1 EP 0518039 B1 EP0518039 B1 EP 0518039B1 EP 92107188 A EP92107188 A EP 92107188A EP 92107188 A EP92107188 A EP 92107188A EP 0518039 B1 EP0518039 B1 EP 0518039B1
Authority
EP
European Patent Office
Prior art keywords
data
output
voltage
input
output device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92107188A
Other languages
German (de)
English (en)
Other versions
EP0518039A1 (fr
Inventor
Michinori Shinkai
Katsuhiko Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP0518039A1 publication Critical patent/EP0518039A1/fr
Application granted granted Critical
Publication of EP0518039B1 publication Critical patent/EP0518039B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

Definitions

  • the present invention relates to an electronic apparatus, and particularly to an electronic apparatus for data input/output processing to a predetermined input/output device.
  • Generally known electronic apparatuses such as personal computers, word processors and the like include electronic apparatuses which receive data from and transmit data to external printers and other electronic apparatuses.
  • Such electronic apparatuses having the input/output function include various types of apparatuses such as desk-top computers, lap-top computers, hand held computers and the like.
  • Lap-top computers and hand held types of apparatuses are frequently driven by a battery or supplied with electricity using DC electric power, such as an AC adapter, externally attached or the like, because importance is attached to portability.
  • the above-described electronic apparatus have a printer interface or a communication interface such as RS232C, or the like, which is provided on the outside thereof, not in the apparatus body, in order to decrease the size and weight of the body or decrease the cost.
  • the interface is frequently supplied with electricity from the body side, like the case in which an interface is contained in the apparatus.
  • This is designed for decreasing the size and weight of a communication interface of the like or decreasing the cost.
  • a central processing unit, CPU and a memory which constitute a control section of the electronic apparatus cannot be normally operated until a stable supply voltage of at least a predetermined value is supplied thereto.
  • the above-described conventional apparatus can become inoperative during communication due to a combination of a drop in the supply voltage caused by the operation of the body and a voltage drop caused by the operation of the communication interface externally attached to the body. In this case, there is also the danger of destroying important user data stored in the memory.
  • An interface such as RS232C, a centronics port, or the like generally conducts a relatively large driving current and thus there is a higher probability that the above problems will be produced than that in the case where the body only is driven.
  • Prior art document US-A-4 984 185 shows a portable computer having a battery voltage detecting circuit. It appears to be known from this reference to detect the amount of power delivered by the battery and to decide upon a further supply of data in accordance with the detection result. This is done during the battery's driving of a load. In particular, in column 3, line 53, to column 4, line 2, it is outlined that a printer operation may be automatically prohibited when the battery power is insufficient.
  • Patent publication US-A-4 907 183 shows a battery powered computer system wherein a energy state of the power supply battery is determined by a voltage detector. Depending on the detection result the power consumption of the computer is decreased by shutting off any high power consumption peripherals.
  • Prior art document WO-A-90/13079 shows a computing system with selective operating voltages. According to this document, it is checked by means of a self-test routine which the minimum operating voltage is necessary for the operation of the microcomputer. This is done by a stepwise decrease of the operating voltage as long as the microcomputer works and, after having detected the level at which the microcomputer does not longer work, by an addiion of a certain amount of power to this "non-working" voltage level to thereby define the minimum operating voltage of the microcomputer.
  • the invention as defined in independent claim 1, which achieves these objectives relates to an electronic apparatus comprising means for inputting and/or outputting data to or from a predetermined input and/or output device, detection means for detecting the minimum main supply voltage needed for the apparatus during data input and/or output to or from the input and/or output device, and control means for comparing the minimum main supply voltage detected by the detection means during the inputting and/or outputting of data to or from the input and/or output device with a predetermined reference voltage so that data input and/or output processing of the inputting and/or outputting means is restricted when the minimum main supply voltage is lower than the reference voltage.
  • the detection means detects the minimum main supply voltage during the inputting and/or outputting of test data into or out of the predetermined input and/or output device.
  • Fig. 1 shows the configuration of a control section common to electronic apparatuses such as a personal computer, a word processor and the like, all of which employ the present invention.
  • reference numeral 101 denotes a control system contained in the apparatus body and having a central processing unit, CPU, 11 comprising a microprocessor, and a read only memory, ROM, 12 and a random access memory, RAM, 13 both of which are connected to the CPU 11 by an address bus and a data bus.
  • CPU central processing unit
  • ROM read only memory
  • RAM random access memory
  • the RAM 13 is used as a work area for the CPU 11 for storing user data.
  • the ROM 12 is used for storing the control program of the CPU 11 described below.
  • An input/output control section 21 is connected to the CPU 11.
  • the input/output control section 21 comprises a control circuit for controlling input/output to an external circuit 104 comprising a centronics interface or parallel port 42 and an RS232C interface 41, which are contained in the apparatus body or are externally attached thereto.
  • the power of the apparatus is supplied from a power source 32 of a power source section 103.
  • the power source 32 comprises, for example, a battery or the like, for supplying power to the control section 101 of the body and for supplying power to the external circuit 104 comprising the external interfaces 41, 42 when the external circuit 104 is connected thereto.
  • the CPU 11 has an internal timer so that an interrupt routine is executed at predetermined time intervals on the basis of the timer control.
  • detection processing is performed at predetermined intervals according to a timer interrupt procedure.
  • test data (which can be specific data, actual data, or calibration data) is output before actual data input and output so that a supply voltage during input and output of data to the external circuit 104 is detected for making a decision as to whether or not communication processing can be performed.
  • Fig. 2 shows the control of input/output to the external circuit 104.
  • Fig. 3 shows the interrupt routine which is executed according to a timer interrupt procedure at predetermined intervals (for example, several seconds to ten-odd seconds). These programs are stored as control programs for the CPU 11 in the ROM 12.
  • Steps S31 to S34 show the process of reading the output voltage of the power source 32 through the A/D converter 31.
  • the A/D converter 31 has a plurality of A/D channels.
  • Step S31 the channel to which the power source 32 is assigned by the CPU 11 is specified by the CPU 11.
  • Steps S32 and S33 the output voltage of the power source 32 is read through the A/D converter 31 when no signal is transmitted from the section 21 to the external circuit 104.
  • the A/D converter outputs digitized data representing the output voltage of the power source 32. This digitized data is transmitted to the input/output control section 21, and the CPU 11 stores the digitized data in the work area of the RAM 13 in Step S34.
  • Step S35 a decision is made by the CPU 11 as to whether or not a flag ND, indicating whether or not the test data is presently output, is set.
  • the flag ND is set during the output of the test data to the external circuit 104. If the flag ND is set, the digitized data representing minimum supply voltage of the power source 32 during the time the flag is set is stored in a specific region of the work area in Step S36.
  • Data representing the minimum value is stored by comparing the value read in Step S34 with data representing a value stored in an area of the RAM 13, of one or more bytes, for the minimum voltage of the power source 32 during the output of the test data to the external circuit 104 read through the A/D converter 31. If the newly-read value of the voltage of the power source 32 read during the output of the test data is smaller than the previously stored value in Step S34, the newly-read value is stored, and if the stored value in Step S34 is smaller than the read value read during the output of test data, the area of the RAM 13 in which the previously-stored value in Step S34 is stored is left as it was without being rewritten. In an initialization step, the data representing maximum value output from the A/D converter is previously stored in this area.
  • Step S11 shown in Fig. 2 a key input using a key board (not shown) is detected by the CPU 11. This is because input and output to the external circuit 104 are generally started by input from the key board. If a key input is detected in Steps S12, S13, a decision is made by the CPU 11 as to whether or not input/output to the RS232C interface 41 or the parallel port 42 is directed by key input. If a key input is not detected in Step S11, the procedure returns to Step S11 to again determine whether a key input is detected.
  • Step S14 When it is decided by the CPU 11 in Step S12 that the RS232C interface 41 is selected, predetermined operations for specifying a communication speed, a parity/stop bit, and so on, are performed in Steps S14 to S16.
  • Step S14 When a key input is present in Step S14 and when communication start is directed in Step S15, the dummy operation of outputting the test data to the RS232C interface 41 is performed in Steps S17 to S111 before actual data is actually output in Step S112. During the dummy operation, the process of deciding the minimum supply voltage stored according to the procedure shown in Fig. 3 is performed. If a key input is not present at Step S14, the procedure returns to Step S14 to again determine if a key input is present, If a communication start is not directed in Step S15, the procedure goes to Step S16 to perform other processing operations.
  • Step S17 the test data output flag ND is set, and in Step S18, the dummy test data is output to the RS232C interface 41 through the input/output control section 21.
  • data of about 100 bytes is output to the RS232C interface 41.
  • the test data preferably has no effect on the RS232C interface 41 or an external apparatus connected therethrough.
  • NULL ( ⁇ ) data is preferable. It is also thought that it is preferable to output a data pattern which increases, to the maximum value, the current consumed by an external circuit, such as the RS232C interface 41 or the like.
  • Step S19 a decision is made by the CPU 11 as to whether or not the test data is completely transmitted. If the output is completed, the flag ND is reset in Step S110. If not, the procedure returns to Step S17.
  • Step S111 data representing the minimum supply voltage during output of the test data, which is stored in the work area of the RAM 13 according to the procedure shown in Fig. 3, is compared with data representing a predetermined reference voltage.
  • the reference voltage is the supply voltage value which enables the satisfactory operation of each of the necessary sections of the apparatus.
  • Step S111 If it is decided by the CPU 11 in Step S111 that the minimum supply voltage stored in the predetermined area of the RAM 13 is greater than the reference voltage, actual data is output to the RS232C interface in Step S112.
  • Step S113 data output is inhibited, and the warning shown in Fig. 4 is displayed on a display or the like.
  • Fig. 4 shows the message displayed on the display D shown in Fig. 1 in Step S113. The message states that the current capacity is insufficient for communication.
  • the minimum supply voltage during the test data output to the external circuit 104 is detected and compared with the predetermined reference voltage so that actual communication is simulated, and a decision is made by measuring the supply voltage during the communication as to whether or not the apparatus can be operated. It is thus possible to prevent the occurrence of the accident that the apparatus becomes inoperative, with the consequent destruction of data.
  • the minimum supply voltage is measured by outputting dummy test data, and a protocol is used for transmitting the header potion before the substantial data portion is transmitted during the output of actual data.
  • the minimum supply voltage may be measured by, for example, transmitting the header portion, not by outputting the dummy data.
  • the invention thus can provide an excellent electronic apparatus which is capable of restricting data input/output processing in response to a voltage drop during data input/output and which is capable of preventing the apparatus from becoming inoperative due to the voltage drop during data input/output and thus preventing the occurrence of the accident that data is destroyed.
  • the apparatus includes an analog-to-digital converter for measuring the voltage output from a power source and for inputting the voltage to a central processing unit and a control section so that during output of test data to a parallel port before substantial data is output, the voltage output from the power source is measured, and a value for the minimum voltage of the power source is stored.
  • the minimum supply voltage during the output of the test data is lower than a reference voltage, actual data output is inhibited, thereby preventing the apparatus from becoming inoperative during data output.
  • the minimum voltage output from the power source can be intermittently detected by a timer interrupt procedure.
  • the minimum main supply voltage is compared with the predetermined reference voltage during data input/output so that a voltage drop is detected during data input/output, and data input/output processing is restricted according to the results of detection.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Power Sources (AREA)

Claims (4)

  1. Appareil électronique de traitement de données numériques comprenant :
    des moyens de détection (31) pour détecter la tension d'une source d'alimentation électrique (32) alimentant ledit appareil électronique ;
    une zone de stockage (13) pour stocker une information représentant la valeur d'une tension d'alimentation minimale ;
    des moyens de sortie de données (102) pour fournir en sortie des données à un dispositif d'entrée et/ou de sortie prédéterminé (104) ; et
    des moyens de commande (11) pour restreindre la fourniture de données au dispositif d'entrée et/ou de sortie prédéterminé (104) lorsque la valeur stockée dans ladite zone de stockage (13) est inférieure à une valeur prédéterminée représentant une tension de référence prédéterminée qui est la valeur de la tension d'alimentation permettant le fonctionnement satisfaisant de chacune des sections nécessaires dudit appareil électronique ;
       caractérisé en ce que
    lesdits moyens de sortie de données (102) fournissent en sortie des données de test particulières audit dispositif d'entrée et/ou de sortie prédéterminé (104) avant que des données réelles soient fournies en sortie audit dispositif d'entrée et/ou de sortie prédéterminé (104) ; et
    en ce que lesdits moyens de détection (31) détectent et choisissent la tension d'alimentation minimale qui doit être stockée en tant que ladite information dans ladite zone de stockage (13) pendant que lesdites données de test particulières sont fournies en sortie audit dispositif d'entrée et/ou de sortie prédéterminé (104).
  2. Appareil électronique selon la revendication 1, caractérisé par des moyens de commande d'affichage (D) pour afficher un message lorsqu'il est déterminé que la tension détectée par lesdits moyens de détection (31) est inférieure à la tension prédéterminée.
  3. Procédé de transfert de données dans un appareil électronique de traitement de données numériques comprenant les étapes qui consistent :
    à envoyer (S112) des données à un dispositif d'entrée et/ou de sortie (104) ;
    à stocker (S34) une information représentant la valeur de la tension d'alimentation minimale ;
    à détecter (S36) une valeur de tension fournie par une source d'alimentation (32) alimentant ledit appareil électronique ; et
    restreindre (S113) la transmission des données au dispositif d'entrée et/ou de sortie (104) lorsqu'il est déterminé que la tension détectée par ladite étape de détection (S36) est inférieure à une tension prédéterminée représentant une tension de référence prédéterminée qui est la valeur de la tension d'alimentation permettant un fonctionnement satisfaisant de chacune des sections nécessaires dudit appareil électronique ;
       caractérisé en ce que
    avant d'envoyer (S112) lesdites données audit dispositif d'entrée et/ou de sortie (104), des données de test particulières sont envoyées (S18) audit dispositif d'entrée et/ou de sortie (104) ; et
    en ce que ladite valeur de tension fournie par ladite source (32) d'alimentation électrique est détectée et choisie lors de ladite étape de détection pendant le fonctionnement dudit dispositif d'entrée et/ou de sortie (104) pendant l'envoi (S18) desdites données de test particulières au dispositif d'entrée et/ou de sortie (104).
  4. Procédé de transfert de données selon la revendication 3, caractérisé par l'étape supplémentaire consistant à afficher un message (D) lorsqu'il est déterminé que la tension détectée lors de ladite étape de détection (S36) est inférieure à la tension prédéterminée.
EP92107188A 1991-06-10 1992-04-28 Dispositif électronique de traitement d'entrées/sorties ayant un contrÔle de la tension d'alimentation Expired - Lifetime EP0518039B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP137321/91 1991-06-10
JP3137321A JP2788680B2 (ja) 1991-06-10 1991-06-10 電子機器及びそのデータ入出力制御方法

Publications (2)

Publication Number Publication Date
EP0518039A1 EP0518039A1 (fr) 1992-12-16
EP0518039B1 true EP0518039B1 (fr) 1999-01-20

Family

ID=15195951

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92107188A Expired - Lifetime EP0518039B1 (fr) 1991-06-10 1992-04-28 Dispositif électronique de traitement d'entrées/sorties ayant un contrÔle de la tension d'alimentation

Country Status (4)

Country Link
US (1) US5386575A (fr)
EP (1) EP0518039B1 (fr)
JP (1) JP2788680B2 (fr)
DE (1) DE69228208T2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2135963C (fr) * 1993-11-17 1999-05-11 Kaoru Endo Appareil electronique a piks
JPH07200525A (ja) * 1993-12-28 1995-08-04 Mitsubishi Electric Corp マイクロコンピュータ、マイクロコンピュータ応用機器及びicカード
JPH11288319A (ja) 1998-01-28 1999-10-19 Seiko Instruments Inc 電子機器
JP4231572B2 (ja) * 1998-07-07 2009-03-04 沖電気工業株式会社 電圧監視回路及びそれを内蔵したメモリカード
CN100343786C (zh) * 2000-12-26 2007-10-17 神基科技股份有限公司 电源监控保护方法
US7123033B1 (en) * 2004-09-20 2006-10-17 Cypress Semiconductor Corporation Method and an apparatus to detect low voltage
US8111577B2 (en) 2007-04-17 2012-02-07 Cypress Semiconductor Corporation System comprising a state-monitoring memory element
CN103164302A (zh) * 2011-12-16 2013-06-19 鸿富锦精密工业(深圳)有限公司 电子装置错误检测系统及方法
CN103926455A (zh) * 2013-01-10 2014-07-16 中兴通讯股份有限公司 一种识别直流输入电压瞬变速度的方法及装置
US9589672B2 (en) * 2014-09-30 2017-03-07 Apple Inc. Power-aware memory self-test unit

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162122A (en) * 1980-05-16 1981-12-12 Canon Inc Electronic apparatus equipped with printing device
US4553081A (en) * 1982-06-07 1985-11-12 Norand Corporation Portable battery powered system
EP0096531B1 (fr) * 1982-06-09 1987-09-16 Fujitsu Limited Dispositif semi-conducteur monopuce incorporant un circuit avec mode de remise à zéro détectant un potentiel d'alimentation
JPS5955526A (ja) * 1982-09-24 1984-03-30 Sharp Corp インタ−フエ−ス回路
JPS59133603A (ja) * 1983-01-20 1984-08-01 Omron Tateisi Electronics Co プログラマブルコントロ−ラ
US4707795A (en) * 1983-03-14 1987-11-17 Alber Engineering, Inc. Battery testing and monitoring system
US4766567A (en) * 1984-04-19 1988-08-23 Ltd. Nippondenso Co. One-chip data processing device including low voltage detector
JPS62146227U (fr) * 1986-03-03 1987-09-16
JPS62239221A (ja) * 1986-04-10 1987-10-20 Toshiba Corp ワ−ドプロセツサ
JPS6375877U (fr) * 1986-11-07 1988-05-20
JPS63236113A (ja) * 1987-03-25 1988-10-03 Toshiba Corp バツテリ駆動携帯用機器
JPH01188918A (ja) * 1988-01-22 1989-07-28 Oki Electric Ind Co Ltd 携帯型データ機器端末装置のバッテリ残量管理方法
US5218705A (en) * 1989-04-17 1993-06-08 Motorola, Inc. Pager receiver with selective operating voltage and reduced power consumption
US5086501A (en) * 1989-04-17 1992-02-04 Motorola, Inc. Computing system with selective operating voltage and bus speed
US5130659A (en) * 1990-08-21 1992-07-14 Sloan Jeffrey M Battery Monitor

Also Published As

Publication number Publication date
DE69228208D1 (de) 1999-03-04
EP0518039A1 (fr) 1992-12-16
DE69228208T2 (de) 1999-08-05
JPH04361316A (ja) 1992-12-14
US5386575A (en) 1995-01-31
JP2788680B2 (ja) 1998-08-20

Similar Documents

Publication Publication Date Title
EP0518039B1 (fr) Dispositif électronique de traitement d'entrées/sorties ayant un contrÔle de la tension d'alimentation
US6501249B1 (en) Battery management system
US5475271A (en) Power source control system for electronic device and expansion unit connected thereto
EP2808755B1 (fr) Procédé et appareil de gestion d'un état de charge dans un dispositif électronique mobile
KR19990001497A (ko) 화면 출력 상태 제어기능을 갖는 컴퓨터 시스템 및 그 제어방법
KR880008120A (ko) 마이크로콤퓨터를 내장한 콤퓨터시스템용 전원공급장치
US6522104B1 (en) Method and apparatus for measurement of charge in a battery
US7039150B1 (en) Serial interface for a battery management system
EP1542180B1 (fr) Système de traitement de données électroniques
JP2745669B2 (ja) プリンタ
US5432938A (en) Method and system for controlling resume process in computer unit capable of connecting expansion unit
US4849919A (en) System wake up circuit for computer
NO175120B (no) Systemlederanordning for databehandlingssystem
US5564110A (en) Printer interface apparatus with plug-in unit authorized for reception of data upon type verification
JP3190564B2 (ja) 電池電源を備えた電子機器
US5720560A (en) Printing apparatus
JPH0736574A (ja) 電子機器の初期化装置及び方法
JP2849584B2 (ja) 電子機器の電源制御方法
JPH0259958A (ja) 文書処理装置
WO2001028064A2 (fr) Systeme de gestion de batterie
JP2579690B2 (ja) 電子機器
JPS6215618A (ja) 携帯型デ−タエントリ−端末装置
JP2816232B2 (ja) 文書編集印刷装置
JPH10187291A (ja) 情報処理装置
JPS59178699A (ja) デ−タ処理装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19930428

17Q First examination report despatched

Effective date: 19970410

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

ITF It: translation for a ep patent filed
ET Fr: translation filed
REF Corresponds to:

Ref document number: 69228208

Country of ref document: DE

Date of ref document: 19990304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19990421

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050408

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050421

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20050427

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060428

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20060430

Year of fee payment: 15

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060428

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20061230

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060502

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070428