Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
  • H01J9/02—Manufacture of electrodes or electrode systems
  • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
  • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
  • H01J1/02—Main electrodes
  • H01J1/30—Cold cathodes, e.g. field-emissive cathode
  • H01J1/304—Field-emissive cathodes
  • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2201/00—Electrodes common to discharge tubes
  • H01J2201/30—Cold cathodes
  • H01J2201/319—Circuit elements associated with the emitters by direct integration

Definitions

• This invention relates generally to cold-cathode field-emission devices and more particularly to cold- cathode field-emission devices formed on surfaces other than the surface of a supporting substrate layer.
• Cold-cathode field-emission devices are known in the art. Such cold-cathode field-emission devices employ emitter electrodes with geometric discontinuities of small radius of curvature for the purpose of emitting electrons.
• FEDs are formed by a number of preferred methods.
• One such method taught by the prior art results in an emitter electrode disposed on the surface of a supporting substrate material, while an alternative method employs selective semiconductor processing to form the emitter electrode directly from the supporting substrate material.
• a number of impediments to optimum utilization of FEDs can be associated with these and other prior art methods.
• One such impediment is that control or limitation of emission is not easily implemented within the FED structure.
• mono-crystal silicon transistor devices are generally restricted to formation in the substrate material in a structure in which FEDs are also located. Therefore, a need exists for an FED formation methodology that can easily incorporate an emitter current limitation mechanism and provide for the formation of single-crystal silicon transistors at locations other than in the substrate material.
• a field emission device comprises a substrate, an insulator layer disposed on at least a part of a surface of the substrate, a layer of single-crystal silicon disposed on at least a part of a surface of the insulator layer, and an emitter disposed on at least a part of a surface of the layer of single crystal silicon.
• the emitter electrode(s) is(are) disposed on a surface of a layer of single-crystal silicon.
• the gate electrode(s) is(are) formed by selective impurity doping of a layer of single-crystal silicon.
• a conductive gate material is disposed on a surface of a layer of single- crystal silicon.
• a layer of single-crystal silicon is selectively patterned to limit the FED emission.
• a layer of single-crystal silicon is selectively doped with impurities.
• a transistor device(s) is(are) formed in a(the) layer(s) of single-crystal silicon.
• Figs. 1A-L comprise a series of side elevational depictions of structures resulting from steps tnat yield a first embodiment of the invention
• Figs. 2A-G comprise a series of side elevational depictions of structures resulting from steps that yield a second embodiment of the invention
• Figs. 3A-D comprise a series of side elevational depictions of structures resulting from steps that yield a third embodiment of the invention
• Figs 4A-B comprise a series of side elevational depictions of structures resulting from steps that yield a fourth embodiment of the invention
• Figs. 5A-D comprise a series of side elevational depictions of structures resulting from steps that yield a fifth embodiment of the invention
• Fig. 6 comprises a side elevational depiction of a structure which forms a sixth embodiment of the invention.
• Figs. 7A-D comprise a series of side elevational depictions of structures resulting from a second method of forming a layer of single-crystal silicon
• Figs. 8A-B comprise a series of side elevational depictions of structures resulting from a third method of forming a layer of single-crystal silicon
• Figs. 9A-E comprise a series of side elevational depictions of structures resulting from steps that yield a seventh embodiment of the invention
• Fig. 10 comprises a side elevational view depicting an eighth embodiment of the invention
• Fig. 11 comprises a side elevational view depicting a tenth embodiment of the invention.
• Fig. 12 comprises a side elevational view depicting a tenth embodiment of the invention
• Fig. 13 comprises a side elevational view depicting an eleventh embodiment of the invention
• Fig. 14 comprises a side elevational view depicting a twelfth embodiment of the invention
• Fig. 15 is a top plan view depicting a plurality of field emission devices employing a preferentially doped layer of single-crystal silicon;
• Fig. 16 is a top plan view of a plurality of field emission devices employing a plurality of selectively doped layers of single-crystal silicon;
• Fig. 17 is a side elevational view depicting a first embodiment of a plurality of field emission devices.
• Fig. 18 is a side elevational view depicting a second embodiment of a plurality of field emission devices.
• Fig. 1A depicts a substrate (101) which forms the support base on which a field emission device will be formed.
• An insulator layer (102) is thermally grown or deposited onto the surface of the substrate (101) (Fig. 1 B). This is followed by deposition of a mask layer (102) (Fig. 1 C).
• the mask layer (103) is selectively exposed, developed, and patterned to provide openings which expose a surface of the underlying insulator layer (102) (Fig. 1 D).
• An insulator etch is performed to selectively remove insulator material from the insulator layer (102) at the areas of the insulator layer (102) exposed by the patterning of the mask layer (103) to the extent that a part of a surface of the underlying substrate (101) will become exposed (Fig. 1 E). This is followed by removal of the mask layer (103) (Fig. 1 F).
• the structure so formed is placed in an environment which readily precipitates silicon preferentially onto the exposed substrate (101 ) and continues to precipitate silicon preferentially so as to build-up a layer of single-crystal silicon (104) (Fig. 1G).
• Such an environment typically contains, in part, silane or di-silane gas.
• the layer of single-crystal silicon is typically grown in this manner to a thickness on the order of 1 ⁇ m.
• an insulator layer (105) is disposed onto a surface of the layer of single-crystal silicon (104) by either thermal oxidation or deposition of a suitable insulator material (Fig. 1 H).
• insulator layer (106) is next deposited onto the surface of the insulator layer (105) (Fig. 11) and subsequently exposed, developed, and patterned (Fig. 1J). Patterning of the mask layer (106) selectively exposes surface area of the underlying insulator layer (105). An etch step is performed to remove insulator layer (105) material to the extent that a surface of the underlying layer of single-crystal silicon (104) is selectively partially exposed (Fig. 1 K). Subsequently, an emitter (107) is formed on the exposed surface of the layer of single-crystal silicon (104) using methods commonly known in the art (Fig. 1 L).
• the layer of single-crystal silicon (104) may be completely electrically isolated from the substrate (101 ) by performing a selective localized etch or selective localized oxidation of the layer of single-crystal silicon (104) at the regions where the layer of single-crystal silicon (104) passes through the intervening insulator layer (102).
• Figs. 2A-G depict a series of steps for realizing a second embodiment of an FED.
• a substrate (201) is shown.
• An implantation of ions (204) into the substrate (201 ) with energy sufficient to result in an insulator layer (202) located beneath the surface of the substrate (201 ) is performed (Fig. 2B).
• This implantation results in a layer of single-crystal silicon (203) disposed on a surface of the insulator layer (202) and electrically isolated from the substrate (201).
• the implantation process results in lattice damage to the layer of single-crystal silicon (203) which is repaired by annealing the layer of single-crystal silicon (203) to yield a reduced defect density in the layer of single- crystal silicon (203) (Fig. 2C).
• the FED is formed as depicted in Figs. 2D-G and as described previously with reference to Figs. 1 H-L.
• the layer of single-crystal silicon (203) in this embodiment, is effectively completely isolated from the substrate (201) without the need for selective localized etch or selective localized oxidation.
• a third embodiment of the invention is realized by repeating the steps described above with respect to Figs. 1A-H.
• the realization continues with the deposition of a gate electrode (306) onto a surface of the insulator layer (105) (Fig. 3A).
• a masking layer (307) onto a surface of a gate electrode (306) (Fig. 3B).
• the mask layer (307) is then exposed, developed, and patterned and an etch step is performed to remove gate electrode (306) material and insulator layer (105) material to selectively expose a part of a surface of the underlying layer of single-crystal silicon (104) (Fig. 3C).
• an emitter (308) is formed on the exposed surface of the layer of single-crystal silicon (104) using methods commonly known in the art (Fig. 3D).
• a fourth embodiment of the invention is realized by first repeating the steps described above with respect to Figs. 2A-D. This is followed by deposition of a gate electrode (406) onto a surface of the insulator layer (205) (Fig. 4A). The realization of the device continues as described above with reference to Figs. 3C and 3D to yield a resultant device as depicted in Fig. 4B having an emitter (308) disposed on the layer of single-crystal silicon (203).
• a fifth embodiment is realized as an FED having more than one layer of single-crystal silicon.
• the realization first proceeds as described above with reference to Figs. 1A-K.
• the structure is then placed in an environment wherein silicon will preferentially precipitate onto the selectively exposed surface of the underlying layer of single-crystal silicon (507) (Fig. 5A).
• a mask layer (508) is deposited onto a surface of the layer of single-crystal silicon (507) (Fig. 5B).
• Subsequent exposing, developing, and patterning of the mask layer (508), etching of the selectively exposed layer of single-crystal silicon (507), and etching of the selectively exposed insulator layer (105) will selectively expose a surface of the layer of single- crystal silicon (104) (Fig.
• each of the layers of single-crystal silicon may be formed by selectively etching an insulator layer to expose the underlying material on which the insulator layer is disposed. By so doing, a structure of successive insulator layers and layers of single-crystal silicon may be formed on a substrate.
• a sixth embodiment of the invention is realized by first repeating the steps described above for Figs. 2A-C. The realization then continues as described above with reference to Figs. 1 H-J and Figs. 5A-D.
• the second layer of single-crystal silicon (507) (Fig. 6) may be effectively electrically isolated from the first layer of single-crystal silicon (203) by performing a selective localized etch or selective localized oxidation of the second layer of single-crystal silicon (507) at the locations where the second layer of single crystal silicon (507) extends through the insulator layer (105).
• Fig. 7A depicts a seventh embodiment of the invention realized with a substrate (701) on which is deposited an insulator layer (702) which has been selectively grown, selectively deposited, or etched to preferentially expose a part of a surface of the underlying substrate (701).
• the structure is placed in an environment wherein silicon preferentially precipitates onto the partially exposed surface of the substrate (701 ) to form a single-crystal silicon protrusion (703) which extends into the plane of the insulator layer (702) and at least partially occupies the volume coincident with the insulator layer (702) where the insulator layer (702) has been selectively etched or selectively not grown or not deposited (Fig. 7B).
• a layer of silicon (704) is deposited onto a surface of the insulator layer (702) and onto a surface of the single-crystal silicon protrusion (703) (Fig. 7C). This is followed by recrystallization of the silicon layer (703) to yield a layer of single-crystal silicon (705) (Fig. 7D).
• the recrystallization of the silicon layer (703) to form the single-crystal silicon layer (705) may be accomplished by any of the methods commonly known in the art included thermal annealing, and laser recrystallization, the purpose of which is to increase crystal grain size and re-orient the lattice of the silicon layer (703) to correspond to that of the lattice of the underlying layer of single-crystal silicon (705).
• Fig. 8A depicts an eighth embodiment of the invention wherein a layer of silicon (803) has been deposited onto a surface of an insulator (802) and onto the preferentially exposed parts of a surface of a substrate (801). A subsequent recrystallization yields a structure with a layer of single-crystal silicon (804) (Fig.
• FIGs. 9A-E depict a series of steps to realize a ninth embodiment of the invention.
• the structure of Fig. 9A formed by any of the methods described above, has diffused in the layer of single-crystal silicon (903) a bipolar transistor (904).
• An insulator layer (905) is deposited onto a surface of the layer of single-crystal silicon (903) and effectively covering the bipolar transistor (904).
• Fig. 9B A mask layer (906) is then deposited onto a surface of the insulator layer (905) (Fig. 9C).
• Fig. 10 depicts a tenth embodiment of the invention which employs a field-effect transistor (1001 ) which resides at least partially within a layer of single- crystal silicon (1002).
• the device so constructed provides for incorporating a field-effect transistor device (1001) formed in a layer of single-crystal silicon (1002), which layer of single-crystal silicon (1002) is not the substrate and which field-effect transistor device (1001) resides in close proximity to and as part of the same structure as the FED.
• Fig. 11 depicts an eleventh embodiment of the invention employing a bipolar transistor device (1101 ) formed in a layer of single-crystal silicon (1103) and having an FED gate electrode (1102) disposed on the layer of single-crystal silicon (1103) and operably coupled to the collector of the bipolar transistor device (1101 ).
• Fig. 12 depicts a twelfth embodiment of the invention employing a field-effect transistor device (1201 ) formed in a layer of single-crystal silicon (1203) and having an FED gate electrode (1202) disposed on the layer of single-crystal silicon 91103) and operably coupled to the drain of the field-effect transistor device (1201 ).
• Fig. 13 depicts a thirteenth embodiment of the invention employing a bipolar transistor device (1302) disposed in a layer of single-crystal silicon (1301 ), which layer of single-crystal silicon (1301 ) has been doped with impurities.
• the layer of single-crystal silicon (1301), so formed, functions as both the collector of the bipolar transistor device (1302) and as the FED gate electrode.
• Fig. 14 depicts a fourteenth embodiment of the invention employing a field-effect transistor device (1401) disposed in a layer of single-crystal silicon
• the layer of single-crystal silicon (1402) functions as both the drain of the field-effect transistor device (1401) and as the FED gate electrode.
• Fig. 15 is a partial top plan depiction of an embodiment of a device (1500) employing a plurality of FEDs which have been selectively electrically interconnected.
• the apertures (1503), in which the emitters (1505) are formed are substantially peripherally individually surrounded by selectively, geometrically shaped gate electrodes (1504).
• the emitters (1505) are electrically connected to selectively doped resistive regions (1506), which selectively doped resistive regions (1506) are disposed in a layer of single-crystal silicon (1501) and operably coupled to a selectively doped high-conductive stripe (1502), which selectively doped high-conductive stripe is also disposed in a layer of single-crystal silicon (1501). So constructed, the device (1500) functions with independently controlled electron emission at each of the emitters (1505).
• Fig. 16 is a top plan depiction which illustrates a means of selectively electrically interconnecting the various electrodes of a multiplicity of FEDs of a device (1600) to obtain row and column addressing capability.
• the emitters (1603) are selectively operably connected to a selectively doped high- conductive stripe (1602) in a columnar manner such that the emitters (1603) are electrically isolated from emitters (1603) not in the same column.
• the selectively geometrically patterned gate electrodes (1604) are electrically operably connected to high-conductive stripes (1601 ), which high-conductive stripes (1601 ) may be formed as a deposition of conductive or semiconductor material, or as a selectively doped region of a layer of single-crystal silicon.
• the device (1600) provides for a means of exercising row and column addressing of individual FEDs of the plurality of FEDs in the device (1600).
• Fig. 17 depicts, in side cross-sectional elevational pictorial form, a selectively operably interconnected plurality of FEDs employing selectively doped resistive regions (1706).
• the columns of emitters (1708) are individually operably connected and disposed on individual selectively doped resistive regions (1706), which selectively doped resistive regions (1706) are disposed in a layer of single-crystal silicon (1707).
• the selectively doped resistive regions (1706) are operably connected to selectively doped high- conductive stripes (1705), which selectively doped high- conductive stripes (1705) are also disposed in a layer of single-crystal silicon (1707).
• a plurality of FEDs constructed in accordance with this embodiment will have provided a means for independent columnar control of same column emitters (1708) and independent limitation of electron emission from each of the plurality of emitters (1708).
• Fig. 18 is a side cross-sectional elevational view of a plurality of FEDs in accordance with an embodiment of the invention.
• the emitters (1806) are disposed on a substantially uniformly doped layer of single-crystal silicon (1804).
• the substantially uniformly doped layer of single-crystal silicon (1804) is implanted with impurities by any of the known methods of semiconductor doping to provide that the substantially uniformly doped layer of single-crystal silicon (1804) will function as a distributed resistive element to effectively limit the electron emission from each of the plurality of emitters (1806) in an independent manner. It will be immediately obvious to those skilled in the art and familiar with the known configurations of FEDs that emitters may be formed in shapes other than the depicted conical shape.
• Some other emitter shapes include wedges of varying lengths and being either straight or serpentine.
• the associated aperture will be non-circularly cylindrical and will conform substantially symmetrically to the elongated shape of the emitter.
• the methods described may be extended to provide field emission devices with more than two layers of single- crystal silicon and/or more than a single electrode in addition to the emitter. Such field emission devices will typically take the form of tetrode or pentode devices commonly known and described in the literature. What is claimed is:

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• 1991
  • 1991-09-06 EP EP19910918341 patent/EP0504370A4/en not_active Withdrawn
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