EP0482263A2 - Videospeichersystem mit einem Zwischenpuffer - Google Patents

Videospeichersystem mit einem Zwischenpuffer Download PDF

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Publication number
EP0482263A2
EP0482263A2 EP90313405A EP90313405A EP0482263A2 EP 0482263 A2 EP0482263 A2 EP 0482263A2 EP 90313405 A EP90313405 A EP 90313405A EP 90313405 A EP90313405 A EP 90313405A EP 0482263 A2 EP0482263 A2 EP 0482263A2
Authority
EP
European Patent Office
Prior art keywords
signals
memory
address
data
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90313405A
Other languages
English (en)
French (fr)
Other versions
EP0482263A3 (en
Inventor
Chien-Chih Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Acer Inc
Original Assignee
Acer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acer Inc filed Critical Acer Inc
Publication of EP0482263A2 publication Critical patent/EP0482263A2/de
Publication of EP0482263A3 publication Critical patent/EP0482263A3/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Definitions

  • the present invention relates to a computer display memory system, and more specifically, to such a system including an intermediate buffer which substantially reduces the memory accessing time of an external processing unit by eliminating the need to insert wait cycles.
  • a typical video memory system 20 for storing the data which represents the image to be displayed.
  • a typical video memory system 20 is illustrated, comprising a video memory 12, a video display control unit (VDCU) 14, and a video processing means 15.
  • the external processing unit (CPU) 10 sends data and control signals to the video memory 12 to update the information stored therein.
  • the VDCU 14 periodically causes the memory 12 to output data to the video processing means 15.
  • Video processing means 15 then converts the data into signals that the external display means 16 can recognize, and outputs these signals to the display means 16 in response to the control signals on lines 17 from VDCU 14. In this manner, the information on the display screen is periodically refreshed.
  • the video memory system 20 may either be incorporated directly into the motherboard of a host computer (not shown) or may take the form of an add-on card. Its general operation is substantially the same for either configuration.
  • both the CPU 10 and the VDCU 14 of a typical video memory system have direct access to the memory 12.
  • a method is needed to designate the time slots during which the CPU 10 and the VDCU 14 may respectively access the memory 12. Otherwise, they may try to access the memory simultaneously, an undesirable result.
  • Time allocation is commonly achieved through the use of a time slot reference signal such as that shown in Fig. 2A wherein CPU 10 may only access the memory 12 between times t1 and t3 and between times t5 and t6.
  • the time slots between t3, t5 and between t6, t7 are allocated to VDCU 14. This type of procedure inherently introduces delays into the system.
  • the CPU 10 pulls its read/write line low (not shown in Fig. 1) when it is ready to write a set of data to memory 12.
  • the read/write line is pulled low at the beginning of a CPU time slot (times t1 or t5 of Fig. 2A)
  • the write operation is performed without delay (Fig. 2B).
  • the CPU must insert wait cycles in order to properly access the memory. For example, if the CPU wishes to write to the memory during a VDCU time slot as shown in Fig.
  • the present invention eliminates the need to insert wait cycles for write operations by interposing an intermediate buffer, between the CPU and the video memory, which functions to intercept the address, data, and control signals from the CPU.
  • the buffer simply relays the intercepted address signals directly to the video memory.
  • the buffer stores the address and data sent by the CPU and retains this information within its memory until the beginning of the next CPU time slot, at which time it accesses the video memory via the stored address and writes the data thereto.
  • the invention allows the CPU to perform write operations regardless of whether the time slot is a CPU time slot, thereby, obviating the need to introduce wait cycles.
  • wait cycles may still need to be inserted for read operations, but since eighty percent of the operations performed by the CPU are write operations and only twenty percent are read operations, the present invention nonetheless saves the CPU a substantial amount of time.
  • the invention is likewise applicable to avoid wait cycles during read operations as well.
  • a preferred embodiment of the invention comprises a memory means, a VDCU connected to the memory means, a video means connected to both the memory means and the VDCU, and an intermediate buffer interposed between an external CPU and the memory means.
  • the external CPU operates to generate a read/write control signal and address and data signals.
  • the intermediate buffer intercepts these signals, and if a write operation is desired, the address and data signals are stored in the buffer.
  • the buffer monitors the time slot reference signal until it detects a CPU time slot, at which time, the address and data signals are sent to the memory means.
  • the memory means then stores the data signals at the addresses indicated by the address signals. For read operations, the intermediate buffer simply relays the address signals to the memory means.
  • Fig. 1 is a block diagram of a prior art video memory system.
  • Fig. 2A shows a typical time slot reference signal employed to designate time slots during which the CPU and the VDCU may access the video memory used in the system of Fig. 1.
  • Figs. 2B-2D show the possible time variations between the read/write signal from the CPU and the time slot reference signal in the system of Fig. 1.
  • Fig. 3 is a functional block diagram of a video memory system to illustrate the invention.
  • Fig. 4 shows a preferred embodiment of the system of Fig. 3.
  • FIG. 3 A block diagram depicting the basic components of the invention is shown in Fig. 3, comprising intermediate buffer 34, random access video memory 38, VDCU 42, and video processing means 39.
  • Video memory 38, VDCU 42, and video processing means 39 are of regular construction and are found in many typical prior art computer display systems; thus, they will not be discussed in detail herein.
  • the external CPU 30 sends data, representing a portion of the image to be displayed, to the video memory 38 where the information is stored. This continues until the entire image is stored within the video memory 38. Thereafter, the main function of CPU 30 is to update the stored image. To update a portion of the video memory 38, the CPU sends out an address on lines 31 and a read/write control signal on line 33 indicating the nature of the operation. For write operations, CPU 30 also sends out data signals on data lines 32.
  • Address lines 31, data lines 32, and control line 33 are all connected to intermediate buffer 34.
  • a time slot reference signal 52 such as that shown in Fig. 2A, dictating the times during which the CPU 30 and the VDCU 42 may access video memory 38, is also supplied to intermediate buffer 34.
  • buffer 34 Depending on the status of the read/write line 33, buffer 34 performs different functions.
  • buffer 34 receives a read address on lines 31 and a read signal on line 33.
  • the internal logic of buffer 34 reads the signal on control line 33 and, realizing that a read operation is desired, relays the read address to memory 38 via memory address lines 35.
  • the read/write control signal is relayed to memory 38 via memory control line 37.
  • Data from the addressed location in the video memory 38 is then put onto the memory data lines 36, said data travelling from the memory 38 through buffer 34 to eventually arrive at CPU 30 via CPU data lines 32.
  • the intermediate buffer 34 only acts as a relay for read operations, CPU 30 is responsible for ensuring that a read operation only takes place during a time slot which has been allocated to the CPU. Otherwise, bus conflict with the VDCU 42 may result. Thus, wait cycles may need to be inserted for read operations. However, since only about twenty percent of the CPU's operations are read operations, the delaying effect of the wait cycles is not significant.
  • the CPU 30 sends to the intermediate buffer 34 a write address on lines 31, write data on lines 32, and a write control signal on line 33.
  • the internal logic of buffer 34 receives the write control signal and responds by initiating a series of operations.
  • the internal logic first scans the memory portion of the buffer 34 to ascertain which locations may be written into. Once an appropriate location is found, the address and data signals on lines 31 and 32, respectively, are stored. Thereafter, the internal logic checks the status of the time slot reference signal 52 to ascertain whether it indicates a CPU time slot. If so, the stored address and data signals are put onto lines 35 and 36, respectively, and a write control signal is sent on line 37. This results in the data being written into the appropriate address in video memory 38.
  • the buffer 34 will wait until the beginning of the next CPU time slot to write the data to the memory 38. Since several sets of addresses and data may be stored by the buffer 34 before the next CPU time slot, the intermediate buffer 34 preferably outputs stored data in a first-in-first-out (FIFO) fashion so that no data remains within the buffer 34 for an extended period of time.
  • FIFO first-in-first-out
  • intermediate buffer 34 due to the presence of intermediate buffer 34, the CPU 30 need not generate any wait cycles. It is free to perform write operations at any time without regard to the status of the time slot reference signal 52. The waiting formerly performed by the CPU is now done by the intermediate buffer. This significantly reduces the memory access time of the CPU and allows it to run more efficiently.
  • buffer register means 60 contains a plurality of storage registers 62 with each register capable of storing a set of address and data signals.
  • Register means 60 receives as input CPU address lines 31, CPU data lines 32, read/write control line 33, and several control lines 65 from control means 70.
  • register means 60 stores within one of its registers 62 the address and data signals appearing on lines 31 and 32. This occurs irrespective of the status of the time slot reference signal 52.
  • the specific register in which the data is stored is dictated by the control signals on lines 65 sent by control means 70. The data remains stored until a WRITE DATA signal on lines 65 instructs the register means 60 to output data from one of its registers. Again, the control signals on lines 65 specify which register is to be accessed.
  • the read/write multiplexer 80 is attached to two sets of input lines, one set from register means 60 and the other set from the CPU 30. Multiplexer 80 receives from register means 60 address lines 74 and data lines 75. Multiplexer 80 also receives a write control signal on line 78 from control means 70. From the CPU 30, multiplexer 80 receives address lines 31, data lines 32, and read/write line 33. In response to a MUX control signal from control means 70 on line 68, multiplexer 80 behaves as a switch to selectively connect one of the sets of input lines to the address lines 35, data lines 36, and read/write line 37 of the video memory 38. Thus, by using line 68, control means 70 can control which device (the CPU or the register means) is connected to the video memory 38.
  • the control means 70 receives as inputs the CPU read/write control signal on line 33, buffer register status signals on lines 81, and the time slot reference signal on line 52. From these inputs signals, the internal logic of the control means 70 generates the appropriate signals to control the register means 60 and the read/write multiplexer 80. To ensure that a register 62 containing fresh data is not overwritten, control means 70 must monitor the status of the registers 62. This may be achieved through the use of a status register 66 which receives, as inputs, buffer register status signals on lines 81 from register means 60. Register 66 preferably contains as many bits 67 as there are registers 62 in the register means 60 so that each bit 67 corresponds to a specific register 62.
  • each bit may be used as a flag to indicate whether the register contains fresh data.
  • an appropriate signal is sent on lines 81 instructing control means 70 to set the flag corresponding to that register to indicate that the register is full.
  • control means 70 in response to an appropriate signal on lines 81 from register means 60.
  • Control means 70 is also equipped with sequential logic means 72 so that it may perform the FIFO function. Each time data is written into register means 60, sequential logic 72 records the location of the register as well as the sequence in which each register 62 was loaded. This allows the data to be outputted in the same sequence as it was loaded. In other words, sequential logic 72 makes it possible to perform the desired first-in-first-out function. To output data, control means 70 checks the status of the time slot reference signal 52 to determine whether the status indicates a time slot allocated for the CPU. If so, a WRITE DATA signal is issued on one of the control lines 65 instructing the register means 60 to output a set of address and data signals. Sequential logic means 72 also sends out several control signals on lines 65 controlling the sequence in which the registers 62 are selected.
  • Control means 70 then sends a MUX control signal on line 68 instructing multiplexer 80 to connect the output lines of register means 60 with the input lines of memory 38.
  • the data on lines 75 is thus written into memory 38.
  • control means 70 instructs multiplexer 80 via line 68 to connect CPU 30 with the memory 38, thereby, allowing the CPU to read data from memory 38 through multiplexer 80.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
EP19900313405 1990-10-24 1990-12-10 Video memory system with intermediate buffer Withdrawn EP0482263A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60247990A 1990-10-24 1990-10-24
US602479 1990-10-24

Publications (2)

Publication Number Publication Date
EP0482263A2 true EP0482263A2 (de) 1992-04-29
EP0482263A3 EP0482263A3 (en) 1992-08-26

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EP19900313405 Withdrawn EP0482263A3 (en) 1990-10-24 1990-12-10 Video memory system with intermediate buffer

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CA (1) CA2031625A1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613115A2 (de) * 1993-02-22 1994-08-31 Casio Computer Company Limited Steuereinrichtung zum Schreiben von Anzeigedaten
DE102008003436A1 (de) * 2008-01-07 2009-07-09 Micronas Gmbh Verfahren zur Änderung von Registerinhalten in einer Videosignalverarbeitungsschaltung und Videosignalverarbeitungsschaltung
US9879898B2 (en) 2005-05-18 2018-01-30 Whirlpool Corporation Insulated ice compartment for bottom mount refrigerator with controlled damper

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418343A (en) * 1981-02-19 1983-11-29 Honeywell Information Systems Inc. CRT Refresh memory system
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418343A (en) * 1981-02-19 1983-11-29 Honeywell Information Systems Inc. CRT Refresh memory system
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 25, no. 3B, August 1982, NEW YORK US pages 1610 - 1611; J.P. HURST: 'Simultaneous storage of two asynchronous memories for CRT refresh' *
PATENT ABSTRACTS OF JAPAN vol. 009, no. 273 (P-401)30 October 1985 & JP-A-60 117 327 ( FUJI XEROX KK ) 24 June 1985 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613115A2 (de) * 1993-02-22 1994-08-31 Casio Computer Company Limited Steuereinrichtung zum Schreiben von Anzeigedaten
EP0613115A3 (en) * 1993-02-22 1997-05-28 Casio Computer Co Ltd Display data write control device.
US9879898B2 (en) 2005-05-18 2018-01-30 Whirlpool Corporation Insulated ice compartment for bottom mount refrigerator with controlled damper
US10775092B2 (en) 2005-05-18 2020-09-15 Whirlpool Corporation Insulated ice compartment for bottom mount refrigerator with controlled damper
US11486625B2 (en) 2005-05-18 2022-11-01 Whirlpool Corporation Insulated ice compartment for bottom mount refrigerator with controlled damper
DE102008003436A1 (de) * 2008-01-07 2009-07-09 Micronas Gmbh Verfahren zur Änderung von Registerinhalten in einer Videosignalverarbeitungsschaltung und Videosignalverarbeitungsschaltung

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Publication number Publication date
CA2031625A1 (en) 1992-04-25
EP0482263A3 (en) 1992-08-26

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