EP0482263A3 - Video memory system with intermediate buffer - Google Patents

Video memory system with intermediate buffer Download PDF

Info

Publication number
EP0482263A3
EP0482263A3 EP19900313405 EP90313405A EP0482263A3 EP 0482263 A3 EP0482263 A3 EP 0482263A3 EP 19900313405 EP19900313405 EP 19900313405 EP 90313405 A EP90313405 A EP 90313405A EP 0482263 A3 EP0482263 A3 EP 0482263A3
Authority
EP
European Patent Office
Prior art keywords
memory system
video memory
intermediate buffer
buffer
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900313405
Other versions
EP0482263A2 (en
Inventor
Chien-Chih Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Acer Inc
Original Assignee
Acer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acer Inc filed Critical Acer Inc
Publication of EP0482263A2 publication Critical patent/EP0482263A2/en
Publication of EP0482263A3 publication Critical patent/EP0482263A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
EP19900313405 1990-10-24 1990-12-10 Video memory system with intermediate buffer Withdrawn EP0482263A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60247990A 1990-10-24 1990-10-24
US602479 1990-10-24

Publications (2)

Publication Number Publication Date
EP0482263A2 EP0482263A2 (en) 1992-04-29
EP0482263A3 true EP0482263A3 (en) 1992-08-26

Family

ID=24411507

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19900313405 Withdrawn EP0482263A3 (en) 1990-10-24 1990-12-10 Video memory system with intermediate buffer

Country Status (2)

Country Link
EP (1) EP0482263A3 (en)
CA (1) CA2031625A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444458A (en) * 1993-02-22 1995-08-22 Casio Computer Co., Ltd. Display data write control device
US7607312B2 (en) 2005-05-27 2009-10-27 Maytag Corporation Insulated ice compartment for bottom mount refrigerator with temperature control system
DE102008003436A1 (en) * 2008-01-07 2009-07-09 Micronas Gmbh Register's content changing method for video signal processing circuit of TV, involves reading configuration data from register in accordance with measure of selection signal, and storing read configuration data in another register

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418343A (en) * 1981-02-19 1983-11-29 Honeywell Information Systems Inc. CRT Refresh memory system
JPS60117327A (en) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd Display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418343A (en) * 1981-02-19 1983-11-29 Honeywell Information Systems Inc. CRT Refresh memory system
JPS60117327A (en) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd Display device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 25, no. 3B, August 1982, NEW YORK US pages 1610 - 1611; J.P. HURST: 'Simultaneous storage of two asynchronous memories for CRT refresh' *
PATENT ABSTRACTS OF JAPAN vol. 009, no. 273 (P-401)30 October 1985 & JP-A-60 117 327 ( FUJI XEROX KK ) 24 June 1985 *

Also Published As

Publication number Publication date
EP0482263A2 (en) 1992-04-29
CA2031625A1 (en) 1992-04-25

Similar Documents

Publication Publication Date Title
SG67911A1 (en) Television receiver with buffer memory
GB2247804B (en) Television system
EP0476993A3 (en) Video effects system
EP0438211A3 (en) Cache memory system
EP0450841A3 (en) Video control system
EP0507571A3 (en) Receiving buffer control system
EP0455016A3 (en) Buffer
ZA918300B (en) Video display system
GB2276300B (en) Video/graphics memory system
GB2267588B (en) FIFO memory system
EP0460853A3 (en) Memory system
GB2246056B (en) Video display system
EP0450602A3 (en) Video system having image combining function
GB2262177B (en) An image buffer
GB2243046B (en) Video display system
EP0447937A3 (en) Image memory
EP0482263A3 (en) Video memory system with intermediate buffer
GB2274041B (en) Buffer regulation
GB2268657B (en) Video memory
GB2257596B (en) Video playback system
GB2252100B (en) Storage system
EP0544247A3 (en) Memory architecture
EP0449618A3 (en) Video graphics systems
GB9006325D0 (en) Maintaining video signals
GB2291320B (en) Video/graphics memory system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19930227