EP0471045A1 - Multiplexeur de signaux numeriques - Google Patents

Multiplexeur de signaux numeriques

Info

Publication number
EP0471045A1
EP0471045A1 EP19910903500 EP91903500A EP0471045A1 EP 0471045 A1 EP0471045 A1 EP 0471045A1 EP 19910903500 EP19910903500 EP 19910903500 EP 91903500 A EP91903500 A EP 91903500A EP 0471045 A1 EP0471045 A1 EP 0471045A1
Authority
EP
European Patent Office
Prior art keywords
channel
data
multiplexer
controller
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910903500
Other languages
German (de)
English (en)
Inventor
Heinz Wiher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schweiz AG
Siemens AG
Original Assignee
Siemens Albis AG
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Albis AG, Siemens AG filed Critical Siemens Albis AG
Publication of EP0471045A1 publication Critical patent/EP0471045A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1641—Hierarchical systems

Definitions

  • the present invention relates to a digital signal multiplexer according to the preamble of patent claim 1.
  • Digital voice signals and data with bit rates of a middle or lower hierarchy level in particular of bit rates with 2400, 4800 and 9600 bit / s are preferably used over long distances in a time-multiplexed form at a higher hierarchy level, e.g. with bit rates of 64kbit / s or a few Mbit / s.
  • a multiplexer used for this purpose and its use in a digital data network is known from St. Bürgin, P.A. Merz "MXB.2 data multiplexer 64kbit / s of the 2nd generation according to CCITT X.50" or P.A.
  • Each MXB.2 multiplexer contains four interface modules, each of which can accommodate five individual channel interfaces and which are connected to two channel processor modules via a serial bus.
  • the flexibility of such a multiple system is severely limited.
  • the channel processor assemblies are not connected to one another via the serial bus and can only access a maximum of 4 X 5 single-channel interfaces.
  • the options for the bit rates of the single channel interfaces are limited.
  • a permissible readjustment of this multiple system to changed requirements of the user in each case requires a high level of development effort and manual access to mostly locally localized assemblies.
  • the serial bus used in the system which connects the individual channel interfaces with the channel processors, carries addresses as well as data and is consequently heavily loaded.
  • the present invention is therefore based on the object of specifying a digital signal multiplexer which can be freely configured as a function of various system constellations.
  • the configuration of several decentrally localized digital signal multiplexers should be possible from a central location and within a very short time.
  • the data traffic between data lines The same and different hierarchy levels and bit rates should be done efficiently and with little effort.
  • the digital signal multiplexer according to the invention has the following advantages: it can be configured quickly and as desired by an external control station. It also has optimal flexibility with regard to data transfer options, expandability and acceptance of any data transfer rates. It is therefore also universally applicable.
  • Fig. 1 The block diagram of a digital signal multiplexer with various internal
  • FIG. 1 shows the block diagram of a digital signal multiplexer according to the invention, which has a data bus SH with n lines, on the single-channel side two interface modules SSB-1, SSB-2 and multiple-channel side two multiplexers MXH-1, MXH-2, which access via an EPIC-Z interface is connected to a parallel DH data bus.
  • the data bus DH has high, preferably standardized data transmission rates such as 64 kbit / s, 2 Mbit / s, 8 Mbit / s etc.
  • the interface modules SSB-1, SSB-2 have ten single-channel interfaces, interfaces EKS-11, ..., EKS-25, the data with lower or medium, preferably standardized data transmission rates such as 2400, 4800, 9600 bit / s receive or send via a subscriber line.
  • Each MXH-Z multiplexer subsequently serves any number of individual channel interfaces EKS-XY located on any SSB-X interface module, which may have different data transmission rates.
  • the resulting data stream, which is fed to the multiplexer MXH-Z corresponds at most to the data transmission rate of the data bus DH.
  • the multiplexers MXH-Z and the interface modules SSB-X bitwise connect the data serially to one of the lines of the data bus SH or collect it from the latter. Such interconnection of all modules MXH-Z and SSB-X on a solid data bus SH results in maximum flexibility.
  • SSB-X interface modules located on different interface modules EKS-XY with a multiplexer MXH-Z different individual channel interfaces EKS-XY or multiplexer MXH-Z can also exchange data with one another.
  • the data transfer on the lines of the data bus SH is provided bidirectionally.
  • the digital signal multiplexer can be changed accordingly Information can be quickly adapted to the administrative units of the affected modules MXH-2, SSB-1, SSB-2.
  • FIG. 2 shows a multiplexer MXH-Z, a configuration and alarm controller KAC-Z and a cycle counter ZC, which are connected via the control bus CB to a programming and control station CTRL. It also contains a channel call memory KAR as well as a multiple channel controller VKC connected to the data bus DH via the EPIC-Z interface and a single channel controller EKC. The controllers EKC and VKC are connected to one another via a processor register memory PR controlled by the configuration and alarm controller KAC-Z. The channel call memory KAR is connected to the configuration and alarming controller KAC-Z, the single channel controller EKC, the cycle counter ZC and a demultiplexer DD and a multiplexer UM. The demultiplexer DD and the multiplexer UM are connected on the one hand to the single-channel controller EKC and on the other hand directly or via a buffer memory UR to the data bus SH.
  • the circuit shown works as follows:
  • the multi-channel controller VKC synchronizes on frames of data that arrive via the data bus DH and the interface EPIC-Z.
  • the data contained in each frame are subsequently broken down into individual channel data and stored in the processor register memory PR.
  • Single channel data which are available in the processor register memory PR for sending to the data bus DH, are taken by the multi-channel controller VKC, enclosed in a frame and output to the EPIC-Z interface.
  • a memory area is assigned to each individual channel for each transmission direction, as well as to the multiple and single channel controllers for alarm messages to the configuration and alarm controller KAC-Z.
  • a memory area for configuration data for the multiple and single channel controllers VKC, EKC is also provided in the processor register PR and in the channel call memory KAR.
  • the configuration and alarming controller KAC-Z When the system is started up or when the system is changed, via the control bus CB, which subsequently writes them into the memories PR and KAR.
  • the multiple and single-channel controllers VKC, EKC monitor the sequence of the data transfer and store any alarm messages in the processor register memory PR. These are removed by the configuration and alarm controller KAC-Z and passed on to the control station.
  • the EKC single-channel controller has individual programs that can be called up for each transmission direction, which are used for bit-by-bit single-channel data transfer and for generating and checking the frame structure on the single-channel side.
  • the configuration and alarm controller KAC-Z writes program configuration data units into the channel call memory KAR, which are cyclically cycled by the cycle counter ZC, read into the single channel controller EKC and by means of which an individual program is selected per cycle.
  • a single channel data bit is fetched from one of the lines of the data bus SH and fed to the processor register memory PR via the multiplexer UM and the single channel controller EKC, or a single channel data bit provided by the multiple channel controller VKC is removed from the processor register memory PR and One of the lines of the data bus SH is fed via the single-channel controller EKC and the demultiplexer DD.
  • an individual program in the single channel controller EKC runs at least 128,000 times per second.
  • control data belonging to the respective program configuration data units are simultaneously applied from the channel call memory KAR to the demultiplexer DD and to the multiplexer UM and the buffer memory UR, so that depending on the control data present the demultiplexer DD that Passes single channel data bit from the single channel controller EKC to the correct line of the data bus SH or that the single channel data bit is sent from the correct line of the data bus SH to the single channel controller EKC after being temporarily stored in the buffer memory UR by the multiplexer UM.
  • Individual programs can also be used to check individual modules or the entire digital signal multiplexer.
  • the interface module SSB-X shown in FIG. 3 contains a configuration and alarm controller KAC-X and a cycle counter ZC which are with a channel call memory KAR and via the control bus CB with the programming and control station CTRL.
  • the configuration and alarm controller KAC-X is also connected via a control line to all individual channel interfaces EKS-X1, ..., EKS-X5.
  • the channel call memory KAR is connected via a further control line to the individual channel interfaces EKS-X1, ..., EKS-X5 as well as to a demultiplexer UD and a multiplexer DM.
  • the demultiplexer UD and the multiplexer DM are also connected to the data bus SH and via a data line to the individual channel interfaces EKS-X1 EKS-X5.
  • the configuration and alarm controller KAC-X writes configuration data units into the channel call memory KAR, which are cyclically applied, clocked by the cycle counter, to the single-channel interfaces EKS-XY and to the multiplexers DM, UD.
  • Single-channel data bits are subsequently picked up by one of the single-channel interfaces EKS-X1, ..., EKS-X5 and taken via the demultiplexer UD to the respective line of the data bus SH or vice versa from one of the lines of the data bus SH and via the multiplexer DM to one of the individual channel interfaces EKS-X1, ..., EKS-X5.
  • the channel call memory controls the multiplexers DM and UD in such a way that the individual channel interfaces EKS-X1, ..., EKS_X5 for data transfer are each connected to the correct line of the data bus SH.
  • the control unit with which the configuration and alarm controller KAC-X is connected to all individual channel interfaces EKS-X1, ..., EKS-X5, serves to initialize these modules EKS-X1, ..., EKS-X5 , as well as for receiving status and alarm messages.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Lens Barrels (AREA)
  • Adjustment Of Camera Lenses (AREA)

Abstract

Le multiplexeur de signaux numériques présenté comporte un bus de données SH avec n lignes auxquelles accèdent, sur le côté monocanal, au moins un ensemble d'interface SSB-X, et, sur le côté multicanal, au moins un multiplexeur MXH-2. Sur l'ensemble d'interface SSB-X sont prévues plusieurs interfaces monocanal EKS-XY qui reçoivent et émettent les signaux monocanal à des débits binaires d'un échelon hiérarchique inférieur. Le mutliplexeur MXH-Z possède au moins une interface EPIC-Z qui reçoit ou émet un flux de données à un débit binaire d'un échelon hiérarchique supérieur, flux qui se compose de différents signaux monocanal. Tous les multiplexeurs MXH-Z et ensembles d'interface sont connectés par un bus de commande (CB) à une station de commande et de programmation (CTRL). Le multiplexeur de signaux numériques peut être librement configuré en fonction des différents agencements de systèmes. Plusieurs multiplexeurs de signaux numériques décentralisés peuvent être configurés en un temps minimum par la station centrale. La communication de données entre les lignes de données d'un même niveau hiérarchique, ou de différents niveaux hiérarchiques, et ayant un débit binaire identique ou différent, se fait efficacement et économiquement.
EP19910903500 1990-03-06 1991-02-08 Multiplexeur de signaux numeriques Withdrawn EP0471045A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH71390A CH679820A5 (fr) 1990-03-06 1990-03-06
CH713/90 1990-03-06

Publications (1)

Publication Number Publication Date
EP0471045A1 true EP0471045A1 (fr) 1992-02-19

Family

ID=4193428

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910903500 Withdrawn EP0471045A1 (fr) 1990-03-06 1991-02-08 Multiplexeur de signaux numeriques

Country Status (9)

Country Link
EP (1) EP0471045A1 (fr)
JP (1) JPH05500893A (fr)
AU (1) AU7227191A (fr)
BR (1) BR9104811A (fr)
CA (1) CA2054742A1 (fr)
CH (1) CH679820A5 (fr)
IE (1) IE910733A1 (fr)
PT (1) PT96935A (fr)
WO (1) WO1991014320A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991312A (en) * 1997-11-03 1999-11-23 Carrier Access Corporation Telecommunications multiplexer
DE102004015333B4 (de) * 2004-03-30 2015-09-03 Koenig & Bauer Aktiengesellschaft Einrichtung zur Überwachung verarbeitungstechnischer Vorgänge innerhalb von Druckmaschinen in Aggregatbauweise

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4697262A (en) * 1984-12-20 1987-09-29 Siemens Aktiengesellschaft Digital carrier channel bus interface module for a multiplexer having a cross-connect bus system
US4809270A (en) * 1984-12-21 1989-02-28 AT&T Information Systems Inc. American Telephone and Telegraph Company Variable time slot communication system
US4658152A (en) * 1985-12-04 1987-04-14 Bell Communications Research, Inc. Adaptive rate multiplexer-demultiplexer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9114320A1 *

Also Published As

Publication number Publication date
WO1991014320A1 (fr) 1991-09-19
AU7227191A (en) 1991-10-10
BR9104811A (pt) 1992-04-21
PT96935A (pt) 1993-04-30
IE910733A1 (en) 1991-09-11
CA2054742A1 (fr) 1991-09-07
CH679820A5 (fr) 1992-04-15
JPH05500893A (ja) 1993-02-18

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