IE910733A1

IE910733A1 - Digital signal multiplexer

Info

Publication number: IE910733A1
Application number: IE73391A
Authority: IE
Original assignee: Siemens Ag
Priority date: 1990-03-06
Filing date: 1991-03-05
Publication date: 1991-09-11
Also published as: EP0471045A1; WO1991014320A1; AU7227191A; BR9104811A; PT96935A; CA2054742A1; CH679820A5; JPH05500893A

Abstract

The digital signal multiplexer comprises a data bus SH with n lines at which there have access at the single channel-side at least one interface component group SSB-X and at the multi-channel-side at least one multiplexer MXH-Z. At the interface component groups SSB-X there are provided a plurality of single channel interfaces (EKS-XY) which receive and transmit single channel signals with bit rates of a lower hierarchial level. The multiplexer MXH-Z comprises at least one interface (EPIC-Z) which receives or transmits a data stream with a bit rate of a higher hierarchial level which is composed of different single channel signals. All of the multiplexers (MXH-Z) and interface component groups are connected by a control bus (CB) with a programming and control station (CTRL). The digital signal multiplexer is freely configurable in dependency upon different system constellations. The configuration of a plurality of de-central localized digital signal multiplexers can be accomplished from the central location and within the shortest amount of time. The data traffic between data lines of the same and different hierarchial levels and bit rates occurs efficiently and with modest expenditure.

Description

Digital signal multiplexer The present invention concerns a digital signal multiplexer according to the preamble of claim 1.

Digital speech signals and data with bit rates at a medium or low hierarchical level, especially bit rates of 2400, 4800 and 9600 bit/s, when transmitted over large distances are preferably sent in time multiplex form at a higher hierarchical level, for example at bit rates of 64 Kbit/s or several Mbit/s. A multiplexer used for this purpose and its use in a digital data network is disclosed in St. Burgin, P.A. Merz ’'MXB.2- Second Generation Data multiplexer 64 Kbit/s according to CCITT X.50 or P.A. Merz Digital data network for the transmission of 2400, 4800 and 9600 bits per second over private lines, Siemens Albis Reports 3 (1987), page 9 ff. or page 4 ff. The multiplexer MXB.2 described makes it possible to multiplex to a total bit stream of 64 Kbit/s five single channels at 9600 bit/s, ten single channels at 4800 bit/s or twenty single channels at 2400 bit/s as well as, with certain limitations, combinations thereof. The data transfer in this case takes place on the single or multiple channel side in envelopes or frames. Figure 6 on page 12 shows a multiple system with four multiplexers MXB.2 which have been connected to together to form a multiple system and each are served by two multiplexer interface and monitoring modules as well as central clock interface and monitoring modules. Each multiplexer MXB.2 contains four interface modules which can each incorporate five individual channel interface modules and which through a serial bus are each connected to two channel processor modules. The flexibility of such a multiple system is therefore considerebly restricted. The channel processor modules are not connected to each other by the serial bus and can access only a maximum of 4 X 5 single channel interfaces. The possibilities of choice for the bit rates of the single channel interfaces are limited. An acceptable readjustment of this multiple system to changed requirements of the users always presupposes high development costs and manual access to mostly local, decentralised modules. The serial bus used in the system, which connects the individual channel interfaces with the channel processors, apart from data also carries addresses and subsequently is subjected to a heavy load.

The object of the present invention therefore is to provide a digital signal multiplexer which can be of any configuration depending on the different system constellations. The configuration of several decentrally localised digital signal multiplexers should be carried out from a central point and within the shortest possible time. The data traffic between data conductors of the same or different hierarchical levels and bit rates should take place efficiently and at low cost.

This object is achieved through the measures disclosed in the characterising part of claim 1. Preferred embodiments of the invention are disclosed in the additional claims.

The digital signal multiplexer according to the invention has the following advantages: It can be structured quickly and as desired through an external control station. Furthermore, it has an optimum flexibility with regard to data transfer possibilities, expansibility and acceptance of any desired data transfer rates. Accordingly it is universally useable.

The invention is explained in more detail with the aid for example of drawings. These show: Fig. 1 The block diagram of a digital signal multiplexer with various different internal multiplexer and interface modules IE 91733 Fig. 2 An internal multiplexer module Fig. 3 An internal interface module Fig. 1 shows the block diagram of a digital signal multiplexer according to the invention which has a data bus SH with n conductors which are accessed on the single channel side by two interface modules SSB-1, SSB-2 and on the multiple channel side by two multiplexers MXH-1, MXH-2 which, through an interface EPIC-Z, are connected to a parallel data bus DH. In this case the data bus DH has high data transmission rates, preferably standardised data transmission rates such as 64 Kbit/s, 2 Mbit/s, 8 Mbit/s etc. Apart from the multiplexer MXH-1 and the interface module SSB-1, which are regarded as the minimum compliment for digital signal multiplexers, further multiplexers MXH-Z can be employed up to a maximum number which corresponds to the number of conductors n of the data bus SH (Z=n) . The interface modules SSB-1, SSB-2 have ten single channel interfaces EKS-11,...., EKS-25, which send or receive data via a subscriber line at low or medium, preferably standard data transmission rates such as 1400, 4800, 9600 bits per second. Each multiplexer MXH-Z serves as a rule any desired number of single channel interfaces EKS-XY, localised on desired interface modules SSB-X, which may have different data transmission rates. However, the resulting data stream, which is fed to the multiplexer MXH-Z, at maximum corresponds to the data transmission rate of the data bus DH.

The data is applied serially in bit form to one of the conductors of the data bus SH or taken from it by the multiplexers MXH-Z and the interface modules SSB-X. Connecting together all the modules MXH-Z and SSB-X into a drawn-out data bus SH results in maximum flexibility. Thus, apart from single channel interfaces EKS-XY localised on various different interface modules SSB-X, with a IE 91733 multiplexer MXH-Z it is also possible for different single channel interfaces EKS-XY or multiplexers MXH-Z to exchange data between each other. For increasing the efficiency of the system, the data transfer in the conductors of the data bus SH takes place bidirectionally. The complete process for the resolution and the creation of the frame structures for the data received or to be sent, as well as the correct timing of the application to and removal from the conductors of the data buses SH is communicated via a preferably parallel control bus CB to a management unit contained in each module MXH-Z, SSB-X, depending upon the particular configuration of the module. This has the advantage that after changes in the configuration of the digital signal multiplexer modules, the digital signal multiplexer can be adjusted to the new situations from a central point almost without delay. For example, if the single channel interfaces EKS-13 and EKS-25 transfer data at the same transmission rate to the multiplexer MXH-2 , and the operation of the first EKS-13 is terminated and the transmission rate of the second EKS-25 is doubled, the digital signal multiplexer through corresponding information can be quickly adjusted to the management units of the particular modules MXH-2, SSB-1, SSB-2.

Fig. 2 shows a multiplexer MXH-Z which has a configuration and alarm controller KAC-Z and a cycle counter ZC which are connected via the control bus CB to a programming and control station CTRL. It also contains a channel call memory KAR, a single channel controller EKC as well as a multiple channel controller VKC connected via the interface EPIC-Z to the data bus DH. The controller EKC and VKC in this case are connected together through a processor register memory PR controlled by the configuration and alarm control KAC-Z. The channel call memory KAR is connected to the configuration and alarm controller KAC-Z, the channel controller EKC, the cycle counter ZC as well to as a demultiplexer DD and a multiplexer UM. The IE 91733 demultiplexer DD as well as the multiplexer UM on the one hand are connected to the single channel controller EKC and on the other hand are connected either directly to the data bus SH or via a buffer memory UR.

The circuit shown functions as follows: The multiple channel controller VKC synchronises frames of data which arrive via the data bus and the interface EPICZ. The data contained in each frame is subsequently split into single channel data and deposited in the processor register memory PR. Single channel data, which is available in the processor register memory PR for sending to the data bus DH is accessed by the multiple channel controller VKC, locked into a frame and passed onto the interface EPIC-Z. In the process register memory PR each single channel is allocated a memory area per transfer direction and the multiple and single channel controller are each allocated a memory area for alarm messages to the configuration and alarm controllers KAC-Z. Furthermore provided in the processor register PR as well as in the channel call memory KAR is a memory area for configuration data for the multiple and the single channel controller VKC, EKC. This configuration data is supplied to the configuration and alarm controller KAC-Z during the start-up or during changes in the system via the control bus CB which subsequently writes them into the memories PR and KAR. The multiple and the single channel controller VKC, EKC monitor the data transfer operation and deposit any alarm messages in the processor register-memory PR. These are accessed by the configuration and alarm controller KAC-Z and passed on to the control station. The single channel controller EKC for each transfer direction has access to single programs which serve to transfer single channel data bit by bit as well as to generate and test the frame structure on the single channel side. The configuration and alarm controller KAC-Z writes program IE 91733 configuration data units into the channel call memory KAR which, timed by the cycle counter ZC, are cyclically read into the single channel controller EKC and by means of which a single program is selected per cycle. Through a single program a single channel data bit is taken from one of the conductors of the data bus SH and supplied to the single channel controller EKC and the processor register memory PR via the multiplexer UM, or a single channel data bit, prepared by the multiple channel controller VKC, is taken from the process register-memory PR and supplied via the single channel controller EKC and the demultiplexer DD to one of the conductors of the data bus SH. For a data transmission rate of 64 Kbit/s per transfer direction a single program accordingly operates at least 128000 times per second in the single channel controller EKC. In order for the transfer of a single channel data bit carried out with the selected single program to operate correctly, control data belonging to the respective program configuration data units from the channel call memory KAR are simultaneously applied to the demultiplexer DD as well as to the multiplexer UM and the buffer memory UR so that, depending on the control data applied, the demultiplexer DD transfers the single channel data bit from the single channel controller EKC to the correct conductor of the data bus SH or that the single channel data bit from the correct conductor of the data bus SH is delivered by the multiplexer UM to the single channel controller EKC after intermediate storage in the buffer memory UR. Single programs can furthermore serve to check individual modules or the entire digital signal multiplexer.

The interface module SSB-X shown in Fig. 3 contains a configuration and alarm controller KAC-X and a cycle counter ZC which are connected to a channel call memory KAR and to the programming and control station CTRL via the control bus CB. The configuration and alarm controller KACX is furthermore connected via a control wire to all the IE 91733 single channel interfaces EKS-X1,...,EKS-X5. The channel call memory KAR through a further control wire is connected to the single channel interfaces EKS-X1,...,EKS-X5 as well as to a demultiplexer UD and a multiplexer DM. The demultiplexer UD and the multiplexer DM are furthermore connected to the data bus SH and to the single channel interfaces EKS-X1,...,EKS-X5 via a data wire respectively.

The configuration and alarm controller KAC-X writes configuration data units into the channel call memory KAR which are cyclically applied, timed by the cycle counter, to the single channel interfaces EKS-XY and to the multiplexers DM, UD. Single channel data bits as a rule are taken from one of the single channel interfaces EKSXI,...,EKS-X5 and through the demultiplexer UD transferred to the respective conductor of the data bus SH or conversely, taken from one of the conductors of the data bus SH and via the multiplexer DM transferred to one of the single channel interfaces EKS-X1,...,EKS-X5. The channel call memory controls the multiplexers DM and UD in such a way that the single channel interfaces EKS-X1,...,EKS-X5 for the data transfer are each connected to the correct conductor of the data bus SH. The control wire, by which the configuration and alarm controller KAC-X is connected to all single channel interfaces EKS-X1,...,EKS-X5, serves to initialise these modules EKS-X1,...,EKS-X5, and for receiving status and alarm signals So as to ensure the synchronous cooperation between multiplexer MXH-Z and the interface modules SSB-X, their cycle counters ZC are started together. This ensures that the data bits are introduced into or taken from the conductors of the data buses SH at the correct time and thus without colliding.

Claims

1. Programmable, flexible digital signal multiplexer with at least one single channel interface (EKS-XY) on the subscriber side for exchanging single channel signals with bit rates of a lower hierarchical level and with at least one interface (EPIC-Z) which receives or delivers a data stream, composed of different single channel signals, with a bit rate of a higher hierarchical level, characterised in that at least one multiplexer (MXH-Z) which has an interface (EPIC-Z) connected to a data bus (DH) and at least one interface (SSB-X) having at least one single channel interface point (EKS-XY) are each connected to a data bus (SH) and via a control bus (CB) to a programming and control station (CTRL) respectively.

2. Digital signal multiplexer according to claim 1, characterised in that the number of conductors of the data bus (SH), which is preferably operated bidirectionally, corresponds to the maximum number of multiplexers (MXH-Z) which exchange single channel data with the interface modules (SSB-X) via the data bus (SH).

3. Digital signal multiplexer according to claim 1, characterised in that the multiplexer (MXH-Z) has a configuration and alarm controller (KAC-Z) and a cycle counter (ZC) which are connected to the programming and control station (CTRL) via the control bus (CB, a single channel controller (EKC) and a multiple channel controller (VKC) connected to the interface (EPIC-Z) which are interconnected via a processor register memory (PR) which is controlled by the configuration and alarm controller (KAC-Z), and a channel call memory (KAR) which is connected to the configuration and alarm controller (KAC-Z), the single channel controller (EKC), the cycle counter (ZC) as well as a demultiplexer (DD) and a multiplexer (UM) which on the one hand are connected to the single channel IE 91733 ._> controller (EKC) and on the other hand via a buffer memory (UR) directly to the data bus (SH).

4. Digital signal multiplexer according to claim 3, characterised in that the multiple channel controller (VKC) is synchronised to the frames of incoming data, splits the data contained in the frame into single channel data and deposits this data in the processor register memory (PR), that the multiple channel controller (VKC) takes single channel data from the processor register memory (PR), locks this in a frame and delivers it to the interface (EPIC-Z), that in the processor register memory (PR) each single channel is allocated a memory area for each transfer direction, that in the processor register memory (PR) and in the channel call memory (KAR) configuration data for the multiple channel and the single channel controller (VKC, EKC) are deposited through the configuration and alarm controller (KAC-Z), that the multiple and single channel controller (VKC, EKC) deposits alarm signals for the configuration and alarm controller (KAC-Z) in these memory modules (PR), that the single channel controller (EKC) for each transfer direction contains addressable single programs for the bit-by-bit single channel data transfer as well as for generating and testing the single channel sided frame structure, that the configuration and alarm controller (KAC-Z) writes program configuration data units into the channel call memory (KAR) which are cyclically read into the single channel controller (EKC) and by means of which a single program is selected, that control data belonging to the particular program configuration data units from the channel address memory (KAR) are simultaneously applied to the demultiplexer (DD) as well as to the multiplexer (UM) and to the buffer memory (UR) , that, depending on the control data applied, the demultiplexer (DD) transfers single channel data bits from the single channel controller (EKC) to a conductor of the data bus (SH) or that a single channel data bit from a IE 91733 conductor of the data bus (SH) is delivered directly to the single channel controller (EKC) or through the multiplexer (UM) after intermediate storage in the buffer memory.

5. Digital signal multiplexer according to claim 1, characterised in that the interface module (SSB-X) has a configuration and alarm controller (KAC-X) and a cycle counter (ZC) which are connected to the programming and control station (CTRL) and a channel address memory (KAR), that the configuration and alarm controller (KAC-X) is connected via a control bus to all the single channel interfaces (EKS-XY), that the channel address memory (KAR) is connected via a control wire to the single channel interfaces (EKS-XY) as well as well as to a demultiplexer (UD) and a multiplexer (DM) , that the demultiplexer (UD) and the multiplexer (DM) on the one hand are connected to the data bus (SH) and on the other hand via a data wire to the single channel interfaces (EKS-XY) respectively.

6. Digital signal multiplexer according to claim 5, characterised in that the configuration and alarm controller (KAC-X) writes configuration data units into the channel address memory (KAR) which are cyclically applied to the single channel interfaces (EKS-XY) and to the multiplexers (DM, UD) , and that consequently single channel data bits are transferred from the single channel interfaces (EKS-XY) to the respective conductor of the data bus (SH) or vice versa.

7. A programmable, flexible digital signal multiplexer according to any preceding claim, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.