EP0439591A1 - Systeme de traitement des donnees et procede pour commander ce systeme, ainsi que carte d'unite centrale - Google Patents

Systeme de traitement des donnees et procede pour commander ce systeme, ainsi que carte d'unite centrale

Info

Publication number
EP0439591A1
EP0439591A1 EP19900912691 EP90912691A EP0439591A1 EP 0439591 A1 EP0439591 A1 EP 0439591A1 EP 19900912691 EP19900912691 EP 19900912691 EP 90912691 A EP90912691 A EP 90912691A EP 0439591 A1 EP0439591 A1 EP 0439591A1
Authority
EP
European Patent Office
Prior art keywords
cpu
main memory
system bus
switching mechanism
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900912691
Other languages
German (de)
English (en)
Inventor
Thomas Schlage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0439591A1 publication Critical patent/EP0439591A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the invention relates to a data processing system and a method for its control, the data processing system having a central computer unit (CPU), a main memory and a system bus which can be connected to the main memory and other functional units.
  • the invention also relates to a CPU board for a data processing system, in which the CPU is arranged on a separate board.
  • the CPU, the main memory and the input / output units (I / O units) or their controllers are usually each on a board, which is also called a board or card. All the functional units connected to the system bus are controlled centrally by the central computer unit (CPU), for example a microprocessor. Communication between the functional units and the CPU always runs via the system bus.
  • CPU central computer unit
  • an I / O unit wants to perform a data transfer with respect to the main memory, ie wants to read data into the main memory or read data from the main memory
  • the I / O unit sends a signal to the system bus, on the basis of which the CPU for is "stopped" for a short time, during which the I / O unit is given direct access, which is also referred to as DMA (Direct Memory Access), to the main memory.
  • DMA Direct Memory Access
  • So-called cache memories are used, for example, as small, fast buffers, which can be arranged on the same board as the CPU.
  • the CPU reads data from the main memory via the system bus and " writes this data to the fast cache memory on the CPU board. If the CPU now wants to access this data again, it must no longer carry out the data transfer from the main memory via the relatively slow system bus, but can directly access the fast cache memory.
  • the object of the invention is to increase the operational behavior of the data processing system in that as many tasks as possible can be processed simultaneously and the waiting times on the system bus are reduced.
  • main memory can be connected directly to the CPU, a first switching mechanism which controls the connection between the CPU and the main memory, and a second switching mechanism which controls the connection between the system bus and the main memory, wherein the first and the second rear derailleur are connected so that only one of the two Switchgear can release the respective connection of the CPU or the system bus with the main memory.
  • a first buffer which is controlled by the first switching mechanism, and a second buffer between the system bus and the main memory is provided between the CPU and the main memory, ensures that the data transfer between the CPU and the main memory, on the one hand and the system bus and the main memory on the other hand is done correctly.
  • the main memory, the first and second switching mechanisms and the first and second buffers are preferably provided on the same board as the CPU.
  • one or more I / O units without direct memory access are provided, which can be connected directly to the CPU via a CPU bus, the CPU optionally with the main memory or one of the I / O units can be connected without direct memory access.
  • the CPU board according to the invention which is described in claims 7 to 11, can be marketed independently of the data processing system, as long as compatibility with the corresponding data processing system is ensured.
  • FIG. 1 shows a schematic block diagram of a data processing system according to the invention
  • Fig. 2 is a flow chart for explaining the operation of a first rear derailleur
  • Fig. 3 is a flow chart to explain the operation of a second switching mechanism.
  • the data processing system has a central computer unit (CPU) 1, a main memory 2 and a system bus 3.
  • the CPU 1 is connected to the main memory 2 via a first buffer 4.
  • the control takes place via a first switching mechanism 5.
  • the main memory 2 is also connected to the system bus 3 via a buffer 6, the control being carried out via a second switching mechanism 7.
  • the data processing system also has a CPU bus 8, through which the CPU 1 is connected to a number of I / O units without direct access, that is to say I / O units without DMA.
  • the embodiment shown is a register set 9, a boot PROM 10, a setup EEPROM 11 and further serial interfaces 12.
  • the I / O units 9 to 12 are typical I / O units which are connected to the system bus 3 in the known data processing systems.
  • the register set 9 usually has an interrupt controller, a clock generator and a real-time clock.
  • Boot PROM 10 and set EEPROM 11 contain the functions for starting the system, the configuration data, hardware-related functions, diagnostic programs, " self-test programs, etc. " in a known manner.
  • the serial interfaces 12 are, for example eight serial interrupt-lines connected to the Svstemkonsole ', terminals, printers, modems u. Like. Are connected. Furthermore, a floating point unit (not shown) can be connected to the CPU bus in a known manner.
  • All of the components shown in FIG. 1 are preferably arranged on the CPU board.
  • the first switching mechanism 5 controls all processes close to the CPU, such as accesses by the CPU 1 to the main memory 2 and to the I / O units without DMA, which are identified in FIG. 1 by the reference numerals 9 to 12.
  • the second switching mechanism 7 controls the processing of the DMA System bus 3 requirements, the actual memory accesses of the DMA units and the CPU 1 accesses to the system bus 3.
  • the first switching mechanism 5 and the second switching mechanism 7 operate in the so-called handshaking process, whereby mutual locking is ensured when access requirements occur simultaneously.
  • step 101 a query is made as to whether the CPU 1 should access main memory 2. If this is not the case, a query is made in step 102 as to whether there is a request for or an interrupt from one of the I / O units identified by reference numerals 9 to 12 in FIG. 1 without DMA. If this is the case, the request or the interrupt is processed in step 103.
  • step 101 If it is determined in step 101 that the main memory 2 is to be accessed, the switching mechanism 5 occupies the main memory 2 in step 104 and emits a corresponding occupancy signal to the switching mechanism 7. If it is determined in step 105 that the main memory 2 is occupied, that is to say an access from a DMA unit via the system bus 3 the main memory 2 is present, the process continues until the main memory 2 is free. After that. The storage action is carried out in step 106, the buffer 4 being controlled accordingly by the switching mechanism 5. After the storage action has ended, the main memory 2 is released again in step 107 and a corresponding release signal is sent from the switching mechanism 5 to the switching mechanism 7.
  • step 201 a query is made as to whether there is a request from a DMA unit via the system bus 3. If this is the case, the switching mechanism 7 issues the DMA release to the system bus 3 in step 202. A bidirectional connection is then established between the switching mechanism 7 via the system bus 3 to the DMA unit connected to the system bus 3 and the first part of the bus protocol is processed in step 203. The switching mechanism 7 then occupies the main memory 2 and emits a corresponding occupancy signal to the switching mechanism 5. If it is determined in step 205 that the main memory 2 is occupied, ie there is still access from the CPU 1 to the main memory 2, the system waits until the main memory 2 is free is. The storage action is then carried out in step 206, the buffer 6 being controlled accordingly by the switching mechanism 7.
  • step 207 the main memory 2 is released in step 207 and a corresponding release signal is sent from the switching mechanism 7 to the switching mechanism 5. Then in step 208 the second part of the bus protocol is processed in communication between the switching mechanism 7 and the DMA unit.
  • the main memory is not occupied during the entire standardized standard cycle time of a DMA access, which runs from steps 201 to 208 in FIG. 3, but only during the absolutely necessary time, which results from steps 204 to 207 in Fig. 3 results.
  • the time referred to as idle time (steps 201 to 203 and step 208 in FIG. 3) between memory allocation (steps 204 to 207 in FIG. 35 and the standard cycle time (steps 201 to 208 in FIG. 3) can be used for other purposes are, for example, for an access of the CPU to the main memory, so that the actual memory accesses can be nested in time.
  • a further increase in system performance can be achieved in that the CPU can process requests from I / O units without DMA access while the main memory is occupied by the system bus, so that true parallel processing is possible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)

Abstract

Dans un système de traitement des données comportant une unité centrale, une mémoire principale (2) et un bus de système (3) pouvant être relié à la mémoire principale (2) et à différentes autres unités fonctionnelles, la mémoire principale (2) peut être reliée directement à l'unité centrale (1) et il est prévu un premier dispositif de commutation (5), qui commande la liaison entre l'unité centrale (1) et la mémoire principale (2), et un deuxième dispositif de commutation (7), qui commande la liaison entre le bus de système (3) et la mémoire prinicpale (2), le premier et le deuxième dispositif de commutatiion (5, 7) étant reliés entre eux de telle manière que l'un seulement des deux dispositif puisse libérer la liaison de l'unité centrale (1) ou celle du bus de système (3) avec la mémoire principale. La mémoire principale, le premier et le deuxième dispositif de commutation ainsi que la première et la deuxième mémoire tampon sont disposés sur la même carte que l'unité centrale (1).
EP19900912691 1989-08-23 1990-08-23 Systeme de traitement des donnees et procede pour commander ce systeme, ainsi que carte d'unite centrale Withdrawn EP0439591A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE8910102U 1989-08-23
DE8910102 1989-08-23

Publications (1)

Publication Number Publication Date
EP0439591A1 true EP0439591A1 (fr) 1991-08-07

Family

ID=6842240

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19900912691 Withdrawn EP0439591A1 (fr) 1989-08-23 1990-08-23 Systeme de traitement des donnees et procede pour commander ce systeme, ainsi que carte d'unite centrale

Country Status (5)

Country Link
EP (1) EP0439591A1 (fr)
JP (1) JPH06105447B2 (fr)
AU (1) AU6164090A (fr)
CA (1) CA2039715A1 (fr)
WO (1) WO1991003020A1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1485758A (en) * 1973-09-16 1977-09-14 Hawker Siddeley Dynamics Ltd Computer systems
JPS5533268A (en) * 1978-08-31 1980-03-08 Toshiba Corp Dma system for electronic computer
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
JPS62231367A (ja) * 1986-04-01 1987-10-09 Meidensha Electric Mfg Co Ltd Ｄｍａデ−タ転送方式
US4771286A (en) * 1986-07-28 1988-09-13 Honeywell Bull Inc. Lan controller having split bus design

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9103020A1 *

Also Published As

Publication number Publication date
CA2039715A1 (fr) 1991-02-24
JPH06105447B2 (ja) 1994-12-21
WO1991003020A1 (fr) 1991-03-07
AU6164090A (en) 1991-04-03
JPH04502975A (ja) 1992-05-28

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