EP0383952A1 - Systeme constitue permettant d'etendre l'echelle logique d'un reseau logique programmable - Google Patents

Systeme constitue permettant d'etendre l'echelle logique d'un reseau logique programmable Download PDF

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Publication number
EP0383952A1
EP0383952A1 EP89909865A EP89909865A EP0383952A1 EP 0383952 A1 EP0383952 A1 EP 0383952A1 EP 89909865 A EP89909865 A EP 89909865A EP 89909865 A EP89909865 A EP 89909865A EP 0383952 A1 EP0383952 A1 EP 0383952A1
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EP
European Patent Office
Prior art keywords
logic
logic array
supplied
setting data
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89909865A
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German (de)
English (en)
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EP0383952A4 (en
Inventor
Hideki Shutou
Fumihiro Suenaga
Minoru Takeno
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of EP0383952A1 publication Critical patent/EP0383952A1/fr
Publication of EP0383952A4 publication Critical patent/EP0383952A4/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable

Definitions

  • the present invention relates to an extended logical scale structure of a programmable logical array, and more particularly to an extended logical scale structure of a programmable logic array which makes it possible to extend the scale of a logic circuit formed by a single logic array to a scale equivalent to the scale of a logic circuit formed by a plurality of logic arrays.
  • a programmable logic array (hereinafter simply referred to as a PLA) is hardware for a logical calculation which can achieve a programmable logic circuit, and is a logic operation circuit which can present a desired logic circuit by a simple structure and which execute logic operation at high speeds.
  • FIG.1 shows a basic structure of a PLA.
  • FIG.1 illustrates a PLA which achieves a logic operation circuit having two inputs (x 1 , x 2 ) and two outputs (y l , Y 2 ) .
  • An input x 1 is supplied to an input buffer 11 1 .
  • a positive logic output x 1 of the input buffer 11 1 is output to an input line 1 1 , and a negative logic output x 1 thereof is output to an input line 1 2 .
  • an input is supplied to an input buffer 11 2 .
  • a positive logic output x 2 of the input buffer 11 2 is output to an input line 1 3 , and a negative logic output x 2 thereof is output to an input line 1 4 .
  • Resistors 12 1 and 12 2 each having an end connected to ground are connected to input terminals of output buffers 13 1 and 13 2 through output lines O 1 and 0 2 , respectively.
  • Product term lines a 1 and a 2 extend in the direction perpendicular to the input lines 1 1 - 1 4 and the output lines O 1 and O 2 .
  • the product term lines a 1 and a 2 are supplied with a high-level voltage Vcc through resistors 14 1 and 14 2 , respectively.
  • Intersecting points where the input lines 1 1 - 1 4 and the output lines O 1 and 0 2 intersect with the product term lines a 1 and a 2 are called PLA intersecting points 15.
  • a wiring group of the input lines 1 1 - 1 4 and the product term lines a 1 and a 2 is called an AND array 16.
  • a wiring group of the output lines O 1 and 0 2 and the product term lines a 1 and a 2 is called an OR array 17.
  • the inputs x 1 and x 2 are drawn through the output buffers 13 1 and 13 2 as the outputs y 1 and y 2 , which are represented by a logic formula of a desired sum-of-products style by making related some of the PLA intersecting points 15 closed or open.
  • the product term line a 1 is logic 1 when both the logic x 1 of the input line 1 1 and the logic x 2 of the input line 1 4 are logic 1.
  • the product term line a 2 is logic 1 when both the logic x 1 of the input one l 2 and the logic x 2 of the input line 1 3 are logic 1.
  • the output line O 1 is logic 1 when at least one of the product lines a 1 and a 2 is logic 1.
  • the output line O 2 is logic 1 when the product term line a 1 is logic 1. Therefore, the logical relationship between the outputs y 1 , y 2 and the inputs x l , x 2 are as follows:
  • a desired logic circuit can be formed by making a decision on whether each of the PLA intersecting points 15 should be made closed or open.
  • each of the PLA intersecting points 15 shown in FIG.1 is formed by use of a fuse 18 shown in FIG.2.
  • all the fuses 18 corresponding the PLA intersecting points 15 are short-circuits at the stage of production.
  • a current pulse is applied to some of the fuses 18 selected based on the contents of a program achieved by a desired logic circuit.
  • the unnecessary fuses 18 at the PLA intersecting points 15 are made open so that desired configurations of the AND array 16 and the OR array 17 can be obtained.
  • a PLA which has not been programmed at the manufacturing stage and which is programmed when used by users, is called a field programmable logic array (hereinafter simply referred to an FPLA).
  • the fuses 18 must be fused by a specific fusing device in order to form a desired logic circuit. For this reason, programming is freely possible only before the user mounts the FPLA on a user's device. Further, the programmed contents cannot be modified after fusing.
  • the proposed PLA is an FPLA which provides a desired logic circuit by controlling the semiconductor switching element 19 through a control line 20 shown in FIG.3 on the base of ON/OFF information (hereinafter referred to as intersecting point information also) stored in a memory element.
  • Such an FPLA is called an electrically alterable programmable logic array (hereinafter simply referred to as an EAPLA).
  • the scale of logic circuit is based on the number of semiconductor switching elements 19 equal to the number of the PLA intersecting points 15. For this reason, the degree of freedom to design logic circuits is low. Further, a structure of large size is required to achieve complex logic operation and a variety of logic operations.
  • the present invention was made taking into account the above-mentioned matters, and is directed to providing an extended logical scale structure of a programmable logic array which makes it possible to extend the scale of a logic circuit formed by a single logic array to a scale equivalent to the scale of a logic circuit formed by a plurality of logic arrays.
  • an extended logical scale structure of a programmable logic array logic array means for carrying out a logic operation provided by a logic circuit.for an input signal and for providing an output signal indicative of an operation result
  • the logic array means including semiconductor switching elements provided at programmable logic array intersecting points, the logic operation of the logic circuit being set by logic setting data supplied to the semiconductor switching elements, storage means for storing a plurality of sets of logic setting data, and setting means for selecting one of the sets of logic setting data stored in the storage means and supplying the logic array means with the selected set of logic setting data.
  • selecting means for sequentially selecting one of the sets of logic setting data stored in the storage means and supplying the logic array means with the selected one of sets of logic setting data
  • latch means for temporarily storing the operation result supplied from the logic circuit of the logic array means and for outputting the latched operation result to the logic array means as the input signal for the logic array means and alternatively outputting the operation result as the output signal indicative of the operation result
  • setting means provided with the latched operation result, for selecting one of the sets of logic setting data when the operation result is stored in the latch means.
  • the logic array circuit is divided into a plurality of blocks, and the storage means is divided into the same number of memory areas.
  • the extended logical scale structure further includes normality/detect detecting means for comparing the logic setting data read out from one of the plurality of memory areas and ON/OFF information on the semiconductor switching elements obtained by supplying the read-out logic setting data to corresponding one of the blocks and for determining whether the structure operates correctly on the basis of the comparison result.
  • a single PLA is formed by a logic array part 21, a storage circuit 23 and a setting circuit 24.
  • the logic array part 21 includes semiconductor switching elements 22 provided at PLA intersecting points.
  • a logic circuit based on logic setting data is formed by executing switching control of the semiconductor switching elements 22 on the based of the logic setting data.
  • the storage circuit 23 has been provided with a plurality of sets of logic setting data beforehand.
  • the setting circuit 24 sequentially selects a set of logic setting data among the plurality of sets of logic setting data stored in the storage circuit 23, and outputs the selected logic setting data to the logic array part 21. Thereby, corresponding one of the logic circuits is sequentially formed in the logic array part 21.
  • An input signal which is input to the logic array part 21 through an input terminal 25 is subjected to logic operation provided by the logic circuits, which are sequentially set one by one by the setting circuit 24.
  • the results of the logic operation are sequentially output to an output terminal 26.
  • the present invention makes it possible to select one of the plurality of logic circuits provided by the single logic array part 21. As a result, it becomes possible to extend the scale of the single logic array 21 to a logical scale equal to the logical scale provided by a plurality of logic array parts.
  • FIG.5 A description is given of a first embodiment of the present invention with reference to FIG.5.
  • FIG.5 those parts which are the same as those shown in FIG.4 are given the same reference numerals, and a description thereof is omitted.
  • an input signal composed of bits applied to input terminals 31 1 and 31 2 in parallel form is in phase with a control signal supplied to an input terminal 32.
  • Selectors 33 1 and 33 2 are provided on the input side of the logic array part 21, and form an input selection circuit 34.
  • Registers 35 and 36 form the aforementioned storage circuit 23.
  • the register 35 has been provided with first logic setting data which consists of m bits.
  • the register 36 has been provided with second logic setting data which consists of m bits.
  • Either the m-bit parallel logic setting data supplied from the register 35 or the m-bit parallel logic setting data supplied from the register 36 is selected by m selectors 37 1 -37 m , and then supplied to the logic array part 21.
  • the supplied logic setting data executes ON/OFF switching control of the m semiconductor switching elements (not shown) provided at the PLA intersecting points in the logic array part 21.
  • the logic array part 21 is set to a first logic circuit structure at the time of inputting the first logic setting data, and a second logic circuit structure at the time of inputting the second logic setting data.
  • Latch circuits 38 and 39 are provided on the output side of the logic array part 21.
  • the latch circuit 38 latches the output signal composed of two bits supplied from the logic array part 21 in synchronism with the rise of the control signal through the input terminal 32, and feeds back the latched output signal to the input selection circuit 34.
  • the latch circuit 38 is made up of inverters 40 1 , 40 2 , a first flip-flop circuit consisting of NAND circuits 41 1 and 42 1 , and a second flip-flop circuit consisting of NAND circuits 41 2 and 4 2 2 .
  • the latch circuit 39 latches the output signal composed of two bits supplied from the logic array part 21 in synchronism with the fall of the control signal through the input terminal 32, and outputs the latched output signal outside of the PLA through external terminals 46 1 and 46 2 in parallel form.
  • the latch circuit 39 is made up of inverters 43 1 , 43 2 , a third flip-flop consisting of NAND circuits 44 1 and 45 1 , and a fourth flip-flop consisting of NAND circuits 44 2 and 45 2 .
  • the selectors 33 1 and 33 2 provided in the input selection circuit 34 selects one of the input signal supplied to the input terminals 31 1 and 31 2 and the output signal to be supplied the NAND circuits 41 1 and 41 2 provided in the latch circuit 38 on the basis of the level of the control signal.
  • the selectors 33 1 , 33 2 , and 37 1 - 37 m are of the same structure as shown in FIG.6, for example.
  • a first input terminal 51 and a second input terminal 52 are connected to input terminals of two-input AND circuits 54 and 55, respectively.
  • a control signal input terminal 53 (corresponding to the aforementioned control signal input terminal 32) is connected to the other input terminal of the AND circuit 54 through an inverter 56, and directly connected to the other input terminal of the AND circuit 55.
  • the output terminals of the AND circuits 54 and 55 are coupled to an output terminal 58 through a two-input OR circuit 57.
  • the selector shown in FIG.6 outputs the second input signal applied to the input terminal 52 to the output terminal 58 when the control signal is at a high level.
  • the selector outputs the first input signal applied to the input terminal 51 to the output terminal 58 when the control signal is at a low level.
  • the 2-bit input signal is supplied to the logic array 21 first, and is then processed by the first logic circuit formed by use of the first logic setting data stored in the register 35.
  • the 2-bit output signal supplied from the first logic circuit is supplied to the logic array part 21, and is then processed by the second logic circuit formed by use of the second logic setting data stored in the register 36. Then the output signal supplied from the second logic circuit is output outward through the latch circuit 39.
  • the present invention is not limited to the two-bit inputs and the twp-bit outputs.
  • selectors 33 1 , 33 2 , ..., 33 Q are used, and each of the latch circuits 38 and 39 includes l flip-flops.
  • the PLA of the first embodiment is of the synchronous type.
  • FIG.7(A) shows a waveform of the control signal supplied to the input terminal 32.
  • the illustrated control signal is at a low level (L level) during the time between times t 1 and t 2 , and is at a high level (H level) during the time between times t 2 and t 3 .
  • L level low level
  • H level high level
  • FIG.7(B) shows a waveform of the input signal supplied to the input terminals 31 1 and 31 2 in parallel form. The content of the input signal is changed from A to B just prior to time t 3 .
  • the input signal A is drawn through the selectors 33 1 and 33 2 and supplied to the logic array part 21.
  • the first logic setting data indicated by a referenced shown in FIG.7(D) is drawn from the register 35 through the selectors 37 1 through 37 m , and is input to the logic array part 21 so that the logic array part 21 is set to the first logic circuit.
  • the input signal A is subjected to the logic operation by the first logic circuit formed in the logic array part 21.
  • the output signal supplied from the logic array part 21 is indicated as I shown in FIG.7(E).
  • the output signal I of the logic array part 21 is latched by the latch circuit 38 when the control signal is switched to H level at time t 2 as shown in FIG.7(A). That is, when the control signal is switched from L level to H level, the output signal bit supplied from the first output line through the inverter 40 1 is latched by the NAND circuits 41 1 and 42 1 , and the output signal bit supplied from the second output line through the inverter 40 2 is latched by the NAND circuits 41 2 and 42 2 .
  • the same control signals to be supplied to the NAND circuits 45 1 and 45 2 are inverted through the inverters 43 1 and 43 2 , respectively, so that they switch from H level to L level and thus the NAND circuits 44 1 , 4 5 2 , 44 2 and 45 2 are made inactive.
  • the second logic setting data stored in the register 36 is drawn through the selectors 37 1 - 37 m .
  • the output signal supplied from the latch circuit 38 (the result of the second logic operation) indicated by a reference shown in F I G .7(C) is selected by the selectors 33 1 and 33 2 .
  • the logic array part 21 outputs a signal as indicated by II shown in FIG.7(E), which is obtained by applying the logic operation provided by the second logic circuit by use of the second logic setting data to the result of the first logic operation.
  • the output signal supplied to the output terminals 46 1 and 46 2 from the latch circuit 39 is switched at time t 4 as indicated by II shown in FIG.7(F).
  • the output signal II shown in FIG.7(F) is the same as the output signal supplied from the logic array part 21 indicated by reference II shown in FIG.7(E), and is a signal obtained by passing the input signal through the first logic circuit and the second logic circuit in this order.
  • the first embodiment it is possible to configure the first and second logic circuits formed by use of two sets of logic setting data registered in the registers 35 and 36 within one period of the control signal (clock signal). It follows that the first embodiment has the logic scale twice the logic scale of the logic array part 21.
  • the above description relates to the case where the logic scale of the logic array part 21 is extended double. It is also possible to triple the logic scale or more by using three registers or more provided in the storage circuit 24.
  • FIG.8 A description is given of a second embodiment of the present invention with reference to FIG.8.
  • those parts which are the same as those shown in FIGS.1 and 4 are given the same reference numbers, and a description thereof is omitted.
  • the control terminals of the semiconductor switching elements provided at the PLA intersecting points 15 are connected to output terminals of a data latch circuit 61 through control lines 60.
  • the data latch circuit 61 latches logic setting data 62 related to all the PLA intersecting points 15 of the logic array part 21, and outputs the same to the corresponding PLA intersecting points 15 through the control lines 60.
  • the logic setting data 62 is defined by read-out data 64 which is supplied from a random access memory (hereinafter simply referred to as a RAM) 63 and is latched in the data latch circuit 61 in synchronism with a latch clock 65 derived from a control circuit 70.
  • the RAM 63 stores beforehand logic setting data 62 (read-out data 64) related to all the PLA intersecting points 15 in the logic array 21 for every available logic circuit.
  • the logic array part 21 can presents a plurality of logic circuits.
  • Either the output signal consisting of y 1 and Y2 or an address signal consisting of two bits is selected through an address selector 67 controlled by a select signal 68 supplied from the control circuit 70, and is then supplied, as a memory address signal 69, to the RAM 63.
  • the RAM 63 outputs, as read-out data 64, corresponding one of the sets of logic setting data on the basis of the supplied memory address signal 69.
  • the above-mentioned operation can be executed during the time when a write enable signal W supplied from the control circuit 70 is made active.
  • logic setting data 62 related to four logical states 1 - 4 are stored in the RAM 63 beforehand.
  • FIG.10(A) shows a storage format of the logic setting data 62 related to four logical states.
  • An area 91 labeled “STATE 1” stores the logic setting data 62 to be output as read-out data 64 when the outputs y 1 and Y 2 are (0, 0).
  • An area 92 labeled “STATE 2” stores the logic setting data 62 to be output as read out data 64 when the outputs y 1 and y 2 are (0, 1).
  • An area 93 labeled “STATE 3” stores the logic setting data 62 to be output as read-out data 64 when the outputs y 1 and Y 2 are (1, 0).
  • An area 94 labeled "STATE 4" stores the logic setting data 62 to be output as read out data 64 when the outputs y and y 2 are (1, 1).
  • the address selector 67 selects the two-bit initial setting address 66 by the select signal 68 supplied from the control circuit 70, and outputs, as the memory address signal 69, the same to the RAM 63, so that the RAM 63 is accessed.
  • the write enable signal W is supplied to the RAM 63 from the control circuit 70 so that the RAM 63 is set to the output enable state.
  • the logic setting data 62 corresponding to one of the four states 1 - 4 shown in FIG.10(A) is output as the read-out data 64, which is latched in synchronism with the latch clock 65 supplied from the control circuit 70. Then the logic setting data 62 controls the states of the PLA intersecting points 15 provided in the logic array part 21 through the control lines 60. Thus, the logical state formed by the logic array part 21 is defined.
  • the select signal 68 controls the address selector 67 so as to select the outputs y 1 and y 2 .
  • the RAM 63 is accessed by the memory address signal 69 which is formed by the settled output signals y 1 and y 2 .
  • the write enable signal W sets the RAM 63 to the output enable state with an appropriate timing
  • the state corresponding to the logical state defined by the outputs y 1 and y 2 is selected from among the states 1 - 4 shown in FIG.10(A), and is then latched, as the read-out data 64, by the data latch circuit 61.
  • each of the PLA intersecting points 15 of the logic array part 21 is set to the state indicated by the corresponding read-out data 64.
  • the logic of the logic circuit formed by the logic array part 21 is dynamically changed based on a change of the logic state of the outputs y and y 2 . That is, an operation such that the logical state of the logic circuit is transitional by its own output state can be achieved. Therefore, since a decision on which one of the the states 1 - 4 is selected is made by its own outputs y and y 2 , there is no need for a specific state transition control circuit for use in state selection. As a result, it is possible to achieve high-level logical state control for the logic array part 21 only by adding the control circuit 70 which generates the select signal 68, the latch clock signal 65 and the write enable signal W.
  • the kind of the logic operation to be next executed can be designated by the logic state of the outputs y 1 and y 2 .
  • FIG.9 A description is given of a third embodiment of the present invention with reference to FIGS.9 through 11.
  • a latch circuit consisting of inverting amplifiers 72 and 73 is connected to the control line 60 for each of the PLA intersecting points 15.
  • the latch circuit is supplied with one bit of logic setting data 76 through a control line 75 and a semiconductor switching element 74.
  • OR array 78 Although only an OR array 78 is illustrated in detail in FIG.9, an AND array 77 is formed in the same manner as the OR array 78.
  • Semiconductor switching elements 74 are connected to related one of the control lines 75 for each of the product term lines a and a 2 in each of the AND array 77 and the OR array 78.
  • the control lines 75 are connected to output terminals of driver buffers 79 1 and 79 2 .
  • each of the semiconductor switching elements 74 is ON/OFF controlled by related one of control lines c1 - c 6 extending from a decoder 80. Any one of the control lines c l - c 6 is made active, and the semiconductor switching elements 74 in the row corresponding to the activated control line are simultaneously turned ON. Then logic setting data 76 is written into the latch circuits (inverting amplifiers 72 and 73) related to the row through the control lines 75 at the same time.
  • a RAM 81 is a memory which stores logic setting data 76 for a plurality of logical states.
  • the logic setting data 76 for each of the states relates to all the PLA intersecting points 15 provided in the logic array part 21.
  • Either the output signal consisting of bits y 1 and Y2 a 2-bit initial setting address 82 is selected by the address selector 67 on the basis of the select signal 68 supplied thereto, and is then input to an address control circuit 83.
  • the address control circuit 83 sequentially outputs a memory address signal 84 related to a row of the PLA intersecting points 15 in response to the settled signal supplied from the address selector 67.
  • the memory address signal 84 sequentially designates the address of the RAM 81 whereby designated one of the plurality of sets of logic setting data 76 is output from the RAM 81.
  • the above-mentioned operation is executable when the write enable signal W is in the enable state.
  • the memory address signal 84 is input to the decoder 80, which is thereby made active.
  • the activated decoder 80 sequentially makes the control lines c 1 - c 6 one by one in synchronism with a gate signal 86 supplied from the address control circuit 83.
  • the third embodiment can provide four logical states based on two bits y 1 and Y2 of the output signal in the same manner as the second embodiment shown in FIG.8.
  • the RAM 81 has the logic setting data 76 for all the PLA intersecting points 15 provided in the logic array part 21 for each of the four logical states.
  • FIG.10(B) is a storage format of the logic setting data 76 for the third embodiment.
  • the area provided for every logical state is divided into sub-areas related to the input lines 1 1 to 1 4 and the output lines O 1 , O 2 .
  • the address selector 67 selects the initial setting address 82 consisting of two bits in response to the select signal 68 supplied from a control circuit 85.
  • the address control circuit 83 accesses one of the areas 95 - 98 related to the states 1 - 4 shown in FIG.10(B).
  • the selected one of the areas 95 - 98 is accessed for each of the sub-areas related to the rows for the input lines 1 1 - 1 4 and the output lines O 1 and 0 2 of the logic array part 21.
  • FIG.11 is a timing chart illustrating the above-mentioned operation.
  • the write enable signal W supplied from the control circuit 85 is changed to L level as shown in FIG.11(C), whereby the RAM 81 is set to the output enable state.
  • the address control circuit 83 outputs the memory address signal 84 which indicates an address on the RAM 81 to the area corresponding to the input line 1 1 provided in the logic array part 21. Then the RAM 81 is accessed and the corresponding logic setting data 76 is output to the control lines 75 through the driver buffers 79 1 and 792.
  • the memory address signal 84 related to the input line 1 1 is input to the decoder 80. Further, the gate signal 86 derived from the address control circuit 83 is output with a timing shown in FIG.11(B). Thus, the decoder 80 makes the control line c 1 active with a timing when the gate signal 86 becomes low-active. The activated control line c 1 turns ON the semiconductor switching elements provided in the PLA intersecting points 15 related to the input line 1 1 in the AND array 77.
  • the logic setting data 76 which is output from the RAM 81 through the above-mentioned operation is latched by the latch circuits (inverting amplifiers 72 and 73) coupled to the PLA intersecting points 15 for the input line 1 1 . Then the logical states of the PLA intersecting points 15 related to the input line 1 1 are settled. Then, the address control circuit 83 sequentially outputs the address related to the input lines 1 2 - 1 4 and the output lines O 1 and 0 2 by the memory address signal 84 shown in FIG.11(A) so that the above-mentioned operation is repeatedly executed. As a result, the logical states of all the PLA intersecting points 15 provided in the logic array part 21 are settled within the period when the write enable signal W shown in FIG.11(C) is held active.
  • the logic of the logic circuit formed by the logic array part 21 is dynamically changed on the base of a change of the logic state defined by the outputs y and y 2 , and the logical state of the logic circuit is made transitional by its own output state.
  • the second embodiment shown in FIG.8 differs from the third embodiment shown in FIG.9 in the following.
  • the second embodiment has the data latch circuit 61 having a capacity corresponding to all the PLA intersecting points 15 provided in the logic array part 21.
  • the third embodiment has one latch circuit for each of the PLA intersecting points 15 in the logic array part 21.
  • the data latch circuit 61 of the second embodiment is provided outside of the logic array part 21.
  • the data latch circuits each consisting of two inverting amplifiers 72 and 73 are provided within the logic array part 21.
  • the logical state of the logic array part 21 for the third embodiment is controlled on the basis of the output signal of the logic array part 21.
  • the logical scale of PLA is extended by sequentially and selectively providing the logic array part 21 with logic setting data. In this case, it is important to check whether desired logic setting data has correctly been set in the logic array part 21.
  • FIG.12 a description is given of a fourth embodiment in which such a checking operation is executed.
  • those parts which are the same as those shown in FIG.4 are given the same reference numerals.
  • a circuit portion corresponding to the setting circuit 24 shown in FIG.4 can be formed by the circuit used in any one of the first to third embodiments, and therefore it is omitted from FIG.12.
  • the logic array part 21 is divided into three blocks 211, 212 and 213. It is determined whether each of the first, second and third blocks 211, 212 and 213 can operate correctly by an operation which is to be executed during a time when a test control signal through an input terminal 100 is at a high level.
  • An intersecting point information memory 101 corresponding to the storage circuit 23 shown in FIG.4 has three divided memory areas 101a, 101b and 101c, which correspond to the first, second and third blocks 211, 212 and 213, respectively, all of which form the logic array part 21.
  • the divided memory areas 101a, 101b and 10Ic separately supply the first, second and third blocks 211, 212 and 213 with logic setting data through control lines 102 1 , 102 2 and 102 3 , respectively.
  • the logic array part 21 supplies the output signal to the output terminal 26, and at the same time provides output lines 103 1 , 103 2 and 103 3 with intersecting point signals which are ON/OFF information on the semiconductor switching elements 22 provided at the PLA intersecting points 15.
  • the intersecting point signals supplied to the output lines 103 1 , 103 2 and 103 3 are supplied to an intersecting point signal selector 104.
  • the logic setting data output to the control lines 102 1 - 102 3 are supplied to an intersecting point information signal selector 105.
  • the intersecting point signal selector 10 4 and the intersecting point information signal selector 105 are controlled by a selector control signal through an input terminal 106.
  • the intersecting point signal selector 104 selects one of the intersecting point signals and then supplies the same to a parity checker 107.
  • the intersecting point information signal selector 105 selects one of the logic setting data on the control lines 102 1 to 102 3 and then supplies a parity checker 108 with the selected logic setting data.
  • a comparator 109 compares the result of parity check supplied from the parity checkers 107 and 108. When both the results coincide with each other, the comparator 109 supplies an output terminal 111 with a detection signal that indicates the block of concern can operate correctly. Adversely, when the results are different from each other, the comparator 109 supplies the output terminal 111 with a detection signal which indicates that the block of concern is defective. That is, a normality/defect detection circuit 110 for the blocks 211, 212 and 213 formed in the logic array part 21 is formed by the intersecting point signal selector 104, the intersecting point information signal selector 105, the parity checkers 107, 108 and the comparator 109.
  • FIG.13A is a circuit diagram of the logic array part 21 shown in FIG.12
  • FIG.13B is a circuit diagram of an essential part of the configuration shown in FIG.13A.
  • FIGS.13A and 13B those parts which are the same as those shown in FIG.12 are given the same reference numerals, and a description thereof is omitted.
  • input signals applied to input terminals 25 1 - 25 3 are supplied to OR circuits 116 1 - 116 3 through input buffers 115 1 -115 3 .
  • the OR circuits 116 1 - 116 3 execute an OR operation on the input signals and the test control signal supplied through the input terminal 100.
  • Output terminals of the OR circuits 116 1 -116 3 are connected to input lines 117 1 - 117 3 .
  • Output lines 118 1 , 118 2 and 118 3 are arranged so as to be perpendicular to the input lines 117 1 , 117 2 and 117 3 , and are connected to output terminals 26 1 , 26 2 and 26 3 through output buffers 119 1 , 119 2 and 119 3 , respectively.
  • transistors 120 serving as semiconductor switching elements 22 are provided at the intersecting points of the input lines 117 1 - 117 3 and the output lines 118 1 - 118 3 (PLA intersecting points 15). Gates of the transistors 120 are connected to the control lines 102 (102 1 - 102 3 ), and drains or sources thereof are connected to the output lines 103 (103 1 - 103 3 ).
  • each of the intersecting point signal selector 104 and the intersecting point information signal selector 105 is formed by a selector having (m + 1) output terminals.
  • (m + 1) is the number of bits of data
  • x is a minimum of a power of 2 larger than n.
  • FIG.15 illustrates a structure for each of the parity checkers 107 and 108 shown in FIG.12.
  • Each of the parity checkers 107 and 108 is made up of (m - 1) exclusive-OR circuits, which carry out the parity check for the (m + 1) bits supplied from the selectors 104 and 105.
  • test control signal which is at H level is supplied to the logic array part 21 through the input terminal 100.
  • the output signals of the OR circuits 116 1 -116 3 shown in FIG.13A that is, the signals on the input lines 117 1 - 117 3 are all fixed to H level.
  • the semiconductor switching elements 22 are turned ON which are supplied with logic setting data having a value of "1" from the divided memory areas 101a - 101c through the control lines 102 1 - 102 3 .
  • the intersecting point signals supplied from the semiconductor switching elements 22 are supplied to the intersecting point signal selector 104.
  • the aforementioned logic setting data is supplied to the intersecting point information signal selector 105.
  • the intersecting point signal selector 104 and the intersecting point information signal selector 105 are controlled by the selector control signal, and select the intersecting point signals related to one of the blocks 211 - 213 and the logic setting data related to corresponding one of the divided memory areas 101a - 101c.
  • the intersecting point information signal selector 105 selects the logic setting data related to the first memory area 101a of the intersecting point information memory 101.
  • the signals output from the intersecting point signal selector 104 are supplied to the parity checker 107 and subjected to the parity check.
  • the result of the parity check is based on the number of semiconductor switching elements 22 (120) which are ON.
  • the signals output from the intersecting point information signal selector 105 are supplied to the parity checker 108 and subjected to the parity check.
  • the result of the parity check is based on the intersecting point information signal which turns the semiconductor switching elements 22 ON.
  • the comparator 109 compares the parity check results obtained by the parity checkers 107 and 108. In other words, the comparator 109 determines whether the number of semiconductor switching elements 22 (120) which are ON is equal to the number of semiconductor switching elements 22 (120) which are requested to be turned ON by the logic setting data. When both the numbers are different from each other, the logic array part 21 is determined to have a defect. In this case, the comparator output is supplied to the output terminal 111 as a defect detection signal.
  • the PLA of the fourth embodiment has a self-diagnosis function.
  • FIG.16 is a diagram illustrating a case where a defective block has been detected.
  • each of the intersecting point information memory 101 and the logic array part 21 is divided into three blocks. If the third block 213 is detected to be defective as shown in FIG.16(B), the third memory area 101c corresponding to the third block 213 of the logic array part 21, and the defective third block 213 are inhibited from be used. Then related information to be set in the logic array part 21 is written into the first and second memory areas 101a and 101b of the intersecting point information memory 101. Thus, a logic circuit consisting of the first and second blocks 211 and 212 of the logic array part 21 is formed.
  • the fourth embodiment is not limited to the case. According to the fourth embodiment, it is possible to detect a defect of logic setting data.
  • a plurality of kinds (sets) of logic setting data are stored in the intersecting point information memory 101. Therefore, by sequentially carrying out the aforementioned defect detection procedure for each of the sets of logic setting data, plural detection results can be obtained.
  • the fourth embodiment can detect an error of logic setting data.
  • a plurality of logic circuits related to a plurality of sets of logic setting data can be formed by a single logic array part.
  • the logical scale of a single logic array part can equivalently be extended to a logical scale obtained by a plurality of logic arrays.
  • different sets of logic setting data are selectively set in the logic array part one by one at the same time as the output signal of the logic array part is fed back to the input side thereof.
  • the result of a complex logic operation obtained by cascading a plurality of logic circuits (logic arrays) can be obtained by a single logic array part which is provided with a plurality of sets of logic setting data.
  • the structure of logic circuit formed by a single logic array part can be changed by sequentially selecting one of sets of logic setting data on the basis of the logical state of the input signal or the output signal with respect to the logic array part.
  • a plurality of logic operations obtained by a plurality of logic circuits can be selected based on the input signal or the output signal with respect to the logic array part.
  • a variety of logic operations can be achieved by a minimum hardware structure.
  • the logic array part is divided into a plurality of blocks and the memory area which stores logic setting data is divided into the same number of memory areas.
  • the logic setting data read out from the plurality of memory areas are sequentially supplied to the corresponding divided blocks.
  • the output of the block being processed is compared with the logic setting data related to the corresponding memory area and it is determined whether there is a defect on the basis of the comparison result.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

Dans le système constitué décrit, qui sert à étendre l'échelle logique d'un réseau logique programmable équipé d'une unité de réseau logique (21), des éléments de commutation à semi-conducteur (22) disposés au point d'intersection du réseau logique programmable subissent une opération de commutation qui est commandée par des données de réglage de circuit logique émises depuis une unité extérieure, afin de régler un circuit logique, et une opération logique est effectuée par le circuit logique ainsi réglé en réponse aux signaux d'entrée et le résultat de l'opération obtenu est produit. Le système constitué servant à étendre l'échelle logique du réseau logique programmable comprend un circuit à mémoire (23) qui stocke à l'avance les données de réglage de circuit logique, ainsi qu'un circuit de réglage (24) qui sélectionne successivement une après l'autre les données de réglage de circuit logique dans la multitude des données de réglage de circuit logique stockées dans le circuit à mémoire (23) et qui fournit ses données à l'unité de réseau logique (21) pour permettre la commutation du circuit logique dans l'unité de réseau logique (21).
EP19890909865 1988-08-31 1989-08-30 Constitution for expanding logic scale of a programmable logic array Withdrawn EP0383952A4 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP215260/88 1988-08-31
JP21525988 1988-08-31
JP21526088 1988-08-31
JP215259/88 1988-08-31
JP232540/88 1988-09-19
JP23254088 1988-09-19

Publications (2)

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EP0383952A1 true EP0383952A1 (fr) 1990-08-29
EP0383952A4 EP0383952A4 (en) 1991-07-03

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EP19890909865 Withdrawn EP0383952A4 (en) 1988-08-31 1989-08-30 Constitution for expanding logic scale of a programmable logic array

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US (1) US5132570A (fr)
EP (1) EP0383952A4 (fr)
AU (1) AU614426B2 (fr)
CA (1) CA1326303C (fr)
WO (1) WO1990002450A1 (fr)

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EP0512536A2 (fr) * 1991-05-10 1992-11-11 Kabushiki Kaisha Toshiba Unité et circuit logiques programmables

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JP2564044B2 (ja) * 1991-02-27 1996-12-18 株式会社東芝 プログラマブル論理回路
US5384499A (en) * 1991-04-25 1995-01-24 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
US5268598A (en) * 1991-04-25 1993-12-07 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
JP2965802B2 (ja) * 1991-12-19 1999-10-18 株式会社東芝 半導体集積回路
CA2158467A1 (fr) * 1993-03-17 1994-09-29 Richard D. Freeman Reseaux configurables a memoire vive (ram)

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EP0512536A3 (fr) * 1991-05-10 1995-08-02 Kabushiki Kaisha Toshiba Unité et circuit logiques programmables

Also Published As

Publication number Publication date
US5132570A (en) 1992-07-21
CA1326303C (fr) 1994-01-18
EP0383952A4 (en) 1991-07-03
AU614426B2 (en) 1991-08-29
AU4199689A (en) 1990-03-23
WO1990002450A1 (fr) 1990-03-08

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