JPS53121537A - Semiconductor logic circuit device - Google Patents
Semiconductor logic circuit deviceInfo
- Publication number
- JPS53121537A JPS53121537A JP3669877A JP3669877A JPS53121537A JP S53121537 A JPS53121537 A JP S53121537A JP 3669877 A JP3669877 A JP 3669877A JP 3669877 A JP3669877 A JP 3669877A JP S53121537 A JPS53121537 A JP S53121537A
- Authority
- JP
- Japan
- Prior art keywords
- logic circuit
- circuit device
- semiconductor logic
- connection
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To secure an easy constitution or modification for the desired logic circuit after its manufacture, by having a connection or non-connection by means of the information memorized in the memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3669877A JPS53121537A (en) | 1977-03-31 | 1977-03-31 | Semiconductor logic circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3669877A JPS53121537A (en) | 1977-03-31 | 1977-03-31 | Semiconductor logic circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS53121537A true JPS53121537A (en) | 1978-10-24 |
Family
ID=12476988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3669877A Pending JPS53121537A (en) | 1977-03-31 | 1977-03-31 | Semiconductor logic circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS53121537A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62269420A (en) * | 1986-05-16 | 1987-11-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
WO1990002450A1 (en) * | 1988-08-31 | 1990-03-08 | Fujitsu Limited | Constitution for expanding logic scale of a programmable logic array |
JPH03500117A (en) * | 1988-02-01 | 1991-01-10 | モトローラ・インコーポレーテッド | Encryption method and device with electronically redefinable algorithms |
JP2544494B2 (en) * | 1988-08-31 | 1996-10-16 | 富士通株式会社 | Logical scale expansion configuration of programmable logic array |
US5761483A (en) * | 1995-08-18 | 1998-06-02 | Xilinx, Inc. | Optimizing and operating a time multiplexed programmable logic device |
US5784313A (en) * | 1995-08-18 | 1998-07-21 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
US5825662A (en) * | 1995-08-18 | 1998-10-20 | Xilinx, Inc. | Computer-implemented method of optimizing a time multiplexed programmable logic device |
US6047115A (en) * | 1997-05-29 | 2000-04-04 | Xilinx, Inc. | Method for configuring FPGA memory planes for virtual hardware computation |
US6421817B1 (en) | 1997-05-29 | 2002-07-16 | Xilinx, Inc. | System and method of computation in a programmable logic device using virtual instructions |
-
1977
- 1977-03-31 JP JP3669877A patent/JPS53121537A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62269420A (en) * | 1986-05-16 | 1987-11-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPH03500117A (en) * | 1988-02-01 | 1991-01-10 | モトローラ・インコーポレーテッド | Encryption method and device with electronically redefinable algorithms |
WO1990002450A1 (en) * | 1988-08-31 | 1990-03-08 | Fujitsu Limited | Constitution for expanding logic scale of a programmable logic array |
US5132570A (en) * | 1988-08-31 | 1992-07-21 | Fujitsu Limited | Extended logical scale structure of a programmable logic array |
JP2544494B2 (en) * | 1988-08-31 | 1996-10-16 | 富士通株式会社 | Logical scale expansion configuration of programmable logic array |
US5784313A (en) * | 1995-08-18 | 1998-07-21 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
US5761483A (en) * | 1995-08-18 | 1998-06-02 | Xilinx, Inc. | Optimizing and operating a time multiplexed programmable logic device |
US5825662A (en) * | 1995-08-18 | 1998-10-20 | Xilinx, Inc. | Computer-implemented method of optimizing a time multiplexed programmable logic device |
US5959881A (en) * | 1995-08-18 | 1999-09-28 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
US5978260A (en) * | 1995-08-18 | 1999-11-02 | Xilinx, Inc. | Method of time multiplexing a programmable logic device |
US6263430B1 (en) | 1995-08-18 | 2001-07-17 | Xilinx, Inc. | Method of time multiplexing a programmable logic device |
US6480954B2 (en) | 1995-08-18 | 2002-11-12 | Xilinx Inc. | Method of time multiplexing a programmable logic device |
US6047115A (en) * | 1997-05-29 | 2000-04-04 | Xilinx, Inc. | Method for configuring FPGA memory planes for virtual hardware computation |
US6421817B1 (en) | 1997-05-29 | 2002-07-16 | Xilinx, Inc. | System and method of computation in a programmable logic device using virtual instructions |
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