EP0343963B1 - Diamanttransistor und Verfahren zu seiner Herstellung - Google Patents

Diamanttransistor und Verfahren zu seiner Herstellung Download PDF

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Publication number
EP0343963B1
EP0343963B1 EP89305259A EP89305259A EP0343963B1 EP 0343963 B1 EP0343963 B1 EP 0343963B1 EP 89305259 A EP89305259 A EP 89305259A EP 89305259 A EP89305259 A EP 89305259A EP 0343963 B1 EP0343963 B1 EP 0343963B1
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EP
European Patent Office
Prior art keywords
source
layer
substrate
metal
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89305259A
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English (en)
French (fr)
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EP0343963A2 (de
EP0343963A3 (en
Inventor
Barbara Lynn Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
De Beers Industrial Diamond Division Pty Ltd
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De Beers Industrial Diamond Division Pty Ltd
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Application filed by De Beers Industrial Diamond Division Pty Ltd filed Critical De Beers Industrial Diamond Division Pty Ltd
Publication of EP0343963A2 publication Critical patent/EP0343963A2/de
Publication of EP0343963A3 publication Critical patent/EP0343963A3/en
Application granted granted Critical
Publication of EP0343963B1 publication Critical patent/EP0343963B1/de
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond

Definitions

  • This invention relates to a field effect transistor formed from diamond material.
  • FETS Field effect transistors
  • FETS Field effect transistors
  • FETS Field effect transistors
  • FETS Field effect transistors
  • the physical properties of diamond result in it having superior characteristics to silicon (Si), gallium arsenide (GaAs) or other known semi-conductive materials in this application.
  • Si silicon
  • GaAs gallium arsenide
  • diamond FETs can be expected to have a lower resistance, and a higher gain and maximum frequency than transistors employing conventional materials.
  • JP-A-60246627 which provides the basis for the prior art portion of claim 1, discloses a MISFET structure in which a diamond substrate is ion-implanted to have source and drain regions and a gate is positioned on a diamond film insulating layer between those regions.
  • a field effect transistor comprising a diamond substrate provided with a gate electrode and spaced apart source and drain regions, respective ohmic or quasi-ohmic source and drain contacts being applied to the source and drain regions with the gate electrode being located between and separated from the source and drain contacts characterized in that said substrate is p type, said source and drain regions are formed by the deposition of p+ semiconductor material on the surface of the substrate and said gate electrode is on or adjacent to said substrate surface.
  • the gate electrode may be separated from the surface of the substrate by an insulating layer of a wide-bandgap material, to provide a MISFET configuration.
  • the gate electrode may be applied directly to the surface of the substrate to provide a MESFET configuration.
  • the source and drain contacts applied to the source and drain regions may be quasi-ohmic contacts formed by the deposition of p+ doped amorphous silicon or germanium on the substrate above the source and drain regions, with a metal layer being deposited on the p+ doped silicon or germanium.
  • the metal layer may comprise aluminium, molybdenum, molybdenum/tantalum alloy, chrome, titanium, nichrome, titanium/tungsten alloy, palladium, platinum, or an aluminium/silicon alloy.
  • a layer of a second metal, different from the first metal, is deposited over the layer of insulating material and then selectively removed from the source and drain regions, so that a MISFET structure is obtained having source and drain contacts of the first metal and a gate contact of the second metal.
  • a portion of the layer of insulating material is removed above the gate region to expose the substrate, a layer of a second metal having a low work function is deposited over the source, gate and drain regions, and the layer of the second metal is then selectively removed from the source and drain regions, so that a MESFET structure is obtained having source and drain contacts of the first metal and a gate contact of the second metal.
  • the second metal may be, in the latter case, aluminium, gold or titanium, for example.
  • the layer of p+ doped amorphous silicon or germanium and the layers of the first and second metals are preferably deposited by chemical vapour deposition (CVD) or physical vapour deposition (PVD).
  • the selective removal of portions of the various layers is preferably done by a photolithographic masking and etching process.
  • the wide-bandgap insulating material preferably comprises an oxide, nitride, oxynitride or carbide, and is preferably deposited by a CVD or PVD process.
  • a p-type diamond substrate 10 is shown schematically.
  • a layer 12 of p+ doped amorphous silicon or germanium is applied to the upper surface of the substrate 10 by means of a chemical vapour deposition (CVD) process, or by means of a physical vapour deposition (PVD) process.
  • CVD chemical vapour deposition
  • PVD physical vapour deposition
  • a layer 14 of a first metal is deposited on top of the p+ layer 12, again by means of a CVD or PVD process.
  • metals which are suitable are aluminium, molybdenum, molybdenum/tantalum alloy, chrome, titanium, nichrome, titanium/tungsten alloy, palladium, platinum, or an aluminium/silicon alloy.
  • a portion of the layers 14 and 12 has been removed selectively by a photolithographic masking and a chemical etching process, exposing the substrate 10 in a region which defines the gate of the transistor. Regions on either side of the gate (G) area define the source (S) and drain (D) of the transistor.
  • a layer 16 of a wide-bandgap insulating material is applied over the structure of Figure 1c, again by means of a CVD or PVD process, covering the source, gate and drain regions.
  • the insulating material is an oxide, nitride, oxynitride, or a carbide.
  • Figure 1e shows a further metallic layer 18, of a second metal which is different from the metal of the layer 14, deposited onto the layer 16 of insulating material.
  • a CVD or PVD process is used.
  • the second metal although different from the first metal of the layer 14, is selected from the group of metals listed above.
  • portions of the layers 18 and 16 are selectively removed by photolithographic masking and chemical etching, to expose the metallic layer 14 above the source and drain regions of the transistor. It can thus be seen that the transistor is provided with metallic contacts of the first metal for the source and drain regions, and a contact of the second metal for the gate region.
  • the transistor has a MISFET structure, with the insulating layer 16 lying between the metal gate contact and the p-type semiconductor substrate of the transistor.
  • the illustrated transistor has no p-n junctions, a transistor switching action is, nevertheless, obtained. If a positive voltage is applied to the gate contact, a corresponding negative charge is induced in the insulating layer adjacent the gate contact. This is balanced by a positive charge in the insulating layer adjacent the surface of the substrate, which again induces a negative charge in the substrate adjacent its surface. This effectively forms an n-type channel in the substrate between the source and drain regions.
  • FIG. 2a to 2d a process for manufacturing a second version of the transistor will be described.
  • the second version of the process is similar to that described above, up to the point were the layer 16 of insulating material is applied to the structure illustrated in Figure 1d.
  • the structure of Figure 2a therefore corresponds to that of Figure 1d.
  • the insulating layer 16 is selectively etched right down to the surface of the substrate 10, to define a gate (G) region.
  • a layer 20 of a second metal which differs from the metal of the layer 14, is deposited over the structure by a CVD or PVD process.
  • the metallic layer 20 is thus in contact with the surface of the substrate 10 in the gate region.
  • the layers 20 and 16 are selectively removed by photolithographic masking and chemical etching, to expose the metal layer 14 above the source and drain regions of the transistor.
  • a transistor is thus obtained which has source and drain contacts of the first metal and a gate contact of the second metal.
  • the transistor has a MESFET configuration, with the metallic gate contact being directly in contact with the substrate 10 in the gate region of the transistor.
  • the layer 16 of insulating material serves to isolate the gate contact from the source and drain contacts.

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
  • Carbon And Carbon Compounds (AREA)

Claims (12)

  1. Feldeffekttransistor umfassend ein Diamant-Substrat (10), der mit einer Steuerelektrode (18, 20) und voneinander getrennten Quellen- und Abzugsbereichen (S, D) versehen ist, und wobei die jeweiligen ohmschen oder quasiohmschen Quellen- und Abzugskontakte (14) auf die Quellen- und Abzugsbereiche (S, D) aufgebracht werden, wobei die Steuerelektrode (18, 20) zwischen und getrennt von den Quellen- und Abzugskontakten angeordnet ist, dadurch gekennzeichnet, daß das Substrat vom p-Typ ist, die Quellen- und Abzugsbereiche (S, D) durch Abscheiden von p+ - Halbleitermaterial (12) auf der Oberfläche des Substrats gebildet werden und die Steuerelektrode (18, 20) auf oder nahebei der Substratoberfläche angeordnet ist.
  2. Feldeffekttransistor nach Anspruch 1, dadurch gekennzeichnet, daß die Steuerelektrode (18) von der Oberfläche des Substrats durch eine Isolierschicht (16) aus einem Material mit breitem Bandabstand getrennt ist, um eine MISFET-Konfiguration bereitzustellen.
  3. Feldeffekttransistor nach Anspruch 1, dadurch gekennzeichnet, daß die Steuerelektrode (20) direkt auf die Oberfläche des Substrats aufgebracht wird, um eine MESFET-Konfiguration bereitzustellen.
  4. Feldeffekttransistor nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die Quellen- und Abzugskontakte (14), die auf die Quellen- und Abzugsbereiche (S, D) aufgebracht sind, quasi-ohmsche Kontakte sind, die durch Abscheidung von p+ - dotiertem, amorphen Silicium oder Germanium (12) auf dem Substrat (10) über den Quellen- und Abzugsbereichen gebildet werden und wobei eine metallische Schicht (14) auf dem p+ - dotierten Silicium oder Germanium abgeschieden wird.
  5. Feldeffekttransistor nach Anspruch 4, dadurch gekennzeichnet, daß die Metallschicht (14) Aluminium, Molybdän, Molybdän/Tantal-Legierung, Chrom, Titan, Nichrom, Titan/Wolfram-Legierung, Palladium, Platin oder eine Aluminium/Silicium-Legierung umfaßt.
  6. Verfahren zur Herstellung eines Feldeffekttransistors, dadurch gekennzeichenet, daß es die folgenden Stufen umfaßt:
    - Bereitstellen eines Diamant-Substrats (10) vom p-Typ
    - Abscheiden einer Schicht (12) aus p+ - dotiertem, amorphem Silicium oder Germanium auf der Oberfläche des Substrats;
    - Abscheiden einer Schicht (14) eines ersten Metalls über der p+ - Schicht;
    - selektives Entfernen von Teilen der Schicht (14) des ersten Metalls und der p+ - Schicht (12), um voneinander getrennte Quellen- und Abzugsbereiche (S, D) des Transistors zu definieren, wobei der Steuerelektrodenbereich (G) durch einen ausgesetzten Teil des Substrats zwischen den Quellen- und Abzugsbereichen definiert ist;
    - Abscheiden einer Schicht (16) eines Isoliermaterials mit breitem Bandabstand über den Quellen-, steuerelektroden- und Abzugsbereichen;
    - selektives Entfernen von Teilen der Schicht (16) des Isoliermaterials und
    - Bereitstellen metallischer Kontakte (14, 18) für die Quellen-, Steuerelektroden- und Abzugsbereiche, die durch das Isoliermaterial getrennt sind.
  7. Verfahren gemäß Anspruch 6, dadurch gekennzeichnet, daß eine Schicht eines zweiten Metalls (18), das von dem ersten Metall (14) verschieden ist, über der Schicht des Isoliermaterials (16) abgeschieden wird und anschließend selektiv von den Quellen- und Abzugsbereichen (S, D) entfernt wird, sodaß eine MISFET-Struktur erhalten wird, die Quellen- und Abzugskontakte (14) des ersten Metalls und einen Steuerelektrodenkontakt (18) des zweiten Metalls aufweist.
  8. Verfahren gemäß Anspruch 6, dadurch gekennzeichnet, daß ein Teil der Schicht (16) des Isoliermaterials über dem Steuerelektrodenbereich (6) entfernt wird, um das Substrat (10) freizulegen, eine Schicht (18) eines zweiten Metalls mit einer geringen Austrittsarbeit über den Quellen-, Steuerelektroden- und Abzugsbereichen (S, G, D) abgeschieden wird und die Schicht (18) des zweiten Metalls dann selektiv von den Quellen- und Abzugsbereichen entfernt wird, sodaß eine MESFET-Struktur erhalten wird, die über Quellen- und Steuerelektrodenkontakte (14) des ersten Metalls und einen Steuerelektrodenkontakt (18) des zweiten Metalls verfügt.
  9. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß das zweite Metall Aluminium, Gold oder Titan ist.
  10. Verfahren nach einem der Ansprüche 7 bis 9, dadurch gekennzeichnet, daß die Schicht (12) aus p+ - dotiertem, amorphem Silicium oder Germanium und die Schichten (14, 18) des ersten und zweiten Metalls durch chemische Dampfabscheidung (CVD) oder physikalische Dampfabscheidung (PVD) abgeschieden werden.
  11. Verfahren nach einem der Ansprüche 6 bis 10, dadurch gekennzeichnet, daß die selektive Entfernung von Teilen der verschiedenen Schichten durch ein photolithographisches Maskierung- und chemisches Ätzverfahren erfolgt.
  12. Verfahren nach einem der Ansprüche 6 bis 11, dadurch gekennzeichnet, daß das Isoliermaterial (16) mit einem breiten Bandabstand ein Oxid, Nitrid, Oxinitrid oder Carbid umfaßt und durch ein CVD- oder PVD-Verfahren abgeschieden wird.
EP89305259A 1988-05-24 1989-05-24 Diamanttransistor und Verfahren zu seiner Herstellung Expired - Lifetime EP0343963B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8812216 1988-05-24
GB888812216A GB8812216D0 (en) 1988-05-24 1988-05-24 Diamond transistor method of manufacture thereof

Publications (3)

Publication Number Publication Date
EP0343963A2 EP0343963A2 (de) 1989-11-29
EP0343963A3 EP0343963A3 (en) 1990-10-31
EP0343963B1 true EP0343963B1 (de) 1994-09-14

Family

ID=10637402

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89305259A Expired - Lifetime EP0343963B1 (de) 1988-05-24 1989-05-24 Diamanttransistor und Verfahren zu seiner Herstellung

Country Status (6)

Country Link
US (1) US5072264A (de)
EP (1) EP0343963B1 (de)
AT (1) ATE111637T1 (de)
DE (1) DE68918158T2 (de)
GB (1) GB8812216D0 (de)
ZA (1) ZA893922B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU630663B2 (en) * 1989-02-01 1992-11-05 Gersan Establishment P-n-p diamond transistor
US5099296A (en) * 1990-04-06 1992-03-24 Xerox Corporation Thin film transistor
US5173761A (en) * 1991-01-28 1992-12-22 Kobe Steel Usa Inc., Electronic Materials Center Semiconducting polycrystalline diamond electronic devices employing an insulating diamond layer
JPH04302172A (ja) * 1991-03-29 1992-10-26 Kobe Steel Ltd ダイヤモンドショットキーダイオード
US5254869A (en) * 1991-06-28 1993-10-19 Linear Technology Corporation Aluminum alloy/silicon chromium sandwich schottky diode
US5155559A (en) * 1991-07-25 1992-10-13 North Carolina State University High temperature refractory silicide rectifying contact
US5371378A (en) * 1992-06-08 1994-12-06 Kobe Steel Usa, Inc. Diamond metal base/permeable base transistor and method of making same
US5294814A (en) * 1992-06-09 1994-03-15 Kobe Steel Usa Vertical diamond field effect transistor
USH1287H (en) 1992-06-16 1994-02-01 The United States Of America As Represented By The Secretary Of The Navy Ion implanted diamond metal-insulator-semiconductor field effect transistor
JP3117563B2 (ja) * 1992-11-24 2000-12-18 株式会社神戸製鋼所 ダイヤモンド薄膜電界効果トランジスタ
US5686737A (en) * 1994-09-16 1997-11-11 Cree Research, Inc. Self-aligned field-effect transistor for high frequency applications
US5455432A (en) * 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US6432804B1 (en) * 2000-05-22 2002-08-13 Sharp Laboratories Of America, Inc. Sputtered silicon target for fabrication of polysilicon thin film transistors
JP2003203930A (ja) * 2002-01-08 2003-07-18 Nec Compound Semiconductor Devices Ltd ショットキーゲート電界効果型トランジスタ
US7402835B2 (en) * 2002-07-18 2008-07-22 Chevron U.S.A. Inc. Heteroatom-containing diamondoid transistors
US20100078652A1 (en) 2007-01-22 2010-04-01 Geoffrey Alan Scarsbrook Diamond electronic devices including a surface and methods for their manufacture

Family Cites Families (6)

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US4016587A (en) * 1974-12-03 1977-04-05 International Business Machines Corporation Raised source and drain IGFET device and method
JPS58141572A (ja) * 1982-02-18 1983-08-22 Seiko Epson Corp 半導体装置
JPS59208821A (ja) * 1983-05-13 1984-11-27 Sumitomo Electric Ind Ltd 気相合成によるダイヤモンド半導体およびその製造方法
JPS60246627A (ja) * 1984-05-21 1985-12-06 Sumitomo Electric Ind Ltd ダイヤモンド半導体素子
JPS61207078A (ja) * 1985-03-11 1986-09-13 Sanyo Electric Co Ltd 電界効果トランジスタ
JP2536523B2 (ja) * 1987-05-14 1996-09-18 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
GB8812216D0 (en) 1988-06-29
DE68918158T2 (de) 1995-01-12
ATE111637T1 (de) 1994-09-15
DE68918158D1 (de) 1994-10-20
EP0343963A2 (de) 1989-11-29
EP0343963A3 (en) 1990-10-31
US5072264A (en) 1991-12-10
ZA893922B (en) 1990-02-28

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