EP0314877A1 - Structure de transistor de puissance, à haute mobilité électronique - Google Patents

Structure de transistor de puissance, à haute mobilité électronique Download PDF

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Publication number
EP0314877A1
EP0314877A1 EP88111246A EP88111246A EP0314877A1 EP 0314877 A1 EP0314877 A1 EP 0314877A1 EP 88111246 A EP88111246 A EP 88111246A EP 88111246 A EP88111246 A EP 88111246A EP 0314877 A1 EP0314877 A1 EP 0314877A1
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EP
European Patent Office
Prior art keywords
semiconductor layer
layer
hole
cross
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88111246A
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German (de)
English (en)
Inventor
Erhard Dr. Kohn
Edward Mark Schneider
Chia-Jen Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0314877A1 publication Critical patent/EP0314877A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • the present invention relates to field effect transistors and more particularly to modulation-doped high mobility field effect transistors (MODFET), also referred to as high electron mobility transistors (HEMT).
  • MODFET modulation-doped high mobility field effect transistors
  • HEMT high electron mobility transistors
  • FET's Field effect transistors (FET's) using gallium arsenide (GaAs) as know to be capable of high speed operation.
  • Devices using gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) heterostructures form a two-dimensional electron gas (2DEG).
  • 2DEG two-dimensional electron gas
  • the donor impurities are confined away from the active channel in which electrons may flow. This separation of donor impurities from the electron layers causes the device to exhibit extremely high electron mobilities and thereby to be capable of extremely fast operation, for example, in high speed switching.
  • HEMT structures utilize a narrow recess configuration for the control gate so as to reduce the effects of series resistance regions not subject to gate control. While such a configuration allows a transistor to be constructed with high RF gain and low noise figure, the source to drain breakdown voltage tends to be low, for example, 4-6 volts, because of field crowding at relatively sharp corners where the trapezoidal-shaped sides of the gate recess or trench in the GaAs meet the bottom. Consequently, the breakdown voltage is primarily determined by the geometrical configuration of the gate metal-2DEG interface rather than the doping level in the AlGaAs layer.
  • the breakdown voltage may be increased by introducing a separation between the gate metal and the drain recess or trench edge, this is herein recognized to be generally undesirable if it is not narrow and tightly controlled since it can lead to current limiting and current lagging effects associated with surface depletion and field dependent trapping and detrapping effects in the doped AlGaAs as well as other problems including I-V collapse at low temperatures in the dark.
  • the gate to drain breakdown voltage may be increased by a parasitic gate to drain voltage drop, this does not result in an increase of RF output power.
  • a modulation doped field effect transistor comprises a first semiconductor layer having a second semiconductor layer formed thereon.
  • An insulating layer which is to be used as an etch mask in fabrication is formed on the second semiconductor layer.
  • a hole for a gate electrode passes through the insulating layer and the second semiconductor layer, and extends into the first semiconductor layer. The wall portions of the hole in the first and second semiconductor layers respectively slope in opposite directions.
  • each of the wall portions slopes away from a central axis of the hole, in the direction towards the interface between the first and second semiconductor layers.
  • the second semiconductor layer is underdcut at its interface with the insulating layer, so that the hole is smaller in the insulating layer than in the second semiconductor layer.
  • FIGURE shows an embodiment in accordance with the invention, in cross-section and not to scale.
  • the FIGURE shows a high electron mobility transistor (HEMT) in accordance with the invention, in which 10 is a GaAs layer, relatively undoped.
  • Adjacent layer 10 is an AlGaAs layer 12, relatively heavily n-doped. This acts as a doner layer and forms a two-dimensional electron gas (2DEG) in a region of layer 10 adjacent layer 12, which is the active channel.
  • Layer 14 is relatively heavily n-doped GaAs and over this is an insulating layer 16 of, for example, silicon nitride (Si3N4) which can be etched selectively with respect to the underlying semiconductor layers.
  • a gate trench or recess 17 has a hole portion 18 in layer 16.
  • hole portion 20 continues as hole portion 20 in layer 14, hole portion 20 being larger adjacent layer 16 than hole portion 18, so that insulating layer 16 overhangs hole portion 20. Proceeding through semiconductor layer 14, hole portion 20 becomes progressively larger until the interface with semiconductor layer 12. Thereafter, proceeding through semiconductor layer 12, hole portion 20 becomes progressively smaller until a bottom 22 is reached in semiconductor layer 12.
  • the walls of the gate hole 17 is semiconductor layer 14 slope away from the center in the (downward) direction towards the interface between semiconductor layers 12 and 14 whereas those walls slope away from the center in semiconductor layer 12 in the (upward) direction towards the same interface.
  • Hole 17 contains a metallic gate electrode 24 formed therein.
  • a gate electrode is being deposited in fabrication, shadowing by insulating layer 16 causes gate electrode 24 substantially not to occupy the portions of hole 17 in the undercut part.
  • the exact profile of the gate metal edge and the hole edge can be varied by changing the extend of the shielding during deposition provided by insulating layer 16 and by changing the thicknesses of layers 12 and 14, either in total thickness and/or the ratio of respective thicknesses.
  • hole 17 is obtainable by using a 011 gate finger orientation on a 100 oriented GaAs substrate, that is, the length horizontally in the plane of the paper in the FIGURE. Since GaAs is etched preferentially, this results in a reentrant recess profile in the 011 direction. However AlGaAs is etched non-preferentially and this results in a cylindrical profile independent of the gate orientation. As a result of layers 12 and 14 being AlGaAs and GaAs respectively, the overall resulting shape, as illustrated in the FIGURE has a relatively flat interface between the gate metal bottom and AlGaAs layer 12, blending into a gentle curve towards the sides.
  • the gate metal does not fill hole 17 out to its sides, a sharp-cornered interface between gate metal and the GaAs/AlGaAs interface is prevented and an extended thin, flat AlGaAs region adjacent the gate metal is avoided. Accordingly, high electric fields at the recess edge are thereby prevented and the gate to drain breakdown voltage is increased without introducing a thin, parasitic AlGaAs layer adjacent the gate metal. In measurements made with a structure in accordance with the present invention, the gate to drain breakdown voltage was found to be substantially improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)
EP88111246A 1987-08-07 1988-07-13 Structure de transistor de puissance, à haute mobilité électronique Withdrawn EP0314877A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83751 1987-08-07
US07/083,751 US4774555A (en) 1987-08-07 1987-08-07 Power hemt structure

Publications (1)

Publication Number Publication Date
EP0314877A1 true EP0314877A1 (fr) 1989-05-10

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EP88111246A Withdrawn EP0314877A1 (fr) 1987-08-07 1988-07-13 Structure de transistor de puissance, à haute mobilité électronique

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US (1) US4774555A (fr)
EP (1) EP0314877A1 (fr)
JP (1) JPH0289324A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0429696A1 (fr) * 1989-11-28 1991-06-05 Siemens Aktiengesellschaft Transistor à effet de champ avec grille en forme de T

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231040A (en) * 1989-04-27 1993-07-27 Mitsubishi Denki Kabushiki Kaisha Method of making a field effect transistor
JPH04184973A (ja) * 1990-11-19 1992-07-01 Mitsubishi Electric Corp 長波長光送信ｏｅｉｃ
JP3027236B2 (ja) * 1991-07-25 2000-03-27 沖電気工業株式会社 半導体素子およびその製造方法
EP0862222A4 (fr) * 1996-09-19 1999-12-01 Ngk Insulators Ltd Dispositif a semi-conducteurs et procede de fabrication

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2168936A1 (fr) * 1972-01-27 1973-09-07 Labo Electronique Physique

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2120388A1 (de) * 1970-04-28 1971-12-16 Agency Ind Science Techn Verbindungshalbleitervorrichtung
JPS58143577A (ja) * 1982-02-22 1983-08-26 Toshiba Corp 埋め込みゲ−ト電界効果トランジスタの製造方法
FR2532471A1 (fr) * 1982-09-01 1984-03-02 Labo Electronique Physique Procede de realisation d'ouverture de faible dimension, utilisation de ce procede pour la fabrication de transistors a effet de champ, a grille alignee submicronique, et transistors ainsi obtenus
JPS61164270A (ja) * 1985-01-16 1986-07-24 Fujitsu Ltd ヘテロ接合電界効果トランジスタ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2168936A1 (fr) * 1972-01-27 1973-09-07 Labo Electronique Physique

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE ELECTRON DEVICE LETTERS, vol. EDL-4, no. 9, September 1983, pages 306-307, IEEE, New York, US; M.D. FEUER et al.: "High-speed low-voltage ring oscillators based on selectively doped heterojunction transistors" *
IEEE ELECTRON DEVICE LETTERS, vol. EDL-5, no. 7, July 1984, pages 241-243, IEEE, New York, US; Y. TAKANASHI et al.: "Control of threshold voltage of AlGaAs/GaAs 2DEG FET's through heat treatment" *
PATENT ABSTRACTS OF JAPAN, vol. 10, no. 236 (E-428)[2292], 15th August 1986; & JP-A-61 69 175 (NEC CORP.) 09-04-1986 *
PROCEEDINGS OF THE 4TH CONFERENCE ON SOLID STATE DEVICES, Tokyo, 1972, Supplement to the Journal of the Japan Society of Applied Physics, vol. 42, 1973, pages 78-87, Tokyo, JP; Y. TARUI et al.: "Self-aligned GaAs schottky barrier gate fet using preferential etching" *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0429696A1 (fr) * 1989-11-28 1991-06-05 Siemens Aktiengesellschaft Transistor à effet de champ avec grille en forme de T

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Publication number Publication date
JPH0289324A (ja) 1990-03-29
US4774555A (en) 1988-09-27

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