EP0265638A2 - Lithographic image size reduction - Google Patents
Lithographic image size reduction Download PDFInfo
- Publication number
- EP0265638A2 EP0265638A2 EP87113097A EP87113097A EP0265638A2 EP 0265638 A2 EP0265638 A2 EP 0265638A2 EP 87113097 A EP87113097 A EP 87113097A EP 87113097 A EP87113097 A EP 87113097A EP 0265638 A2 EP0265638 A2 EP 0265638A2
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- European Patent Office
- Prior art keywords
- opening
- layer
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- size
- mask
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- 238000005549 size reduction Methods 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 34
- 238000001459 lithography Methods 0.000 claims abstract description 23
- 239000012212 insulator Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 12
- 230000009467 reduction Effects 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical group C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910020781 SixOy Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- -1 SixOx Chemical compound 0.000 claims 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 description 12
- 238000002955 isolation Methods 0.000 description 5
- 238000010894 electron beam technology Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000036528 appetite Effects 0.000 description 1
- 235000019789 appetite Nutrition 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000001117 sulphuric acid Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000035899 viability Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
- Y10T428/24322—Composite web or sheet
Definitions
- the invention relates to a method of reducing lithographic image size for integrated circuit (IC) manufacture. More particularly, it is a method of forming a mask having openings of a size smaller than obtainable by lithography.
- Improved lithographic tools such as 1:1 optical projection systems fitted with deep-ultraviolet source and optics, electron-beam, direct-step-on-wafer, and X-ray and ion-beam systems and improved photoresist materials and processes such as multilayer resist utilizing a top resist sensitized to X-ray or electron-beam and bottom straight optical resist layer(s) are some of the components of this driving force.
- the invention precisely satisfies this need for reducing lithographic image sizes by extending lithographic resolution to smaller sizes than capable by lithography.
- the invention provides a method of reducing the size of a lithographic image by establishing a sidewall on the interior of the opening in the lithographic mask material used to obtain the image.
- the invention presents a process for making a mask having openings of a size smaller than obtainable by lithography.
- a substrate e.g., semiconductor, insulator or metal
- a thin release layer of an insulator material such as photoresist and silicon dioxide
- a thick layer of photosensitive material is then applied.
- the thick layer is patterned by lithographic means to have openings of a minimum size dictated by limits of lithography.
- a conformal layer material is applied to the patterned photosensitive layer and the substrate portions exposed by the openings in the patterned layer.
- the thickness of the conformal layer material is determined by the desired reduction in the size of the openings. For example, for an elongated opening, the reduction in the width of the opening is approximately twice the thickness of the conformal layer.
- An example of the conformal layer material is Si x O y formed by plasma-deposited hexamethyldisilazane (HMDS). By directional reactive ion etching (RIE), the conformal layer is removed from all the horizontal surfaces leaving sidewalls of the conformal layer material on the non-horizontal surfaces corresponding to the openings in the photosensitive material.
- the release layer exposed by the openings in the photosensitive material is also removed by RIE.
- the thick photosensitve mask in combination with the sidewalls of the conformal layer material constitute a new mask (stencil) having openings smaller than obtainable by lithography alone.
- This new mask can be used for a variety of purposes including ion implantation to implant the substrate exposed by the reduced-dimensioned openings therein, as a RIE mask to etch narrow trenches in the substrate, as an oxidation mask to form recessed oxide isolation in the exposed regions of the semiconductor substrate, as a contact or metallization mask to respectively establish narrow dimensioned contacts to or conductors on the substrate, etc. Following such use, the new mask is lifted off the substrate by subjecting the release layer to a wet etchant.
- the above mask forming process is modified by starting with a semiconductor substrate having thereon a thick insulator layer such as photoresist or polyimide.
- the new mask as described above is formed on the thick insulator, after which the thick insulator layer is patterned by RIE using the new mask as an RIE mask.
- the patterned thick insulator layer on the substrate will serve as a trench RIE mask for etching deep trenches having a width smaller than the lithography limit in the semiconductor material.
- the substrate 10 may be any material on which a photoactive layer can be coated and patterned by lithographic techniques.
- the substrate 10 may be a semiconductor material, glass, insulator, primary photosensitive material, metal or a combination thereof.
- a release layer 12 is applied to the substrate 10.
- the release layer 12 is composed of a material that is easily removable from the substrate 10. Such removal is made by wet chemical etchants or by oxygen ashing. Since the basic function of release layer 12 is to facilitate easy removal of itself, any subsequently formed layers/structures thereon are correspondingly removed as well. Examples of the material suitable for forming layer 12 include photoresist.
- AZ 1350J (trademark of American Hoechst Corporation) photoresist material is applied by spin coating, followed by baking at a temperature of about 200-250°C for about 30-60 mins. to obtain a release layer 12 of about 200-1000 A ° thickness. Below about 200 ⁇ thickness, the release layer would be too thin to reliably coat the substrate 10.
- a thick imaging layer 14 of a photosensitive material is applied, for example, by spin-coating as illustrated in Fig. 1.
- the imaging layer 14 is of a sufficient thickness in the range 0.8-3 microns.
- An example of the material of layer 14 is AZ 1350J photoresist.
- After coating the photosensitive material it is patterned in a desired pattern by pattern-exposing in a lithographic tool, developed, rinsed and dried.
- a single opening 16 having a lateral dimension A is shown in the layer 14 having a substantially horizontal surface 18 and substantially vertical surfaces 20-20.
- the dimension A may be the smallest image size that is obtainable by lithography.
- the width A may be the smallest dimension that is achievable by pushing lithography (which includes x-ray, electron-beam, etc.) to its highest resolution limit.
- the patterned photosensitive layer is subjected to a hardening process step to thermally stabilize the layer 14. Deep ultraviolet exposure or heat treatment at a temperature of about 200-250°C for about 1-2 mins. may be used for hardening.
- Another method of hardening the layer 14 is by subjecting it to a halogen gas plasma. This hardening step is needed for conventional photoresists, lest the photosensitive material constituting layer 14 may bubble up, melt and flow or otherwise get degraded during the deposition of subsequent layers thereon.
- the next step in the present process is establishing sidewalls on the vertical surfaces 20-20 to reduce the lateral dimension A of the opening 16 beyond that achievable by lithography alone.
- Sidewall technology is known to the prior art as exemplified by the following patents.
- U.S. pat. no. 4,209,349 assigned to the present assignee utilizes sidewall technology for forming small openings in a mask.
- first insulator regions are formed on a substrate so that horizontal and vertical surfaces are obtained.
- a second insulator layer is applied thereon of a material different from that of the first layer, and is subjected to RIE in such a manner that the horizontal regions of the second insulator are removed, with merely very narrow regions of this layer remaining on the vertical surface regions of the first insulator, and the respective regions of the substrate, respectively. Subsequently, the exposed substrate regions are thermally oxidized, and for finally forming the desired mask openings the regions of the second insulator layer there are removed.
- U.S. pat. no. 3,358,340 describes a method of making submicron devices using sidewall image transfer.
- a conductive film of submicron thickness is deposited across a vertical step between adjacent surfaces of an isolation, and subsequently vertically etched until there remains only part of the conductive film which is adjacent to the vertical step. The remaining isolation not covered by the conductor is removed, thus obtaining a submicron-wide gate of an MOS field effect transistor.
- U.S. pat. nos. 4,419,809 and 4,419,810 assigned to the present assignee disclose methods of making self-aligned field effect transistors using sidewall to define narrow gates.
- U.S. pat. no. 4,462,846 discloses use of sidewalls to minimize birds beak extensions of recessed oxide isolation regions.
- 4,502,914 assigned to the present assignee describes a method of making submicron structures by providing a polymeric material structure having vertical walls, the latter serving to make sidewall structure of submicron width.
- the sidewall structures are directly used as masks.
- another layer is applied over the side-wall structures, which is partly removed until the peaks of the sidewall structures are exposed. Subsequently, the sidewall structures themselves are removed and the resulting opening is used as a mask opening for fabricating integrated circuit devices.
- a conformal layer 22 is formed over the patterned photosensitive layer 14 and the portion of the release layer 12 exposed by the opening 16 therein.
- the conformal layer material may be polysilicon, Si x O y , silicon dioxide, silicon nitride, silicon oxynitride or a combination thereof.
- the conformal layer 22 may be any material which can be deposited at a temperature low enough as to not cause degradation of the patterned photosensitive layer 14.
- a preferred material for forming layer 22 is Si x O y obtained by hexamethyldisilazane (HMDS) plasma deposition.
- the layer 22 is formed by mounting the substrate with the structure of Fig. 1 in a plasma deposition system, introducing liquid HMDS into the process chamber and generating the necessary electric field therein which transforms the liquid HMDS into a HMDS plasma.
- the HMDS plasma will deposit on the structure of Fig. 1 obtaining a conformal and uniform layer 22 of plasma-deposited HMDS having the composition Si x O y .
- the thickness B of layer 22 is determined by the desired reduction in the lithographic image size in the photosensitive layer 14. Typically, for very large scale integrated circuit fabrication, the thickness of layer 22 is in the range 0.01 - 0.6 microns.
- the lower limit for the thickness of layer 22 is dictated by the requirements of good step coverage associated with the substantially vertical wall profile 20 in layer 14 and viability of the layer 22 as a thin film.
- the upper limit for the thickness of layer 22 is determined by the desired percentage reduction in the size of the opening 16 in the layer 14.
- the percentage reduction in the opening size is governed by the factor 2B/A. In other words, if the size of the opening is 3 microns, in order to achieve a 66.6% reduction in the size of the hole 16 (or an actual reduction of the hole size to 1 micron), a 1 micron thick HMDS layer 22 is deposited. After forming the conformal layer 22, next by anisotropic etching it is removed from all the substantially horizontal surfaces leaving it only on the substantially vertical surfaces of layer 14.
- RIE may be accomplished by a halogen-containing etchant gas.
- a halogen-containing etchant gas is CF4.
- CF4 a halogen-containing etchant gas
- the resulting structure will be as shown in Fig. 3 where the unetched portions of layer 22 are designated by 24, now serving as sidewalls on the vertical surfaces 20 of layer 14. Due to the establishment of the sidewalls 24 on the interior of the vertical surfaces of the opening, the size of the opening 16 is reduced to a new dimension designated as C in Fig. 3.
- the portion of the release layer 12 exposed by the reduced-size opening 16 is removed by RIE using, for example, either the same etchant species which facilitated removal of layer 22 from the horizontal surfaces of layer 14 or O2 plasma.
- the photosensitive mask in combination with the sidewalls 24 fabricated in this manner constitutes a new mask (or stencil) having openings of a substantially reduced dimension than obtainable by lithography alone.
- the new mask serves a variety of purposes. As illustrated in Fig. 4, for example, it may be used as an ion implantation mask to implant an extremely narrow/small region 26 of the substrate 10.
- Another application of the new mask is as an etch mask to etch extremely narrow deep/shallow trenches in the substrate 10.
- Yet another application is to grow a recessed isolation oxide free of bird's beak and bird's head of a width essentially equal to the dimension C by subjecting the substrate and the overlying stencil structure to a low temperature oxidation.
- a further use of the new mask is as a contact (liftoff) mask for establishing highly localized electrical contacts to the substrate.
- Another use of the mask is to form narrow conductor or insulator lines of width C on the substrate.
- the release layer 12 By subjecting the release layer 12 to a suitable etchant for example, a hot oxidizing acid such as nitric acid, sulphuric acid, or hot phenol it is lifted off the surface of the substrate thereby removing the overlying layer 14 and its associated sidewalls 24.
- a suitable etchant for example, a hot oxidizing acid such as nitric acid, sulphuric acid, or hot phenol it is lifted off the surface of the substrate thereby removing the overlying layer 14 and its associated sidewalls 24.
- the photosensitive layer 14 and the release layer 12 may be removed concurrently by oxygen plasma. Any sidewall material 24 that remains is removed by mechanical means, CF4 plasma etch or washed off in a liquid base.
- Fig. 5 there is shown in this figure an alternative process of fabricating a nonerodable stencil having openings therein of a size smaller than capable by lithography, per se.
- an underlayer 30 is formed between the substrate 10 and the release layer 12.
- the release layer 12 may be omitted.
- the underlayer 30 is substantially thicker than the photosensitive material 14.
- the underlayer may be an insulator such as polyimide or photoresist.
- the process is modified to anisotropically etch the underlayer 30 to transfer the opening 16 in the layer 14 to the underlayer 30 obtaining the opening 32 therein.
- the underlayer is polyimide
- this etching is done by using O2 plasma.
- the overlying structure is removed by liftoff of the release layer as previously elaborated in conjunction with Fig. 4 description.
- the underlayer 30 defined in this manner will serve as a thick nonerodable mask for etching, for example, deep and extremely narrow trenches in the substrate 10.
- One such trench is shown in Fig. 5 designated by numeral 34.
- the trench 34 will have near perfect vertical walls owing to the enormous thickness of the nonerodable mask.
- a method of reducing lithographic image size that fully satisfies the objects and advantages set forth above.
- This method permits reduction in lithographic image size over and beyond that possible by improved lithographic resolution brought about by lithography tool enhancements.
- this method can be applied universally and for all time to come, to move lithographic image resolution a significant step ahead of improvements due to tool enhancements.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
- The invention relates to a method of reducing lithographic image size for integrated circuit (IC) manufacture. More particularly, it is a method of forming a mask having openings of a size smaller than obtainable by lithography.
- There has been an inexorable advance in IC industry due to the insatiable appetite for scaling down the devices. Scaling device dimensions reduces cost of manufacture while increasing the performance (speed). While this advance can be attributed to new processing techniques such as replacement of wet etching by dry etching (plasma etching, reactive ion etching and ion milling), use of low-resistivity silicides and refractory metals as replacements for high-resistivity polysilicon interconnections, multiple-resists to compensate for wafer surface variations that thwart accurate fine-line lithography, laser and electron-beam processing to purify and reduce defects in materials, nonoptical methods of inspecting line widths and layer-to-layer registration to replace optical methods incapable of measuring these parameters at low-micrometer levels, lithography has been the driving force behind each step forward. Improved lithographic tools such as 1:1 optical projection systems fitted with deep-ultraviolet source and optics, electron-beam, direct-step-on-wafer, and X-ray and ion-beam systems and improved photoresist materials and processes such as multilayer resist utilizing a top resist sensitized to X-ray or electron-beam and bottom straight optical resist layer(s) are some of the components of this driving force.
- Despite this tremendous progress, there remains an ever-growing need for reduction of image sizes over and beyond that offered by enhancements to lithographic tools, materials and processes, per se. However, the prior art has not been able to meet this need.
- The invention precisely satisfies this need for reducing lithographic image sizes by extending lithographic resolution to smaller sizes than capable by lithography.
- In its broadest form, the invention provides a method of reducing the size of a lithographic image by establishing a sidewall on the interior of the opening in the lithographic mask material used to obtain the image. In a specific embodiment, the invention presents a process for making a mask having openings of a size smaller than obtainable by lithography. Starting with a substrate (e.g., semiconductor, insulator or metal), a thin release layer of an insulator material, such as photoresist and silicon dioxide, is formed on the substrate. A thick layer of photosensitive material is then applied. The thick layer is patterned by lithographic means to have openings of a minimum size dictated by limits of lithography. Thereafter, to further reduce the size of the openings, a conformal layer material is applied to the patterned photosensitive layer and the substrate portions exposed by the openings in the patterned layer. The thickness of the conformal layer material is determined by the desired reduction in the size of the openings. For example, for an elongated opening, the reduction in the width of the opening is approximately twice the thickness of the conformal layer. An example of the conformal layer material is SixOy formed by plasma-deposited hexamethyldisilazane (HMDS). By directional reactive ion etching (RIE), the conformal layer is removed from all the horizontal surfaces leaving sidewalls of the conformal layer material on the non-horizontal surfaces corresponding to the openings in the photosensitive material. The release layer exposed by the openings in the photosensitive material is also removed by RIE. The thick photosensitve mask in combination with the sidewalls of the conformal layer material constitute a new mask (stencil) having openings smaller than obtainable by lithography alone. This new mask can be used for a variety of purposes including ion implantation to implant the substrate exposed by the reduced-dimensioned openings therein, as a RIE mask to etch narrow trenches in the substrate, as an oxidation mask to form recessed oxide isolation in the exposed regions of the semiconductor substrate, as a contact or metallization mask to respectively establish narrow dimensioned contacts to or conductors on the substrate, etc. Following such use, the new mask is lifted off the substrate by subjecting the release layer to a wet etchant.
- To form narrow and deep trenches in a semiconductor substrate, the above mask forming process is modified by starting with a semiconductor substrate having thereon a thick insulator layer such as photoresist or polyimide. The new mask as described above is formed on the thick insulator, after which the thick insulator layer is patterned by RIE using the new mask as an RIE mask. Following the liftoff of the release layer, the patterned thick insulator layer on the substrate will serve as a trench RIE mask for etching deep trenches having a width smaller than the lithography limit in the semiconductor material.
- The novel features, process steps and their combination characteristic of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the detailed description which follows in conjunction with the accompanying drawings, wherein:
- Figs. 1-4 are sequential cross-sectional representations of one embodiment of a process for forming a mask/stencil having opening(s) smaller than dictated by lithography limit.
- Fig. 5 is s cross-sectional representation of an extension of the process step sequence illustrated in the preceding figures.
- Now referring to the process steps illustrated in Figs. 1-4, the process is initiated starting with a
substrate 10. Thesubstrate 10 may be any material on which a photoactive layer can be coated and patterned by lithographic techniques. For example, thesubstrate 10 may be a semiconductor material, glass, insulator, primary photosensitive material, metal or a combination thereof. Next, arelease layer 12 is applied to thesubstrate 10. Therelease layer 12 is composed of a material that is easily removable from thesubstrate 10. Such removal is made by wet chemical etchants or by oxygen ashing. Since the basic function ofrelease layer 12 is to facilitate easy removal of itself, any subsequently formed layers/structures thereon are correspondingly removed as well. Examples of the material suitable for forminglayer 12 include photoresist. In one example, AZ 1350J (trademark of American Hoechst Corporation) photoresist material is applied by spin coating, followed by baking at a temperature of about 200-250°C for about 30-60 mins. to obtain arelease layer 12 of about 200-1000 A ° thickness. Below about 200 Å thickness, the release layer would be too thin to reliably coat thesubstrate 10. - Continuing with the present process, after forming the
release layer 12, athick imaging layer 14 of a photosensitive material is applied, for example, by spin-coating as illustrated in Fig. 1. Theimaging layer 14 is of a sufficient thickness in the range 0.8-3 microns. An example of the material oflayer 14 is AZ 1350J photoresist. After coating the photosensitive material, it is patterned in a desired pattern by pattern-exposing in a lithographic tool, developed, rinsed and dried. For simplicity of illustration, in Fig. 1 asingle opening 16 having a lateral dimension A is shown in thelayer 14 having a substantiallyhorizontal surface 18 and substantially vertical surfaces 20-20. The dimension A may be the smallest image size that is obtainable by lithography. In other words, the width A may be the smallest dimension that is achievable by pushing lithography (which includes x-ray, electron-beam, etc.) to its highest resolution limit. Next, the patterned photosensitive layer is subjected to a hardening process step to thermally stabilize thelayer 14. Deep ultraviolet exposure or heat treatment at a temperature of about 200-250°C for about 1-2 mins. may be used for hardening. Another method of hardening thelayer 14 is by subjecting it to a halogen gas plasma. This hardening step is needed for conventional photoresists, lest the photosensitivematerial constituting layer 14 may bubble up, melt and flow or otherwise get degraded during the deposition of subsequent layers thereon. - The next step in the present process is establishing sidewalls on the vertical surfaces 20-20 to reduce the lateral dimension A of the opening 16 beyond that achievable by lithography alone. Sidewall technology is known to the prior art as exemplified by the following patents. U.S. pat. no. 4,209,349 assigned to the present assignee, utilizes sidewall technology for forming small openings in a mask. According to this method, first insulator regions are formed on a substrate so that horizontal and vertical surfaces are obtained. A second insulator layer is applied thereon of a material different from that of the first layer, and is subjected to RIE in such a manner that the horizontal regions of the second insulator are removed, with merely very narrow regions of this layer remaining on the vertical surface regions of the first insulator, and the respective regions of the substrate, respectively. Subsequently, the exposed substrate regions are thermally oxidized, and for finally forming the desired mask openings the regions of the second insulator layer there are removed. U.S. pat. no. 3,358,340 describes a method of making submicron devices using sidewall image transfer. A conductive film of submicron thickness is deposited across a vertical step between adjacent surfaces of an isolation, and subsequently vertically etched until there remains only part of the conductive film which is adjacent to the vertical step. The remaining isolation not covered by the conductor is removed, thus obtaining a submicron-wide gate of an MOS field effect transistor. U.S. pat. nos. 4,419,809 and 4,419,810 assigned to the present assignee disclose methods of making self-aligned field effect transistors using sidewall to define narrow gates. U.S. pat. no. 4,462,846 discloses use of sidewalls to minimize birds beak extensions of recessed oxide isolation regions. U.S. pat. no. 4,502,914 assigned to the present assignee describes a method of making submicron structures by providing a polymeric material structure having vertical walls, the latter serving to make sidewall structure of submicron width. The sidewall structures are directly used as masks. For negative lithography, another layer is applied over the side-wall structures, which is partly removed until the peaks of the sidewall structures are exposed. Subsequently, the sidewall structures themselves are removed and the resulting opening is used as a mask opening for fabricating integrated circuit devices.
- To reduce the size of the
opening 16 in thelayer 14, referring to Fig. 2, aconformal layer 22 is formed over the patternedphotosensitive layer 14 and the portion of therelease layer 12 exposed by theopening 16 therein. The conformal layer material may be polysilicon, SixOy, silicon dioxide, silicon nitride, silicon oxynitride or a combination thereof. In general, theconformal layer 22 may be any material which can be deposited at a temperature low enough as to not cause degradation of the patternedphotosensitive layer 14. A preferred material for forminglayer 22 is SixOy obtained by hexamethyldisilazane (HMDS) plasma deposition. - Typically, the
layer 22 is formed by mounting the substrate with the structure of Fig. 1 in a plasma deposition system, introducing liquid HMDS into the process chamber and generating the necessary electric field therein which transforms the liquid HMDS into a HMDS plasma. The HMDS plasma will deposit on the structure of Fig. 1 obtaining a conformal anduniform layer 22 of plasma-deposited HMDS having the composition SixOy. The thickness B oflayer 22 is determined by the desired reduction in the lithographic image size in thephotosensitive layer 14. Typically, for very large scale integrated circuit fabrication, the thickness oflayer 22 is in the range 0.01 - 0.6 microns. The lower limit for the thickness oflayer 22 is dictated by the requirements of good step coverage associated with the substantiallyvertical wall profile 20 inlayer 14 and viability of thelayer 22 as a thin film. The upper limit for the thickness oflayer 22 is determined by the desired percentage reduction in the size of theopening 16 in thelayer 14. The percentage reduction in the opening size is governed by the factor 2B/A. In other words, if the size of the opening is 3 microns, in order to achieve a 66.6% reduction in the size of the hole 16 (or an actual reduction of the hole size to 1 micron), a 1 micronthick HMDS layer 22 is deposited. After forming theconformal layer 22, next by anisotropic etching it is removed from all the substantially horizontal surfaces leaving it only on the substantially vertical surfaces oflayer 14. RIE may be accomplished by a halogen-containing etchant gas. One suitable etchant gas is CF4. The resulting structure will be as shown in Fig. 3 where the unetched portions oflayer 22 are designated by 24, now serving as sidewalls on thevertical surfaces 20 oflayer 14. Due to the establishment of thesidewalls 24 on the interior of the vertical surfaces of the opening, the size of theopening 16 is reduced to a new dimension designated as C in Fig. 3. The relationship between the parameters A, B and C is given by: C = A - 2B. - Following the establishment of the
sidewalls 24 on the vertical surfaces of theopening 16, the portion of therelease layer 12 exposed by the reduced-size opening 16 is removed by RIE using, for example, either the same etchant species which facilitated removal oflayer 22 from the horizontal surfaces oflayer 14 or O₂ plasma. - The photosensitive mask in combination with the
sidewalls 24 fabricated in this manner constitutes a new mask (or stencil) having openings of a substantially reduced dimension than obtainable by lithography alone. The new mask serves a variety of purposes. As illustrated in Fig. 4, for example, it may be used as an ion implantation mask to implant an extremely narrow/small region 26 of thesubstrate 10. Another application of the new mask is as an etch mask to etch extremely narrow deep/shallow trenches in thesubstrate 10. Yet another application is to grow a recessed isolation oxide free of bird's beak and bird's head of a width essentially equal to the dimension C by subjecting the substrate and the overlying stencil structure to a low temperature oxidation. A further use of the new mask is as a contact (liftoff) mask for establishing highly localized electrical contacts to the substrate. Another use of the mask is to form narrow conductor or insulator lines of width C on the substrate. - Once the intended use of the new mask is complete, it is removed from the
substrate 10 by taking advantage of therelease layer 12. By subjecting therelease layer 12 to a suitable etchant for example, a hot oxidizing acid such as nitric acid, sulphuric acid, or hot phenol it is lifted off the surface of the substrate thereby removing theoverlying layer 14 and its associatedsidewalls 24. Alternatively, thephotosensitive layer 14 and therelease layer 12 may be removed concurrently by oxygen plasma. Anysidewall material 24 that remains is removed by mechanical means, CF4 plasma etch or washed off in a liquid base. - Turning to Fig. 5, there is shown in this figure an alternative process of fabricating a nonerodable stencil having openings therein of a size smaller than capable by lithography, per se. In this process, an
underlayer 30 is formed between thesubstrate 10 and therelease layer 12. (In this embodiment, therelease layer 12 may be omitted.) Theunderlayer 30 is substantially thicker than thephotosensitive material 14. For example, when the substrate material is a semiconductor, the underlayer may be an insulator such as polyimide or photoresist. After forming the stencil precursor comprised of therelease layer 12 and thephotosensitive layer 14 having sidewalls 24 in the manner described above in conjunction with Figs. 1-4, the process is modified to anisotropically etch theunderlayer 30 to transfer theopening 16 in thelayer 14 to theunderlayer 30 obtaining theopening 32 therein. When the underlayer is polyimide, this etching is done by using O2 plasma. Following the definition of thenonerodable mask 30, the overlying structure is removed by liftoff of the release layer as previously elaborated in conjunction with Fig. 4 description. Theunderlayer 30 defined in this manner will serve as a thick nonerodable mask for etching, for example, deep and extremely narrow trenches in thesubstrate 10. One such trench is shown in Fig. 5 designated bynumeral 34. Thetrench 34 will have near perfect vertical walls owing to the enormous thickness of the nonerodable mask. - Thus, there has been provided in accordance with the invention, a method of reducing lithographic image size that fully satisfies the objects and advantages set forth above. This method permits reduction in lithographic image size over and beyond that possible by improved lithographic resolution brought about by lithography tool enhancements. In other words, this method can be applied universally and for all time to come, to move lithographic image resolution a significant step ahead of improvements due to tool enhancements.
- While the invention has been described in conjunction with preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is, therefore, contemplated that the appended claims will embrace any such alternatives, modifications and variations as fall within the true scope and spirit of the invention.
Claims (30)
providing a substrate coated with a photosensitive material;
patterning the photosensitive material to form an opening therein, said opening having substantially vertical walls and minimum size dictated by resolution limit of lithography;
forming a conformal layer of a material on the resulting structure including said vertical walls; and
anisotropically etching said conformal layer to provide said conformal layer material on said vertical walls whereby said size of said opening is reduced.
forming on a substrate a mask material having at least one opening of minimum size A determined by the resolution limit of lithographic exposure tooling, said opening having substantially vertical interior walls; and
establishing sidewalls of a material of a thickness B on said walls, whereby the new size C of said opening is at least approximately A-2B.
forming a conformal layer of said sidewall material; and
anisotropically etching to remove said sidewall material from everywhere except the walls of said opening.
providing a substrate covered with a relatively thick layer of a first material;
coating said first material with a photosensitive layer having an opening of a minimum size dictated by the resolution limit of lithography, said opening having substantially vertical surfaces;
depositing a conformal layer of an insulator material on said first material including said vertical surfaces and on the substrate exposed by said opening;
anisotropically etching to remove said conformal layer from everywhere except said walls of said opening, thereby reducing the size of said opening by approximately twice the thickness of said conformal layer; and
anisotropically etching said first material layer to transfer thereto an image of said opening of reduced size in said photosensitive layer and transform said first material layer into a mask for said substrate.
a substrate of a first material;
a layer of a second material having at least one opening formed on said substrate, said opening having substantially vertical walls; and
sidewalls of a third material of a common and uniform thickness formed on all of said vertical walls, decreasing the size of said opening.
a rigid layer of a first material having therein at least one opening of linear dimension A, said opening having substantially vertical walls; and
a sidewall of a second material of a common and uniform thickness B established on all of said walls,
whereby said dimension A of said opening is reduced.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/924,223 US4707218A (en) | 1986-10-28 | 1986-10-28 | Lithographic image size reduction |
US924223 | 1986-10-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0265638A2 true EP0265638A2 (en) | 1988-05-04 |
EP0265638A3 EP0265638A3 (en) | 1988-10-05 |
Family
ID=25449914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87113097A Ceased EP0265638A3 (en) | 1986-10-28 | 1987-09-08 | Lithographic image size reduction |
Country Status (4)
Country | Link |
---|---|
US (1) | US4707218A (en) |
EP (1) | EP0265638A3 (en) |
JP (1) | JP2553078B2 (en) |
CA (1) | CA1250669A (en) |
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US6077773A (en) * | 1995-09-14 | 2000-06-20 | Advanced Micro Devices, Inc. | Damascene process for reduced feature size |
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Also Published As
Publication number | Publication date |
---|---|
EP0265638A3 (en) | 1988-10-05 |
JPS63116430A (en) | 1988-05-20 |
CA1250669A (en) | 1989-02-28 |
US4707218A (en) | 1987-11-17 |
CA1260627C (en) | 1989-09-26 |
JP2553078B2 (en) | 1996-11-13 |
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