EP0242468A1 - Flüssigkristallanzeigeeinheit und Verfahren zum Steuern dieser Einheit - Google Patents

Flüssigkristallanzeigeeinheit und Verfahren zum Steuern dieser Einheit Download PDF

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Publication number
EP0242468A1
EP0242468A1 EP86303037A EP86303037A EP0242468A1 EP 0242468 A1 EP0242468 A1 EP 0242468A1 EP 86303037 A EP86303037 A EP 86303037A EP 86303037 A EP86303037 A EP 86303037A EP 0242468 A1 EP0242468 A1 EP 0242468A1
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EP
European Patent Office
Prior art keywords
liquid crystal
display device
crystal display
signal
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86303037A
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English (en)
French (fr)
Inventor
Mitsuyoshi Hara
Takamasa Harada
Kenichi Kondo
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Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to EP86303037A priority Critical patent/EP0242468A1/de
Publication of EP0242468A1 publication Critical patent/EP0242468A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • This invention relates to liquid crystal display devices and methods of driving same.
  • Liquid crystal display devices of the dot matrix type have drawn increasing attention recently, and the size of the display surface of such devices and the number of scanning lines have been increased.
  • One conventional dynamic driving system for a liquid crystal display device is an A.C. driving method which inverts the polarity of the voltage applied to a liquid crystal material between an electrode selection time and an electrode non-selection time, whenever all the scanning lines are scanned once. This will be referred to hereinafter as the "two-frame A.C. driving system".
  • Such a driving system is described, for example, in "Nikkei Electronics", 1980, August 18, pp 150 - 174.
  • Figure 7 shows a conventional common electrode driving circuit for a liquid crystal display device.
  • a shift register 27 sequentially shifts a line sequential scanning signal by a clock signal CK1 which is in synchronism with a common electrode scanning speed.
  • a latch circuit 28 latches the signal from the shift register 27 in synchronism with the clock signal CK2 and supplies a driving voltage from a voltage generation circuit 30 to common electrodes CM',, CM' 2 , ..., CM' n of the liquid crystal display device through an output gate circuit 29.
  • the driving voltage generation circuit 30 described above receives liquid crystal driving voltages V o p, (1 - )V op , V op and zero (0) potential supplied from a power source (not shown), through analog switches 31 a, 31b, 31c, 31d such as transmission gates, respectively, and produces an output pair from the analog switches 31a, 31b which receive the driving voltage V a p and the zero potential and also produces an output pair from the analog switches 31 c, 31 c which receive the driving voltages (1 - )Vp and V op . These output pairs are fed to the output gate circuit 29.
  • a polarity inversion signal is applied directly and through an inverter 33 to control terminals of the pair of analog switches 31a, 31b and the pair of analog switches 31c, 31d of the driving voltage generation circuit 30 so as to generate zero potential and the driving voltages (1 )V op or V oP and V op from the driving voltage generation circuit 30.
  • the output gate circuit 29 has a pair of two analog switches 32a, 32b , for each common electrode and each pair receives the voltages from the driving voltage generation circuit 30.
  • the analog switches 32a directly receive the output signal from the latch circuit 28, and the analog switches 32b receive the output signal from the latch circuit 28 after inversion by an inverter 16.
  • Figure 8 shows a conventional segment electrode driving circuit of the liquid crystal display device.
  • a shift register 38 receives a data signal and a segment electrode scanning timing, that is, a sub-scanning clock signal CK 2 and shifts the data signal by the clock signal CK 2 .
  • a latch circuit 39 latches the signal from the shift register 38 in synchronism with the clock signal CK 2 and supplies the driving voltage from a driving voltage generation circuit 36 to segment electrodes SG' 1 , SG' ... SG' m of the liquid crystal display device through the output gate circuit 37.
  • the driving voltage generation circuit 36 receives liquid crystal driving voltages V o p, (1 - )V op and V op and a zero potential supplied from a power source (not shown), through analog switches 36 a, 36b, 36c 36d such as transmission gates, and produces an output pair from the analog switches 36a, 36b that receive the driving voltage V op and the zero potential, and produces an output pair from the analog switches 36c, 36d which receive the driving voltages (1 - )V op and V op . These output pairs are fed to the output gate circuit 37.
  • a polarity inversion signal is applied directly and through an inverter 34 to the control terminals of the pairs of analog swtiches 36a, 36b, and 36c, 36d of the driving voltage generation circuit 36 so as to generate the zero potential and the driving voltage V op or the driving voltages V o p and (1 - )V op .
  • the output gate circuit consists of a pair of analog switches 37a, 37b for each segment electrode. Each pair receives voltages from the driving voltage generation circuit 36.
  • the output signal from the latch circuit 39 is directly applied to each analog switch 37a and each analog switch 37b receives the the output of the latch circuit 39 after inversion by an inverter 35.
  • the driving voltage generation circuit 30 When the polarity inversion signal is at low level, the driving voltage generation circuit 30 generates the driving voltages V op and V op so that the driving voltage V op is applied to the common electrode CM', whilst the driving voltage a V op to the other common electrodes.
  • the driving voltage generation circuit 36 outputs the zero potential and the driving voltage V op when the polarity inversion signal is at low level.
  • the segment When the data signal from the latch circuit 39 is at high level, the segment is in the selection state and output zero potential.
  • the data signal is at low level, it outputs the voltage VoP.
  • Figure 9 shows the case where all the data signals are ON and the output waveform is of the common electrode CM',.
  • the voltage generation circuit 30 ( Figure 7) generates the zero potential and the driving voltage (1 - .)Vop and the voltage generation circuit 36 ( Figure 8) generates the driving voltages V oP and (1 - )V op . Therefore, the polarity of the impressed voltage applied to the liquid crystal material of the liquid crystal display device (the potential difference between the common electrode output waveform and the segment electrode output waveform of a pixel) is inverted depending upon the high and low levels of the polarity inversion signal.
  • Figure 10 shows driving waveforms in the aforementioned two frame A.C. driving system in the case where the number of scanning lines (i.e. the number of common electrodes) is 12.
  • Reference letter H represents the output waveform of the common electrode and reference letter I shows the output waveform of segment electrodes when all of them are ON.
  • Reference letter J representes the output waveform when all the segment electrodes are OFF and reference letter K shows the output waveform when ON and OFF appear alternately.
  • Reference letter L represents the output waveform of the impressed voltage when all the segment electrodes are ON and reference letter M shows the waveform of the liquid crystal impressed voltage when all the segment electrodes are OFF.
  • Reference letter N represents the waveform of the impressed voltage when the segment electrodes are ON and OFF alternately.
  • FIG. 11 shows the relationship between the frequency of the voltage applied to the liquid crystal material and the threshold voltage of the electro-optical characteristics of the liquid crystal material.
  • the threshold voltage is low at low frequency and high at high frequency. Therefore, even if the display device is driven by the same voltage value, the cross-talk phenomenon occurs partly in the case of particular display states.
  • a first solution is to increase the frame frequency. Since there is a limit to the driving frequency of a liquid crystal controller IC, however, it is not possible to increase the frame frequency to such an extent as to extinguish the cross-talk. Another problem is that current consumption becomes relatively large because the current consumption of the liquid crystal material and the CMOS circuit is determined by charge-discharge current at the time of switching.
  • a second solution is to reduce the resistance of a transparent conductive film of which the electrodes of the liquid crystal display device are formed, but this does not overcome the problem that transmissivity drops if the film thickness is incre-sed in order to reduce its resistance.
  • a third solution is to develop liquid crystal materials having less dependency upon the driving waveform frequency, but such liquid crystal materials have not yet been produced.
  • the present invention seeks to provide a liquid crystal display device free from non-uniform display that is caused by cross-talk.
  • a liquid crystal display device arranged to be dynamically driven characterised by means for generating a polarity inversion signal at a frequency at or adjacent a predetermined value in any display state.
  • Preferably further means are provided for inverting the polarity of the voltage applied to liquid crystal material for each scanning frame.
  • the first-mentioned means comprises frequency divider means settable to a predetermined division ratio and means for modulating a high frequency signal in dependence upon the division ratio to produce said inversion signal.
  • the divider means may be selectively settable.
  • a method of dynamically driving a liquid crystal display device characterised by generating a polarity inversion signal at a frequency at or adjacent a predetermined value in any display state.
  • FIG. 1 is a perspective view of a liquid crystal display panel of a liquid crystal display device according to the present invention.
  • Substrates 1,2 constitute a cell of a liquid crystal display panel.
  • the substrates 1,2 include common electrodes 1a, 2a respectively which are disposed on the surface of electrically insulating, transparent sheets such as glass, and an insulating film such as, for example, polyimide, Teflon (Trade Mark), etc. is formed on each sheet surface by printing, dipping, etc., and is then rubbed unidirectionally to form uniaxially orientated films 1b,2b, respectively.
  • the substrates 1,2 are disposed parallel to one another in such a manner that their orientated films are opposed with a gap of from several to some dozens of microns between them.
  • a liquid crystal material 5 is charged into this gap.
  • a pair of polariser plates 3,4 are disposed on the outer surfaces of the substrates 1,2 so that the state of orientation of the molecules of the liquid crystal material can be displayed in
  • the pair of polariser plates 3,4 are arranged in such a fashion that their axes of polarisation are substantially at right angles or parallel to each other, and the rubbing directions are substantially at right angles or parallel to the axes of polarisation.
  • the present invention is applicable to a liquid crystal display device wherein the liquid crystal material is less than 10 microns thick, a twist angle is greater than 180° but less than 360°, and the ratio dip is from 0.5 to 0.95 (d: thickness of liquid crystal layer, p: rotation pitch of twist angle of liquid crystal molecules), such as disclosed in Published European Patent Application No. 131,216.
  • FIG 2 is a block diagram of a liquid crystal display device according to the present invention using the liquid crystal display panel of Figure 1.
  • the reference numeral 6 represents the liquid crystal display panel, the common electrodes and the segment electrodes of which are connected to a common electrode driving circuit 7 and a segment electrode driving circuit 8, respectively.
  • FIG. 3 shows the common electrode driving circuit 7 in detail.
  • a shift register 9 sequentially shifts a line sequential scanning signal in synchronism with a common electrode scanning speed determined by a clock signal CK 2 .
  • a latch circuit latches the signal from the shift register 9 in synchronism with the clock signal, and supplies a driving voltage from a driving voltage generation circuit 11 to common electrodes CM,, CM 2 ... CM n to an output gate circuit 12.
  • the driving voltage generation circuit 11 receives liquid crystal driving voltages V o p, (1 - )V op , V op and zero potential supplied from a power source, (not shown), through analog switches 11a, 11b, 11c, 11d, such as transmission gates, and supplies an output pair from the analog switches 11 a, 11 b, that receive the driving voltage Vp and the zero potential and an output pair from the analog switches 11c, 11d, that receive the driving voltages (1 - )V op and V op .
  • the output pairs are fed to the output gate circuit 12.
  • a 1/N frequency divider 13 divides the frequency of a clock signal CK, and outputs a signal having a frequency which is from 6 to 7 times the frequency of a polarity inversion signal.
  • An exclusive-OR gate 14 receives the signal from the frequency divider 13 and the polarity inversion signal, inverts the former when the polarity inversion signal is applied thereto, and applies, in turn, a signal to the control terminals of the pairs of analog switches 11 a, 11b and 11c, 11 d directly and through an inverter 15. respectively, so that the driving voltage generation circuit 11 generates the zero potential and the driving voltage (1 - )V op or the driving voltage V op and V op .
  • the output gate circuit 12 consists of a pair of analog switches 12a, 12b corresponding to each common electrode and receives voltages from the driving voltage circuit 11.
  • the analog switch 12a receives directly the output signal from the latch circuit 10, while the other analog switch 12b receives the output signal from the latch circuit 10 after inversion by an inverter 16.
  • FIG. 4 shows the segment electrode driving circuit 8 in detail.
  • a shift register 18 receives a data signal and segment electrode scanning timing, that is, a sub-scanning clock signal CK 2 , to shift the data signal by the clock signal CK 2 .
  • a latch circuit 19 latches the signal from the shift register 18 in synchronism with the clock signal CK 2 , and supplies driving voltages from a driving voltage generation circuit 20 to segment electrodes SG,, SG 2 ... SG m to an output gate circuit 21.
  • the driving voltage generation circuit 20 receives liquid crystal driving voltages V o p, (1 - )V op , V op and zero potential supplied from a power source (not shown), through analog switches 20a, 20b, 20 c, 20d such as transmission gates, respectively. Output pairs from the analog switches 20a and 20b that receive the driving voltage V op and the zero potential, and output pairs from the analog switches 20c and 20d, that receive the driving voltages (1 - ). V o pand V op are fed to the output gate circuit 21.
  • a 1/N frequency divider 22 and an exclusive-OR gate 23 operate in the same way as the frequency divider 13 and the exclusive-OR gate 14 shown in Figure 3, respectively.
  • the signal phase from the frequency divider 22 is inverted and is applied directly and through an inverter 24 to the pairs of analog switches 20a, 20b and 20c, 20d of the driving voltage generation circuit 20 which thus produces the zero potential and the driving signal V op or the driving voltages V op and (1 - )V op .
  • the output gate circuit 21 consists of a pair of analog switches 21a, 21b for each segment electrode. Each pair of analog switches receives voltages from the driving voltage generation circuit 20.
  • the output signal from the latch circuit 19 is directly applied to one of the analog switches 21a which the other analog switch 21b receives the output signal from the latter circuit after inversion by the inverter 25.
  • Figure 5 shows the case where the number of scanning lines is 12 and the output frequency of the frequency divider 13 shown in Figure 3 and the frequency divider 22 shown in Figure 4 is 6 times the polarity inversion signal frequency.
  • the line segment scanning signal When the line segment scanning signal is outputted, it is latched by the latch circuit 10 through the shift register 9, whereby the first common electrode CM, is in a selection state with the other common electrodes CM2 ... CM n being in the non-selection state.
  • the clock signal CK is frequency divided by the frequency divider 13 and a signal having a frequency which is 6 times the polarity inversion signal frequency is produced and applied to the exclusive-OR gate 14.
  • the phase of the signal is inverted when the polarity inversion signal is inputted, and is applied to the driving voltage generation circuit 11. Due to this signal, the voltages tabulated below are outputted to the common electrodes CM n :
  • Figure 5 shows the common electrode output waveform that is outputted in the manner described above.
  • the segment electrode output waveform shown in Figure 5 represents the case where all the display pixels are ON.
  • Figure 6 shows an example of the driving waveform in the liquid crystal display device.
  • Figure 6 illustrates the case where the number of common electrodes is 12.
  • Reference letter A represents a common electrode output waveform
  • reference letter B is a segment electrode output waveform when the data signals are all ON
  • reference letter C is a segment electrode output waveform at the time all the data signals are OFF
  • reference letter D is a segment electrode output waveform when ON and OFF data signals apear alternately
  • reference letter E is a liquid crystal impressed voltage waveform at the time all the segment electrodes are ON
  • reference letter F is a liquid crystal impressed voltage waveform at the time all the segment electrodes are OFF
  • reference letter G is a liquid crystal impressed voltage waveform when the segment electrodes are ON and OFF alternately.
  • Figure 12 is a detailed block diagram showing an embodiment of the circuit of a liquid crystal display device according to the present invention.
  • variable counters 40,41 divide the frequency of the clock signal CK
  • a flip-flop circuit 42 divides the output of the variable counter 41 by 2
  • an OR circuit or an exclusive-OR gate 43 receives the output of the flip-flop circuit 42 and a polarity inversion signal M.
  • Reference numerals 20,21,11 and 12 represent a segment side driving voltage generation circuit, a segment electrode driving circuit, a common side driving voltage generation circuit and a common electrode driving circuit respectively.
  • the setting values of the variable counters 40, 41 are determined by setting switches 55 to 62 ON or OFF.
  • a bias voltage supplying circuit 80 comprises resistors 71 to 75 connected in series and the driving voltage (bias voltage) is taken from connecting points between each pair of resistors.
  • the operation of the circuit shown in Figure 12 will now be explained.
  • the switches 56 and 59 are changed to ON so that the variable counters 40 and 41 have setting values of 1/3 and 1/2, respectively.
  • the clock signal CK is divided into 1/3 through the variable counter 40 and the divided signal is further divided by 2 through the variable counter 41.
  • the output signal of the variable counter 41 is furthermore divided by 2 by the flip-flop circuit 42 and is changed into a rectangular wave signal with a duty ratio 1:1.
  • the resulting output 01 enters one terminal of the exclusive-OR gate 43 and the plurality inversion signal M is received at the other terminal. Therefore, the output Q1 of the flip-flop 42 has its polarity inverted for each frame and operates as a control signal for the segment side driving voltage generation circuit 20 and the common side driving voltage generation circuit 11.
  • the segment side and common side driving voltage generation circuits 20, 11 are formed of transmission gates 63 to 66 and 67 to 70, respectively.
  • the output of the exclusive-OR gate 43 is 1
  • the states of transistors 63, 65, 67, 69 are ON, so that the driving voltage is V o p and (1 - 0.)VoPare applied to the segment electrode driving circuit 21, and zero potential and the driving voltage (1 - )V op are applied to the common electrode driving circuit 12.
  • the output of the exclusive-OR gate 43 is 0 the states of the transmission gates 64.
  • the segment electrode driving circuit 21 and the common electrode driving circuit 12 are formed by transmission gates 76 to 79, the transmission gates being changed by 1 or 0 by the SEG signal and the COM signal, so that the transmission gates produce ON or OFF driving signals.
  • the exclusive-OR gate 43 inverts the oututs of the driving voltage generating circuits 20, 11 by the high frequency signal Q1 which is 1/N x the frequency of the clock signal CK, and inverts for each frame by the polarity inversion signal M.
  • a driving voltage which has a frequency near a predetermined value and the polarity of which is inverted for each frame may be applied to any part of the picture element.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP86303037A 1986-04-22 1986-04-22 Flüssigkristallanzeigeeinheit und Verfahren zum Steuern dieser Einheit Withdrawn EP0242468A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP86303037A EP0242468A1 (de) 1986-04-22 1986-04-22 Flüssigkristallanzeigeeinheit und Verfahren zum Steuern dieser Einheit

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Application Number Priority Date Filing Date Title
EP86303037A EP0242468A1 (de) 1986-04-22 1986-04-22 Flüssigkristallanzeigeeinheit und Verfahren zum Steuern dieser Einheit

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EP0242468A1 true EP0242468A1 (de) 1987-10-28

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454470A2 (de) * 1990-04-25 1991-10-30 Sharp Kabushiki Kaisha Verfahren und Einrichtung zum Steuern eines Anzeigegerätes
EP0479896A1 (de) * 1989-06-30 1992-04-15 Poqet Computer Corp Stromversorgung und abtastverfahren für flüssigkristallanzeige.
EP0726558A1 (de) * 1995-02-11 1996-08-14 Samsung Electronics Co., Ltd. Treiberschaltung für eine Flüssigkristallanzeige mit Dünnfilmtransistoren
EP0974952A1 (de) * 1998-02-09 2000-01-26 Seiko Epson Corporation Elektrooptische vorrichtung und verfahren zu ihrer steuerung, flüssigkristallvorrichtung und verfahren zu ihrer steuerung, treiberschaltung für elektrooptische vorrichtung und elektronisches gerät
DE4240552B4 (de) * 1991-12-03 2006-04-20 Rohm Co. Ltd. Anzeigevorrichtung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2075738A (en) * 1980-05-02 1981-11-18 Hitachi Ltd Driving guest-host type phase transition liquid crystal matrix panel
EP0149899A2 (de) * 1983-12-09 1985-07-31 Seiko Instruments Inc. Flüssigkristallanzeigeeinrichtung
EP0173158A2 (de) * 1984-08-20 1986-03-05 Hitachi, Ltd. Flüssigkristallanzeigeeinheit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2075738A (en) * 1980-05-02 1981-11-18 Hitachi Ltd Driving guest-host type phase transition liquid crystal matrix panel
EP0149899A2 (de) * 1983-12-09 1985-07-31 Seiko Instruments Inc. Flüssigkristallanzeigeeinrichtung
EP0173158A2 (de) * 1984-08-20 1986-03-05 Hitachi, Ltd. Flüssigkristallanzeigeeinheit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0479896A1 (de) * 1989-06-30 1992-04-15 Poqet Computer Corp Stromversorgung und abtastverfahren für flüssigkristallanzeige.
EP0479896A4 (en) * 1989-06-30 1993-03-03 Poqet Computer Corporation Power system and scan method for liquid crystal display
EP0454470A2 (de) * 1990-04-25 1991-10-30 Sharp Kabushiki Kaisha Verfahren und Einrichtung zum Steuern eines Anzeigegerätes
EP0454470A3 (en) * 1990-04-25 1992-04-01 Sharp Corporation A driving method and a driving device for a display device
US5206631A (en) * 1990-04-25 1993-04-27 Sharp Kabushiki Kaisha Method and apparatus for driving a capacitive flat matrix display panel
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