EP0188956B1 - Circuit de sélection de données pour mémoire morte à CMOS - Google Patents

Circuit de sélection de données pour mémoire morte à CMOS Download PDF

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Publication number
EP0188956B1
EP0188956B1 EP85402564A EP85402564A EP0188956B1 EP 0188956 B1 EP0188956 B1 EP 0188956B1 EP 85402564 A EP85402564 A EP 85402564A EP 85402564 A EP85402564 A EP 85402564A EP 0188956 B1 EP0188956 B1 EP 0188956B1
Authority
EP
European Patent Office
Prior art keywords
line
column
bit lines
channel
column line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP85402564A
Other languages
German (de)
English (en)
Other versions
EP0188956A2 (fr
EP0188956A3 (en
Inventor
Harold L. Davis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of EP0188956A2 publication Critical patent/EP0188956A2/fr
Publication of EP0188956A3 publication Critical patent/EP0188956A3/en
Application granted granted Critical
Publication of EP0188956B1 publication Critical patent/EP0188956B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/126—Virtual ground arrays

Definitions

  • the field of the invention is that of CMOS integrated circuit ROMs.
  • the memory matrix comprises a set of column lines connected through a pair of data storage transistors to adjacent bit lines.
  • the column line is pulled to ground, thus creating a potential path through the intermediate transistors from the bit lines, which remain near five volts, to ground at the column line.
  • the column decode line outside the memory matrix controls three gates per column - the column line in question and pass transistors connecting the two adjacent bit lines with corresponding data lines.
  • the use of the NMOS technology means that the full value of VCC cannot be used on the bit lines because there is a threshold drop on the pass transistor between the bit line and the data line.
  • the value of the voltage on the bit lines may vary across the chip as a result of Vt variation.
  • the invention relates to a data selection circuit adapted for a CMOS ROM, in which P-channel pass transistors on the bit lines have gates that are connected directly to the intermediate column line.
  • the column decode line then controls only one transistor per column line - that on the column line.
  • the initially off P-channel pass transistors create a path that will pass the full voltage value of VCC, which is uniform across the chip.
  • CMOS ROM would need an inverter to invert the signal on the column decoder line and a second line paralleling the column decode line to control the gates of the P-channel pass transistors on the bit lines. There would, therefore, be twice as many lines in the controlling circuit.
  • Figure 1 illustrates a data select circuit in the prior art.
  • Figure 2 illustrates a straightforward circuit employing P-channel pass transistors.
  • FIG. 3 illustrates an embodiment of the invention.
  • column line 110 is bracketed by bit lines 112 and 114, connected by data storage transistors 102 and 104 is shown in this figure.
  • column decode line 117 which controls pull-down transistor 120 and pass transistors 122 and 124.
  • Transistor 120 pulls down the column line to ground and transistors 122 and 124 create a path between data lines 113 and 115 and bit lines 112 and 114 respectively. Since a voltage no higher than VCC minus the Vt of the pass transistor can pass between the bit lines and their data lines, this forces the bit lines to be precharged to this lower voltage level instead of all the way to VCC, the preferred CMOS level.
  • CMOS circuit which allows bit lines to be fully precharged to VCC by using P-channel pass gates is shown, with similar elements indicated by the same numeral.
  • the column line and the two bit lines are all precharged to VCC by conventional means that form no part of this invention.
  • the P-channel pass gates 132 and 134 which have replaced the N-channel pass gates 122 and 124 from Figure 1 may now pass the full VCC from bit lines to data lines, but their gates must be driven by a new signal 127, the inversion of 117.
  • FIG. 3 there is shown an embodiment of the invention in which, again, similar elements are indicated by the same numeral.
  • the function of the circuit is the same as in Figure 2, but the P-channel pass gates are driven, not by a complement column decode signal, but by the column line 110.
  • the column line 110 and its pulldown transistor 120 are being used both for their column line functions and as a dynamic inverter to locally create the necessary column decode line inversion to drive the P-channel pass gates, thus doing away with the need for the complement column decode line 127 shown in Figure 2.
  • the advantages of the embodiment shown in Figure 3 over the circuits in Figures 1 and 2 are as follows: Unlike Figure 1, the invention allows bit lines to be precharged completely to VCC by using P-channel pass gates instead of N-channel. This will result in uniform bit-line precharge voltage across the chip, in contrast to the prior art, in which the threshold will vary.
  • the invention has less capacitance on line 117 because only one transistor is connected per column line instead of three. In large chips, where a decode line may control more than a hundred columns, this reduction is significant.
  • the invention does not require the complement column decode line to be generated and run to the P-channel pass gates.
  • the invention places the pass gates, which are of negligible capacitance separately but of sizeable capacitance as a group, separately on each column line. Since the capacitance of the column line is much higher than that of the two pass gates, the effect is also negligible upon the operation of the column line.
  • pass transisitors 132' and 134' in the embodiment of Figure 3 are wider, so that there is lower impedance (or better charge transfer) to the data line so that the quality of the signal to the sense amplifier or other sensing device is improved.

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  • Read Only Memory (AREA)
  • Electronic Switches (AREA)

Claims (1)

  1. Circuit de sélection de données pour une mémoire CMOS en circuit intégré ayant une ligne colonne (110) comprise entre une première et une seconde ligne de bit (112,114) et ayant au moins un couple de transistors de stockage de données (102,104) reliés respectivement entre la dite ligne colonne et la dite première ligne de bit, et entre la dite ligne colonne et la dite seconde ligne de bit, chaque couple du dit ensemble d'au moins un couple de transistors de stockage ayant au moins une grille reliée à une ligne rangée commune (119) d'un ensemble d'au moins une ligne rangée, la dite ligne colonne (110) étant reliée à la masse à travers un transistor à canal-N abaisseur (120) et chacune des dites lignes de bit étant reliée à travers un transistor d'accès à canal-P (132',134') à une première et à une seconde ligne de données (113,115), respectivement, dans lequel le dit transistor abaisseur (120) a une électrode de grille reliée à une ligne de décodage de colonne (117) et chacun des dits transistors d'accès a une grille connectée à ladite ligne colonne, moyennant quoi une transition d'une tension positive à la masse sur la dite ligne colonne en réponse à un signal appliqué à la dite ligne de décodage colonne, rend passant les dits transistors d'accès à canal-P, établissant un chemin de courant entre chacune des dites lignes de bit et une ligne correspondante de données.
EP85402564A 1984-12-26 1985-12-20 Circuit de sélection de données pour mémoire morte à CMOS Expired - Lifetime EP0188956B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US686330 1984-12-26
US06/686,330 US4571708A (en) 1984-12-26 1984-12-26 CMOS ROM Data select circuit

Publications (3)

Publication Number Publication Date
EP0188956A2 EP0188956A2 (fr) 1986-07-30
EP0188956A3 EP0188956A3 (en) 1989-02-22
EP0188956B1 true EP0188956B1 (fr) 1991-03-27

Family

ID=24755864

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85402564A Expired - Lifetime EP0188956B1 (fr) 1984-12-26 1985-12-20 Circuit de sélection de données pour mémoire morte à CMOS

Country Status (5)

Country Link
US (1) US4571708A (fr)
EP (1) EP0188956B1 (fr)
JP (1) JP2504724B2 (fr)
KR (1) KR930004176B1 (fr)
DE (1) DE3582323D1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01196647A (ja) * 1988-01-31 1989-08-08 Nec Corp 誤り訂正機能を有する記憶装置
US5099297A (en) * 1988-02-05 1992-03-24 Emanuel Hazani EEPROM cell structure and architecture with programming and erase terminals shared between several cells
GB9007788D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Dynamic memory bitline precharge scheme
US5784327A (en) * 1991-06-12 1998-07-21 Hazani; Emanuel Memory cell array selection circuits
JP2637314B2 (ja) * 1991-08-30 1997-08-06 株式会社東芝 不揮発性メモリ回路
US7623367B2 (en) * 2006-10-13 2009-11-24 Agere Systems Inc. Read-only memory device and related method of design

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493338A (en) * 1977-10-11 1979-07-24 Texas Instruments Inc Read only memory
JPS5819144B2 (ja) * 1977-12-02 1983-04-16 株式会社東芝 読み出し専用記憶装置
US4207616A (en) * 1978-11-29 1980-06-10 Teletype Corporation Logic array having improved speed characteristics
JPS5831676B2 (ja) * 1979-08-29 1983-07-07 松下電器産業株式会社 記憶装置
JPS5939839B2 (ja) * 1980-05-12 1984-09-26 セイコーエプソン株式会社 リ−ド・オンリ−・メモリ−
JPS5883392A (ja) * 1981-11-10 1983-05-19 Matsushita Electronics Corp 読出し専用メモリおよびその製造方法
JPS58137194A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPS61222096A (ja) 1986-10-02
KR860005376A (ko) 1986-07-21
DE3582323D1 (de) 1991-05-02
KR930004176B1 (ko) 1993-05-21
JP2504724B2 (ja) 1996-06-05
EP0188956A2 (fr) 1986-07-30
EP0188956A3 (en) 1989-02-22
US4571708A (en) 1986-02-18

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