EP0188956B1 - Cmos rom data select circuit - Google Patents
Cmos rom data select circuit Download PDFInfo
- Publication number
- EP0188956B1 EP0188956B1 EP85402564A EP85402564A EP0188956B1 EP 0188956 B1 EP0188956 B1 EP 0188956B1 EP 85402564 A EP85402564 A EP 85402564A EP 85402564 A EP85402564 A EP 85402564A EP 0188956 B1 EP0188956 B1 EP 0188956B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- line
- column
- bit lines
- channel
- column line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
- G11C17/126—Virtual ground arrays
Definitions
- the field of the invention is that of CMOS integrated circuit ROMs.
- the memory matrix comprises a set of column lines connected through a pair of data storage transistors to adjacent bit lines.
- the column line is pulled to ground, thus creating a potential path through the intermediate transistors from the bit lines, which remain near five volts, to ground at the column line.
- the column decode line outside the memory matrix controls three gates per column - the column line in question and pass transistors connecting the two adjacent bit lines with corresponding data lines.
- the use of the NMOS technology means that the full value of VCC cannot be used on the bit lines because there is a threshold drop on the pass transistor between the bit line and the data line.
- the value of the voltage on the bit lines may vary across the chip as a result of Vt variation.
- the invention relates to a data selection circuit adapted for a CMOS ROM, in which P-channel pass transistors on the bit lines have gates that are connected directly to the intermediate column line.
- the column decode line then controls only one transistor per column line - that on the column line.
- the initially off P-channel pass transistors create a path that will pass the full voltage value of VCC, which is uniform across the chip.
- CMOS ROM would need an inverter to invert the signal on the column decoder line and a second line paralleling the column decode line to control the gates of the P-channel pass transistors on the bit lines. There would, therefore, be twice as many lines in the controlling circuit.
- Figure 1 illustrates a data select circuit in the prior art.
- Figure 2 illustrates a straightforward circuit employing P-channel pass transistors.
- FIG. 3 illustrates an embodiment of the invention.
- column line 110 is bracketed by bit lines 112 and 114, connected by data storage transistors 102 and 104 is shown in this figure.
- column decode line 117 which controls pull-down transistor 120 and pass transistors 122 and 124.
- Transistor 120 pulls down the column line to ground and transistors 122 and 124 create a path between data lines 113 and 115 and bit lines 112 and 114 respectively. Since a voltage no higher than VCC minus the Vt of the pass transistor can pass between the bit lines and their data lines, this forces the bit lines to be precharged to this lower voltage level instead of all the way to VCC, the preferred CMOS level.
- CMOS circuit which allows bit lines to be fully precharged to VCC by using P-channel pass gates is shown, with similar elements indicated by the same numeral.
- the column line and the two bit lines are all precharged to VCC by conventional means that form no part of this invention.
- the P-channel pass gates 132 and 134 which have replaced the N-channel pass gates 122 and 124 from Figure 1 may now pass the full VCC from bit lines to data lines, but their gates must be driven by a new signal 127, the inversion of 117.
- FIG. 3 there is shown an embodiment of the invention in which, again, similar elements are indicated by the same numeral.
- the function of the circuit is the same as in Figure 2, but the P-channel pass gates are driven, not by a complement column decode signal, but by the column line 110.
- the column line 110 and its pulldown transistor 120 are being used both for their column line functions and as a dynamic inverter to locally create the necessary column decode line inversion to drive the P-channel pass gates, thus doing away with the need for the complement column decode line 127 shown in Figure 2.
- the advantages of the embodiment shown in Figure 3 over the circuits in Figures 1 and 2 are as follows: Unlike Figure 1, the invention allows bit lines to be precharged completely to VCC by using P-channel pass gates instead of N-channel. This will result in uniform bit-line precharge voltage across the chip, in contrast to the prior art, in which the threshold will vary.
- the invention has less capacitance on line 117 because only one transistor is connected per column line instead of three. In large chips, where a decode line may control more than a hundred columns, this reduction is significant.
- the invention does not require the complement column decode line to be generated and run to the P-channel pass gates.
- the invention places the pass gates, which are of negligible capacitance separately but of sizeable capacitance as a group, separately on each column line. Since the capacitance of the column line is much higher than that of the two pass gates, the effect is also negligible upon the operation of the column line.
- pass transisitors 132' and 134' in the embodiment of Figure 3 are wider, so that there is lower impedance (or better charge transfer) to the data line so that the quality of the signal to the sense amplifier or other sensing device is improved.
Landscapes
- Read Only Memory (AREA)
- Electronic Switches (AREA)
Description
- The field of the invention is that of CMOS integrated circuit ROMs.
- In conventional NMOS ROMs, the memory matrix comprises a set of column lines connected through a pair of data storage transistors to adjacent bit lines. In operation, the column line is pulled to ground, thus creating a potential path through the intermediate transistors from the bit lines, which remain near five volts, to ground at the column line. Since column lines and bit lines alternate, the column decode line outside the memory matrix controls three gates per column - the column line in question and pass transistors connecting the two adjacent bit lines with corresponding data lines. The use of the NMOS technology means that the full value of VCC cannot be used on the bit lines because there is a threshold drop on the pass transistor between the bit line and the data line. The value of the voltage on the bit lines may vary across the chip as a result of Vt variation.
- The invention relates to a data selection circuit adapted for a CMOS ROM, in which P-channel pass transistors on the bit lines have gates that are connected directly to the intermediate column line. The column decode line then controls only one transistor per column line - that on the column line. When the column line drops to ground, the initially off P-channel pass transistors create a path that will pass the full voltage value of VCC, which is uniform across the chip.
- Ordinarily, to perform this function, a CMOS ROM would need an inverter to invert the signal on the column decoder line and a second line paralleling the column decode line to control the gates of the P-channel pass transistors on the bit lines. There would, therefore, be twice as many lines in the controlling circuit.
- Figure 1 illustrates a data select circuit in the prior art.
- Figure 2 illustrates a straightforward circuit employing P-channel pass transistors.
- Figure 3 illustrates an embodiment of the invention.
- Referring to Figure 1, the prior art circuit described above is shown, in which
column line 110 is bracketed bybit lines data storage transistors 102 and 104 is shown in this figure. There will, of course, be many more to be distributed throughout a memory matrix. The operation of the column is controlled bycolumn decode line 117 which controls pull-downtransistor 120 andpass transistors Transistor 120 pulls down the column line to ground andtransistors data lines bit lines - Referring now to Figure 2, a CMOS circuit which allows bit lines to be fully precharged to VCC by using P-channel pass gates is shown, with similar elements indicated by the same numeral. In operation, the column line and the two bit lines are all precharged to VCC by conventional means that form no part of this invention. The P-
channel pass gates channel pass gates new signal 127, the inversion of 117. This requires twice as many column decode lines as the version in Figure 1, because both true and complement decode lines must be used for each column circuit, with the true line driving the pulldown transistor and the complement driving the pass gates. - Referring to Figure 3, there is shown an embodiment of the invention in which, again, similar elements are indicated by the same numeral. The function of the circuit is the same as in Figure 2, but the P-channel pass gates are driven, not by a complement column decode signal, but by the
column line 110. In this embodiment, thecolumn line 110 and itspulldown transistor 120 are being used both for their column line functions and as a dynamic inverter to locally create the necessary column decode line inversion to drive the P-channel pass gates, thus doing away with the need for the complementcolumn decode line 127 shown in Figure 2. The advantages of the embodiment shown in Figure 3 over the circuits in Figures 1 and 2 are as follows: Unlike Figure 1, the invention allows bit lines to be precharged completely to VCC by using P-channel pass gates instead of N-channel. This will result in uniform bit-line precharge voltage across the chip, in contrast to the prior art, in which the threshold will vary. - Unlike Figure 1, the invention has less capacitance on
line 117 because only one transistor is connected per column line instead of three. In large chips, where a decode line may control more than a hundred columns, this reduction is significant. - Unlike Figure 2, the invention does not require the complement column decode line to be generated and run to the P-channel pass gates.
- Unlike the embodiments of both Figures 1 and 2, the invention places the pass gates, which are of negligible capacitance separately but of sizeable capacitance as a group, separately on each column line. Since the capacitance of the column line is much higher than that of the two pass gates, the effect is also negligible upon the operation of the column line.
- As a further advantage, pass transisitors 132' and 134' in the embodiment of Figure 3 are wider, so that there is lower impedance (or better charge transfer) to the data line so that the quality of the signal to the sense amplifier or other sensing device is improved.
- This invention has been described with respect to an embodiment in which the column line is brought to ground through an N-channel transistor and the bit lines have P-channel transistors to rise to VCC. As is known in the art, an equivalent circuit could be constructed in which all the voltages and polarities are reversed i.e. a P-channel pull-up transistor on the column line pulls it to VCC and N-channel pass transistors on the bit line go all the way to ground during the set up stage. In the following claims, channel polarity references and voltage references shall be deemed also to refer to their opposites.
Claims (1)
- A data selection circuit for a CMOS memory integrated circuit having a column line (110) bracketed by first and second bit lines (112,114) and having at least one pair of data storage transistors (102,104) connected respectively between said column line and said first bit line and between said column line and said second bit line, each pair of said at least one pair of data storage transistors having a gate connected to a common row line (119) of a set of at least one row line, said column line (110) being connected through an N-channel pull-down transistor (120) to ground and each of said bit lines being connected through a P-channel pass transistor (132',134') to first and second data lines (113,115), respectively, in which said pull-down transistor (120) has a gate electrode connected to a column decode line (117) and each of said pass transistors has a gate connected to said column line, whereby a transition from a positive voltage to ground on said column line in response to a signal on said column decode line turns on said P-channel pass transistors, establishing a current path between each of said bit lines and a corresponding data line.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/686,330 US4571708A (en) | 1984-12-26 | 1984-12-26 | CMOS ROM Data select circuit |
US686330 | 2000-10-11 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0188956A2 EP0188956A2 (en) | 1986-07-30 |
EP0188956A3 EP0188956A3 (en) | 1989-02-22 |
EP0188956B1 true EP0188956B1 (en) | 1991-03-27 |
Family
ID=24755864
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP85402564A Expired - Lifetime EP0188956B1 (en) | 1984-12-26 | 1985-12-20 | Cmos rom data select circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4571708A (en) |
EP (1) | EP0188956B1 (en) |
JP (1) | JP2504724B2 (en) |
KR (1) | KR930004176B1 (en) |
DE (1) | DE3582323D1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01196647A (en) * | 1988-01-31 | 1989-08-08 | Nec Corp | Storage device with error correcting function |
US5099297A (en) * | 1988-02-05 | 1992-03-24 | Emanuel Hazani | EEPROM cell structure and architecture with programming and erase terminals shared between several cells |
GB9007788D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Dynamic memory bitline precharge scheme |
US5784327A (en) * | 1991-06-12 | 1998-07-21 | Hazani; Emanuel | Memory cell array selection circuits |
JP2637314B2 (en) * | 1991-08-30 | 1997-08-06 | 株式会社東芝 | Non-volatile memory circuit |
US7623367B2 (en) * | 2006-10-13 | 2009-11-24 | Agere Systems Inc. | Read-only memory device and related method of design |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5493338A (en) * | 1977-10-11 | 1979-07-24 | Texas Instruments Inc | Read only memory |
JPS5819144B2 (en) * | 1977-12-02 | 1983-04-16 | 株式会社東芝 | read-only storage |
US4207616A (en) * | 1978-11-29 | 1980-06-10 | Teletype Corporation | Logic array having improved speed characteristics |
JPS5831676B2 (en) * | 1979-08-29 | 1983-07-07 | 松下電器産業株式会社 | Storage device |
JPS5939839B2 (en) * | 1980-05-12 | 1984-09-26 | セイコーエプソン株式会社 | Read-only memory |
JPS5883392A (en) * | 1981-11-10 | 1983-05-19 | Matsushita Electronics Corp | Read-only memory and its manufacture |
JPS58137194A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Semiconductor storage device |
-
1984
- 1984-12-26 US US06/686,330 patent/US4571708A/en not_active Expired - Lifetime
-
1985
- 1985-12-20 DE DE8585402564T patent/DE3582323D1/en not_active Expired - Fee Related
- 1985-12-20 EP EP85402564A patent/EP0188956B1/en not_active Expired - Lifetime
- 1985-12-24 JP JP29179785A patent/JP2504724B2/en not_active Expired - Lifetime
- 1985-12-24 KR KR1019850009824A patent/KR930004176B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR860005376A (en) | 1986-07-21 |
US4571708A (en) | 1986-02-18 |
JPS61222096A (en) | 1986-10-02 |
EP0188956A2 (en) | 1986-07-30 |
KR930004176B1 (en) | 1993-05-21 |
DE3582323D1 (en) | 1991-05-02 |
JP2504724B2 (en) | 1996-06-05 |
EP0188956A3 (en) | 1989-02-22 |
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