JPS5883392A - Read-only memory and its manufacture - Google Patents

Abstract

PURPOSE:To obtain an ROM speedily and easily, by varying the thereshold value of an MIS structure element through partial irradiation with electron beams and particle beams. CONSTITUTION:Specific transistors (TR) Q12, Q15-, etc., in MISTR groups Q11- Q14, Q21-Q24- arranged in a matrix are irradiated with electron beams having necessary energy. Some of the electron beams pass through the polycrystalline silicon of a gate part to reach a gate insulating film and silicon right under it, increasing the surface potential density. Thus, the specific TRs Q12, Q15- increase in threshold voltage, and bit outputs corresponding to those TRs Q12, Q15- have binary values different from those of other TRs. This method which eliminates the need for a photomask and photoetching allows speedy and easy manufacture of an ROM having desired contents. Further, the same result is obtained even by irradiation with particle beams.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to read-only memories.

Conventionally, 'read-only' memory uses a photomask to write the memory contents, and by distinguishing between the presence and absence of 'transistors' at the intersections of the matrix, '1' or '' is read-only memory.
A method of writing in fixed information such as "0" is used.As a method that does not use a photomaskler, a pattern is formed on the resist by directly exposing the photoresist to an electron beam, and this resist pattern is then exposed to 5is.
By selectively etching the N4 film, this Bi, skk
The presence or absence of an oxide film is determined by the presence or absence of . A method that uses the so-called selective oxidation method to create transistors with thick oxide films and transistors with thin oxide films, and creates a difference in threshold voltage (V) in MIS structure transistors, thereby writing information of "1" or "0". It has been known.

Although this method does not require making a photomask,
The photo-etching process is necessary and precise.

This requires a complicated manufacturing process. - The present invention provides a new read-only memory and its manufacturing method that can be realized without any photo-etching process. That is, an object of the present invention is to provide a read-only memory that does not use photomass to write memory contents, and a method for manufacturing the same.

An object of the present invention is to quickly and easily manufacture a read-only memory by introducing a process that can shorten the time required to determine the memory contents and complete the memory device that exhibits the performance thereof. The present invention provides a read-only memory that can realize a memory device of 1, and a method for manufacturing the same.

In the present invention, an electron beam is applied partially near the surface of a semiconductor.

By irradiating the WXS structure element with a particle beam, etc., the electrical properties of the WXS structure element, such as the surface mobility of the threshold voltage, etc. are changed, thereby realizing a 2m memory element with different characteristic values between the irradiated area and the non-irradiated area. By electrically detecting the difference in this characteristic value, the difference between '1' and '0' can be detected.
The value is stored and read out. This will be explained in detail below using examples.

The figure shows an example of the configuration of a 16-bit read-only memory.
The bit addresses 1 to 3 are divided into four lines each by two decoders. This memory is composed of P-channel silicon gates, and only one of the transistors Q1 to Q4 is turned on or off depending on the output of the decoder 1).
N), others are (OFF OFF) and s ll+ ~ 14
Ground one of them. (In this case, the ground level is set to high level.) m1 to m4 are output lines of the decoder (II) and are illusory.

Depending on the signal of system 3, only one becomes high level, and Q11~Q1& , Q21~Q241 QS1~Q
Only one set of each of the transistor groups Q4t to Q44 is driven accordingly.

Each of the above transistor groups Q11 to Q1a, Q21 to Q
24°Qs+~QS4, 16 of Q41~Q44
Each of these transistors is a memory transistor of a 16-bit memory, and is arranged in the chip in a uniform positional relationship as shown in this circuit diagram. Now, among these 16 transistors, the one enclosed in a circle is Q' * Q" *
Q22 + Q2A t Q51 # Qll p Q
An electron beam having an energy μ of 30 keV to 300 kaV is irradiated only to the gate portion of each transistor of 42 + Q44. A considerable portion of the electron beam passes through the polycrystalline silicon of the gate portion and reaches the gate insulating film and the silicon directly below it, resulting in an increase in surface state density and the like.

As a result, the value (absolute value) of the threshold voltage of the irradiated transistor increases, and becomes a value at which the transistor cannot be turned on at the low level value of the output of the decoder (II). Therefore, when any one of the transistors (for example, Q12) enclosed in the circle mentioned above is selected from the combination k of the outputs of the decoder fI) and the decoder (Ill), the transistor is off and the readout line d is Negative power supply vD111
The output terminal (OUT) becomes low level, which is the same potential as .゛・Furthermore, when a transistor not enclosed in a circle (for example, Qll) is selected, that transistor is turned on at the low level of the output of the decoder fll), so the readout line d becomes approximately at ground potential, that is, at a high level, The output terminal (otrr) becomes high level p. Here, R is a detection resistor. Therefore, if the high level p corresponds to "1" and the low level corresponds to "O・〃, '
By irradiating only the gate portion of the transistor at the desired address with an electron beam, the contents of the memory can be written with only the step of irradiating the electron beam.

It should be noted that the technique of selectively irradiating specific positions within a plane with an electron beam is already widely used as a well-known technique, so a description thereof will be omitted.

Generally, when irradiated with an electron beam, the above-mentioned threshold voltage V
The surface mobility often decreases with the change in , and in the above-mentioned P-channel silicon gate element C, this also acts in the direction of turning off the transistor, and has a synergistic effect with the change in the threshold voltage vte.

Although the above embodiment is an example of a silicon gate, it can be similarly implemented in the case of a metal gate MOS (MOS) transistor, and in the case of an n-channel transistor, there is no synergistic effect as described above, and the direction of fluctuation is opposite. Taking this into consideration, it goes without saying that they are essentially the same and the present invention can be effectively implemented.

Although the above embodiment uses electron beam irradiation, the present invention is not limited to the use of electron beams, and can be implemented using a wide range of particle beams, such as ion implantation. Techniques for utilizing particle beams are also well known in ion implantation techniques and the like, so explanations thereof will be omitted.

As explained using the above embodiments, according to the present invention, the memory contents can be written without using a photomanuk or without using a photoetching process, so the manufacturing process is quick and easy. Therefore, the number of days required from determining the memory contents to completing the memory device can be extremely shortened. In addition, since the present invention writes the memory contents near the final process of memory device manufacturing, all the memory devices can be manufactured in the same way regardless of the memory contents up until that point, and the wafer last can be manufactured up to that point and only have to write the memory. If this is done, the completion of the memory device will be further accelerated, and the effectiveness of the present invention will be further demonstrated.

[Brief explanation of the drawing]

The figure is a schematic diagram of a read-only memory circuit configuration diagram according to an embodiment of the present invention. Ql...Qa4...P channel silicon gate transistor (memory element). Name of agent: Patent attorney Nakao-male and 1 other person 1983-83392 (3)

Claims (2)

[Claims] (1) The memory transistor is constituted by a transistor group having a first threshold voltage and a transistor group having a second threshold voltage converted by irradiation with an electron beam or a grain beam, and A read-only memory characterized by storing price information. (2) It is possible to write information of either 1 or 0 by irradiating the gate part of the memory transistor into which information of either 1 or 0 is to be written. A method for manufacturing a read-only memory featuring features.