EP0180593B1 - Kathodenstrahlröhreanzeigegerät - Google Patents

Kathodenstrahlröhreanzeigegerät Download PDF

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Publication number
EP0180593B1
EP0180593B1 EP19850901828 EP85901828A EP0180593B1 EP 0180593 B1 EP0180593 B1 EP 0180593B1 EP 19850901828 EP19850901828 EP 19850901828 EP 85901828 A EP85901828 A EP 85901828A EP 0180593 B1 EP0180593 B1 EP 0180593B1
Authority
EP
European Patent Office
Prior art keywords
signal
memory
ray tube
cathode ray
crt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19850901828
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English (en)
French (fr)
Other versions
EP0180593A1 (de
Inventor
Chin-Cheng Yang
Shinsaku Fujikawa
Masashi Utsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59077643A external-priority patent/JPS60225887A/ja
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0180593A1 publication Critical patent/EP0180593A1/de
Application granted granted Critical
Publication of EP0180593B1 publication Critical patent/EP0180593B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Definitions

  • This invention relates to cathode ray tube display systems of the kind including: a cathode ray tube adapted to display images on the screen thereof; memory means adapted to the store data to be displayed; processing means adapted to access said memory means; a cathode ray tube controller adapted to access said memory means to refresh images displayed on said screen; and multiplexing means connected to receive address signals from said processing means and from said cathode ray tube controller and having an output coupled to said memory means, said multiplexing means being responsive to a switching signal to provide address signals from said processing means to said output, and said signal generating means being responsive to an inhibit signal to inhibit the provision of said video signal for a predetermined period of time.
  • CTR cathode ray tube
  • a cathode ray tube display system of the kind specified is known from U.S. Patent Specification US-A-4,379,293.
  • the known system includes a CRT controller connected to a processor and having a refresh address generator to refresh the display on the cathode ray tube, an update address generator to update information in the refresh memory, and a control circuit for connecting the update address generator and the refresh address generator to address the memory so that only one of the generators has control of the refresh memory at a time.
  • the known system has the disadvantage of being complex in construction and hence expensive to manufacture.
  • a cathode ray tube display system wherein data to be displayed on a cathode ray tube (CRT) is formed by a microcomputer during a display period and is stored in a work memory.
  • a CRT controller supplies a vertical. synchronizing signal to the CRT, which signal also serves as an interrupt signal for the microcomputer whereby an address supplied by the microcomputer is effective to access a display memory, such that data is transferred from the work memory to the display memory during the vertical blanking period of the picture being displayed on the CRT.
  • the amount of data to be transferred is large, the data transfer is continued beyond the vertical blanking period and during the data transfer the display on the CRT is inhibited, whereby a visual impression is created as if the picture disappeared for a short period of time.
  • a cathode ray tube display system of the kind specified is characterized by control means coupled to said processing means, said multiplying means and said video signal generating means by first data bus means connected to said memory and to latching means which are connected to said signal generating means; and by second bus means connected to said processing means and to gating means connected to said first bus and responsive to a gating signal provided by said control means to connect said first bus means to said second bus means; whereby, in response to a request signal applied from said processing means to said control means, said control means is effective to provide said switching signal to said multiplexing means, to provide said gating signal to said gating means and to provide said inhibit signal to said signal generating means.
  • a cathode ray tube display system has the advantage of being relatively simple in construction.
  • a further advantage is that the system has the capability of obviating any flashing or flickering on the screen which could occur during processor access to the refresh memory.
  • Still another advantage is that timing difficulties are alleviated. For example, synchronization between reference clocks for the processor and the cathode ray tube controller and any consequent need for high speed circuit elements is avoided.
  • the preferred embodiment utilizes a cathode ray tube having a long persistence light emission time.and constructed in such a manner that the CRT controller monopolizes the refresh memory to sequentially read out addresses therefrom unless access to the memory is requested by the central processing unit (CPU).
  • Data which is read out from the refresh memory by the CRT controller is stored in a latch circuit and a character generator produces a display pattern signal which is based on such data.
  • the display pattern signal is converted into serial data by a parallel-to-serial converter and is sent to the long persisting CRT as a video signal for controlling electron beams.
  • the control unit in the system of the preferred embodiment is constructed so as to generate and send out various control signals such as a select signal for switching an appropriate address bus when the access to the memory is requested by the CPU, a gate control signal for connecting and switching a data bus, and a video ir hibit signal.
  • the control unit sends the select signal to a multiplexer to switch the address bus from the CRT controller to the CPU and also sends the gate control signal to the gate to connect a data line of the memory with the data bus of the CPU.
  • the control unit sends a read or write signal to the refresh memory to permit the access to the memory from the CPU.
  • the data stored in the latch when the CPU accesses the memory is not the data to be displayed on the CRT at that time, but is the data based on the access from the CPU so that sending a video signal which is generated in form as based on this data to the long persisting CRT would cause a flash to appear on the CRT screen.
  • the control unit sends the video inhibit signal for a predetermined period of time after the access is requested by the CPU to inhibit the video signal from being sent out from the parallel-to-serial converter.
  • a portion of the screen will not flicker owing to the visual persistence effect of the long persisting CRT even though the sending out of the video signal is inhibited for the predetermined period of time.
  • Fig. 1 is a block diagram illustrating the diagrammatic structure of an embodiment of the present invention wherein 10 is a central processing unit or CPU using an SCLK as the reference clock signal, 12 is a cathode ray tube or CRT controller using a CCLK as the reference clock signal, 14 is a CRT refresh memory for storing data required for the CRT screen display and 16 is a multiplexer for switching an address bus 18 from the CPU 10 and an address bus 20 from the controller 12 so as to connect either one of the buses to the memory 14.
  • a latch circuit 22 is controlled by the reference clock CCLKto latch the data on a data line of the memory 14.
  • a character generator CG 24 sends a pattern signal of a character to be displayed in accordance with the data in the latch circuit 22, and a parallel-to-serial converter 26 converts the parallel display pattern signal sent from the character generator 24 into a serial signal to send it to a CRT 30 as the video signal.
  • a long persisting CRT 30 uses fluorescent paint such as P-39 or the like to provide a CRT screen of long persistence time.
  • a control unit 32 sends various control signals such as a select signal 33, a gate control signal 35, and a video inhibit signal DISPLAY INHIBIT according to the request from the CPU 10 to access the memory 14.
  • a gate circuit 34 is provided between and connects a data bus 36 of the CPU and a data bus 38 of the memory 14.
  • the CRT controller 12 sequentially reads out the content of the refresh memory 14 while always counting up addresses one by one in accordance with the reference clock CCLK to refresh the display on the screen of the CRT 30.
  • the control unit 32 sends the select signal to the multiplexer 16 to switch the address line to the address bus 18, sends the gate control signal to the gate circuit 34 to connect the data bus 36 and the data line 38 together and to access the memory 14 simultaneously therewith.
  • the data on the data line 38 which is sent at that particular time is a read data in response to the request of the CPU 10 or is a write data sent from the CPU and is not the data intended for the CRT 30 display.
  • the latch circuit 22 unconditionally latches the data on the data line 38 in accordance with the reference clock CCLK and the character generator 24 produces a display pattern signal based on the latch data in the latch and sends it to the parallel-to-serial converter 26. Then, if the converter 26 converts the display pattern signal into a serial signal and sends it to the CRT 30 as the video signal, a character which should not be displayed will be instantaneously displayed and thereby cause the flash to generate or appear on the CRT screen.
  • the DISPLAY INHIBIT signal is adapted to inhibit the sending out of the video signal for the predetermined period of time until a correct display pattern signal comes out, thereby preventing flashing on the screen.
  • the long persisting CRT 30 is used so that a preferable display state can be maintained without flicker on the screen, owing to the visual persistence effect of the long persisting CRT, even though the sending out of the video signal is stopped or delayed for the predetermined period of time.
  • Fig. 2 is a diagrammatic block diagram illustrating the relationship between the control unit and the associated peripheral circuit elements.
  • a memory request signal MREQ and a read signal RD or a write signal WR are input into an AND gate 44, the output of which is connected to a flip-flop 46, to the gate circuit 34, and to the multiplexer 16.
  • the read signal RD is input into the gate circuit 34 and is inverted by an inverter 48 to be input into a NOR gate 50 together with the output from the AND gate 44 and then to be supplied to the refresh memory 14.
  • the write signal WR is directly supplied to the refresh memory 14.
  • the output of the flip-flop 46 is connected to the input of a flip-flop 52 through an AND gate 54, and the output of the flip-flop 52 is connected to the parallel-to-serial converter 26 as a DISPLAY INHIBIT signal.
  • the reference clock CCLK signal of the controller 12 is input through an inverter 56 to the clock inputs of the flip-flops 46 and 52.
  • the reference clock signal CCLK is also provided to the latch circuit 22 through an inverter 58.
  • the output from the gate 44 also goes to the low level which output is then sent to the multiplexer 16 and the gate circuit 34 as means for generating the select signal 33 and the gate control signal 35, whereby the switching of the address buses 18 and 20 and the connection between the data buses 36 and 38 are accomplished.
  • the RD signal is also being input into the gate 34 by which its connecting direction is switched in such a manner that the data from the memory 14 is sent to the CPU 10 in the read mode while the data from the CPU is written into the memory 14 in the write mode.
  • the RD or WR signal is sent to the refresh memory 14 thereby to read the data from or write the data into the memory.
  • the flip-flop 46 When the output from the AND gate 44 is at the low level, the flip-flop 46 is directly reset by reason of which the flip-flop 52 is also reset at the next fall of the reference clock signal CCLK. When the flip-flop 52 is reset, the low output is sent to the parallel-to-serial converter 26 as the DISPLAY INHIBIT or video inhibit signal to inhibit the video signal from being sent to the CRT 30.
  • the flip-flops 46 and 52 are sequentially set at each falling of the CCLK signal after the output from the AND gate 44 goes to the high level. In other words, the flip-flop 52 is set at the second falling edge of the CCLK signal after the output from the AND gate 44 goes to the high level and, hence, the video inhibit signal is not sent out.
  • the duration of the DISPLAY INHIBIT signal corresponds to that of two reference clock CCLK signals
  • the duration and the time of sending the video inhibit signal can be freely changed depending on the access time of the character generator 24 and the parallel-to-serial converter 26 and the necessity or requirement of the Chinese or like character display. For example, in order to display one Chinese character, it is necessary to continuously access the refresh memory 14 two times and, in relation thereto, it is necessary to send the video inhibit signal for a relatively longer time. Accordingly, and as illustrated in Fig.
  • Fig. 4 is a timing diagram illustrating various operation timings of the embodiment in Fig. 2.
  • the controller 12 accesses the refresh memory 14 by sequentially counting up addresses in accordance with the reference clock CCLK signal.
  • the select signal (g) is immediately sent to the multiplexer 16 to switch the address buses 18 and 20. Since the address data is already sent on the address bus 18 of the CPU 10 as shown by Fig. 4(c), the memory read or memory write signal (f) is immediately sent out.
  • Fig. 4 the select signal
  • the CRT controller 12 reads out the addresses from the refresh memory 14 in a monopolizing manner when the access to the memory is not requested by the CPU 10, and the controller gives a priority to the CPU when the access is requested by the CPU and sends the video inhibit signal during that time whereby the full one cycle of the reference clock CCLK signal is assigned as the access time of the memory so that the present invention can provide the CRT display device in an arrangement capable of processing the access request of the CPU without delay even when elements of relatively low speed are used.
  • the flashing on the screen due to the generation of an incorrect video signal can be avoided and a preferable display state can be maintained by generating the video inhibit signal for inhibiting the sending out of the video signal based on the access data of the CPU 10 and by utilizing the visual persistence effect of the long persisting CRT 30.
  • the CRT 30 display device is composed of a simpler structure by using low speed elements so that a lower priced CRT display device can be provided.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Claims (4)

1. Kathodenstrahlenröhren-Anzeigesystem mit: einer Kathodenstrahlenröhre (30), die geeignet ist, Bilder auf ihrem Schirm anzuzeigen; einer Speichervorrichtung (14), die geeignet ist, anzuzeigende Daten zu speichern; einer Verarbeitungsvorrichtung (10), die geeignet ist, auf die Speichervorrichtung (14) zuzugreifen; einer Kathodenstrahlenröhrensteuerung (12), die geeigent ist, auf die Speichervorrichtung (14) zuzugreifen, um auf dem Schirm angezeigte Bilder aufzufrischen und einer Multiplexervorrichtung (16), die zum Empfang von Adressensignalen von der Verarbeitungsvorrichtung (10) und von der Kathodenstrahlröhrensteuerung (12) geschaltet und mit einem Ausgang versehen ist, der mit der Speichervorrichtung (14) gekoppelt ist, wobei die Multiplexervorrichtung (16) auf ein Schaltsignal anspricht, um Adressensignale von der Verarbeitungsvorrichtung (10) an den Ausgang zu legen und die Signalerzeugungsvorrichtung (24, 26) auf ein Blockiersignal anspricht, um die Abgabe des Videosignals für eine vorbestimmte Zeitperiode zu blockieren, gekennzeichnet durch eine Steuervorrichtung (32), die mit der Verarbeitungsvorrichtung (10), der Multiplexervorrichtung (16) und der Videosignal-Erzeugungsvorrichtung (24, 26) gekoppelt ist; durch eine erste Datensammelleitungsvorrichtung (38), die mit der Speichervorrichtung (14) und einer Haltevorrichtung (22) gekoppelt ist, die mit der Signalerzeugungsvorrichtung (24, 26) verbunden sind; und durch eine zweite Sammelleitungsvorrichtung (36), die mit der Verarbeitungsvorrichtung (10) und einer mit der ersten Sammelleitungsvorrichtung (38) verbundenen Torvorrichtung (34) verbunden ist, die auf ein von der Steuervorrichtung (32) abgegebenes Torsignal anspricht, um die erste Sammelleitungsvorrichtung (38) mit der zweiten Sammelleitungsvorrichtung (36) zu verbinden; wodurch unter Ansprechen auf ein von der Verarbeitungsvorrichtung (10) an die Steuervorrichtung (32) angelegtes Anforderungssignal die Steuervorrichtung (32) wirksam wird, um das Schaltsignal an die Multiplexervorrichtung (16) zu legen, um das Torsignal an die Torvorrichtung (34) abzugeben und das Blockiersignal an die Signalerzeugungsvorrichtung (24, 26) zu legen.
2. Anzeigesystem nach Anspruch 1, dadurch gekennzeichnet, daß die Kathodenstrahlröhre (30) eine genügend lange Nachleuchtdauer abhängig von der vorbestimmten Zeitperiode besitzt, um ein Aufblitzen oder Flackern der Anzeige auf dem Schirm zu verhindern.
3. Anzeigesystem nach Anspruch 2, dadurch gekennzeichnet, daß die Signalerzeugungsvorrichtung (24, 26) einen Zeichen-Generator (24) aufweist, der mit einer Parallel-Seriell-Umwandlungsvorrichtung (26) gekoppelt ist, die geeignet ist, das Videosignal abzugeben, und angeordnet ist, das Blockier-signal zu empfangen.
4. Anzeigesystem nach Anspruch 1, dadurch gekennzeichnet, daß die Verarbeitungsvorrichtung einen Mikroprozessor (10) aufweist.
EP19850901828 1984-04-19 1985-03-27 Kathodenstrahlröhreanzeigegerät Expired EP0180593B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP77643/84 1984-04-19
JP59077643A JPS60225887A (ja) 1984-04-19 1984-04-19 Ｃｒｔデイスプレイ装置
US06/677,115 US4581611A (en) 1984-04-19 1984-11-30 Character display system
US677115 1991-03-29

Publications (2)

Publication Number Publication Date
EP0180593A1 EP0180593A1 (de) 1986-05-14
EP0180593B1 true EP0180593B1 (de) 1989-09-13

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EP19850901828 Expired EP0180593B1 (de) 1984-04-19 1985-03-27 Kathodenstrahlröhreanzeigegerät

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EP (1) EP0180593B1 (de)
DE (1) DE3573037D1 (de)
WO (1) WO1985004976A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2557077B2 (ja) * 1987-12-21 1996-11-27 エイ・ティ・アンド・ティ グローバル インフォメーション ソルーションズ インターナショナル インコーポレイテッド 同期アクセス方式のキヤラクタ表示システム
GB8908612D0 (en) * 1989-04-17 1989-06-01 Quantel Ltd Video graphics system
GB2250668B (en) * 1990-11-21 1994-07-20 Apple Computer Tear-free updates of computer graphical output displays

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852231B2 (ja) * 1978-04-14 1983-11-21 ファナック株式会社 キヤラクタデイスプレイ
JPS5960480A (ja) * 1982-09-29 1984-04-06 フアナツク株式会社 デイスプレイ装置

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WO1985004976A1 (en) 1985-11-07
DE3573037D1 (en) 1989-10-19
EP0180593A1 (de) 1986-05-14

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