EP0169940A1 - Dispositif de commande d'affichage pour un terminal de visualisation de données - Google Patents

Dispositif de commande d'affichage pour un terminal de visualisation de données Download PDF

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Publication number
EP0169940A1
EP0169940A1 EP84115597A EP84115597A EP0169940A1 EP 0169940 A1 EP0169940 A1 EP 0169940A1 EP 84115597 A EP84115597 A EP 84115597A EP 84115597 A EP84115597 A EP 84115597A EP 0169940 A1 EP0169940 A1 EP 0169940A1
Authority
EP
European Patent Office
Prior art keywords
memory
control unit
signals
image control
unit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP84115597A
Other languages
German (de)
English (en)
Inventor
Roland Dipl.-Ing. Roth
Ivan Dipl.-Ing. Furjanic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0169940A1 publication Critical patent/EP0169940A1/fr
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays

Definitions

  • the invention relates to an image control unit for a data display device according to the preamble of patent claim 1.
  • Image control units for data display devices are generally known and are commercially available in the form of integrated circuits. They are intended for display units, in particular cathode ray tubes with standardized BAS signal inputs. When using display units which do not have these standardized BAS signal inputs, with maximum utilization of the image area and with high image change frequencies, these known image control units can no longer be used without further ado. In addition, when such image control units are connected to microprocessors, there is often additional component expenditure. If it is also necessary to slowly shift the content of the display unit under the designation "soft scroll", further signals must be generated, which must be generated at specified times when the image is being built up.
  • the invention is therefore based on the object of specifying an image control unit which requires little outlay but which can nevertheless be adapted to different applications and which can be produced inexpensively.
  • the task in the image control unit of the type mentioned by the in the characterizing nenden part of claim 1 specified features solved.
  • the image control unit according to the invention has the advantage that it can be used very flexibly for different types of image construction on the display unit by exchanging the memory or by changing the memory content.
  • the memory is designed as an exchangeable, as an electrically programmable read-only memory or as a loadable memory.
  • the second counter can be set by means of block length signals stored in the memory itself and thus defines the length of the subsequent block. It is particularly advantageous here if the block length signals are stored serially in the memory and are fed to the second counter for presetting.
  • the second counter is expediently followed by a flip-flop, which is set when the second counter is carried over and whose output signal is linked to an end-of-line signal in order to advance the third counter.
  • a buffer is expediently connected downstream of the memory, in which binary characters assigned to the control signals can be buffered. Further binary characters can be stored in the memory, which are assigned to video signals of markings or, for example, frames on the display unit.
  • the binary characters can control signals from a variety of different types of image be saved on the display unit and called up by a switch.
  • the data display device shown in FIG. 1 is controlled by a microprocessor MP.
  • An interruption control IS and, on the other hand, a programmable control unit for direct memory access DMA (Direct Memory Access) are connected to the microprocessor MP.
  • a primary memory PS, a secondary memory SS, a keyboard TA, a printer DR, a communication part KT and a display unit AE with a screen BS are connected via a data bus DB and possibly an address bus.
  • the primary memory PS is designed as a semiconductor memory and it serves as a program memory and working memory.
  • the secondary storage SS can be designed as a floppy disk storage and / or as a magnetic bubble storage.
  • the keyboard TA contains keys for entering alphanumeric characters and function keys for performing various functions.
  • the printer DR is designed in a known manner and contains a type or a mosaic printing unit.
  • the communication part KT is connected to a long-distance line FL and contains transmission units for sending or receiving characters.
  • the image generator BG contains a character generator that. contains data words assigned to the shape of the characters in a manner known per se. Depending on the code characters, the corresponding data words are read from the character generator and transferred to a pixel memory BP. A memory element of the pixel memory is assigned to each pixel on the screen BS. The pixel memory serves as an image repetition memory and from it the data words are read out in accordance with an image change frequency and transmitted to the display unit AE.
  • the screen BS of the display unit AE can be designed as a screen of a cathode ray tube.
  • corresponding video signals are generated from the binary characters stored in the pixel memory, with which, for example, the electron beam of the cathode ray tube is scanned brightly. If the screen BS is formed from individual picture elements, the video signals are supplied to these picture elements.
  • the characters on the screen BS are displayed line by line and the characters to be displayed are composed of pixels which are arranged on these lines.
  • the image generator BG shown in FIG. 2 contains a control unit ST, which, for example, is also a micro processor is trained.
  • the control unit ST is connected on the input side to the data bus DB.
  • the code character CZ assigned to this character is transmitted to the image generator BG via the data bus DB.
  • the control unit ST switches the code character CZ through to the character generator ZG, in which data words DW associated with the shape of the character are stored.
  • the character is formed line by line, with each line corresponding to a data word DW.
  • address signals which are assigned to the coordinates of the character on the screen BS are transmitted via the data bus DB. These coordinates are buffered in two registers XAR and YAR.
  • the image generator BG contains an image control unit B, which transfers the data words DW into the pixel memory BP, reads out the data words DW from the pixel memory BP for generating the video signals VS and generating signals SV and SH for vertical and horizontal synchronization of the Display unit AE controls.
  • graphic patterns for example alphanumeric characters
  • a cursor SM indicates the position at which the next character is written.
  • Writing is only possible within one writing line, which is identified by the two markings M1 and M2.
  • the signals SV and SH for vertical and horizontal synchronization are blanking pulses for the picture width of for example 82 characters, memory drive signals, such as request signals for the memory controller DMA and for the interrupt controller IS, and line end pulses are required.
  • marking signals are also required, which can also be generated in the image control unit.
  • the video signals VS for displaying the characters on the screen BS are generated in the pixel memory BP.
  • binary characters assigned to the control signals for the image structure are stored in a memory SP. It would be conceivable to provide a line of binary characters in the memory SP for each line on the screen BS. However, this would require a great deal of effort if, for example, a line would require 109 storage spaces and 318 lines could be displayed on the BS screen. For the image area BF, however, only 82 drawing spaces and 300 lines would be used, for example.
  • the memory SP is advantageously designed as a read-only memory. It can be exchangeable or can be designed as an electrically programmable read-only memory.
  • the memory SP is addressed cyclically and a corresponding control signal is output at each of its data outputs. Two data outputs are used to control the addressing of the memory SP by a type of microprogramming, which is simultaneously stored in the memory SP.
  • the memory SP is addressed with the aid of three counters Z1 to Z3, the counter Z1 counting the number of characters along a line, for example 109, the memory Z2 counting the number of identical lines within a block and the counter Z3 indicating the block number.
  • the memory SP is followed by a buffer R designed as a register, at the outputs of which the signals SV and SH as well as the further control signals are emitted.
  • the image control unit BS also contains a clock generator TG, which outputs clock pulses to the memory SP, the buffer memory R and the counter Z1 and also controls a buffer memory ZS, in which characters are stored by the pixel memory BP and are read out serially in order to transmit the video signal VS. produce.
  • the time t is represented in the abscissa direction by the corresponding number of character clock pulses ZT and in the ordinate direction the instantaneous values of the various control signals.
  • the signals shown in solid lines in FIG. 5 are assigned, for example, to a block which shows 12 lines on the screen BS, namely those 12 lines which are arranged approximately in the center of the screen BS and with which the markings M1 and M2 can be represented.
  • the other blocks usually differ from this block only in that the dashed signal SV for vertical synchronization and the memory control signals DR and IN then have a different course.
  • a block length signal BL in other blocks contains either no or a different number of pulses.
  • the signal SV in this block has the binary value 0 and is therefore inactive.
  • the signal SH for horizontal synchronization still has the binary value 0, which in this case is assigned to the active state.
  • a blanking signal A which defines the area in which characters can be displayed on the screen BS, has the binary value 1 and is inactive.
  • a memory control signal DR with which the memory PS can be accessed directly, has the binary value 0 and is therefore active in order to retrieve from the memory PS the characters which are displayed using the line to be displayed.
  • the further memory drive signal IN which is an interrupt signal, can also be active at this point in time if soft scrolling capability is desired.
  • This marking signal MA is also fed via the gate G1 to the display unit AE as a video signal VS in order to make the screen BS appear dark at this point. Then the signal SH assumes the binary value 1 and thus becomes inactive. It becomes active again at the ZT97 counting cycle and initiates horizontal synchronization. Then the blanking signal A becomes inactive again and blocks the screen BS for a representation of characters. A marking signal MA then occurs again in order to display the right writing line marking M2 on the screen BS.
  • the line end signal LE occurs at the counting clock ZT109. This switches the counter Z2 on via the OR gate G2. If the line was not the last line of the block shown, the counter Z3 is not affected. The counter Z1, on the other hand, is reset and counted up again, so that the same control signals are generated again. However, if the line shown was the last line of a block, the counter Z2, which has a fixed count length, outputs a carry signal C to a flip-flop F, whereby this is set. The counter Z3 is then advanced via the AND gate G3 and the next block is addressed.
  • next block has the same length, which corresponds to the fixed counting range of the counter Z2, again so many lines are shown until the counter Z2 emits the carry signal C and the next block is addressed.
  • the counter Z2 if it has a fixed count length of 16, will be replaced by block length signals BL during the representation of the last line of the previous block by four block length signals BL via the AND gate G4 and the OR gate G2 is counted up, so that when the next block is read out, the carry signal C occurs after 12 signals LE and the counter Z3 is incremented.
  • the counter Z3 has a count length of 32, for example, so that up to 32 different blocks are available for generating the control signals.
  • the counter Z1 has a count length of 128, for example, of which only 109 are used in the present exemplary embodiment.
  • control signal SV has the binary value 1 and is therefore activated in order to carry out a vertical synchronization.
  • the signal SV is therefore shown in dashed lines in FIG. 5.
  • the memory control signal IN briefly assumes the binary value 0 and is thus activated in order to trigger a rapid re-storage of the video information assigned to the lines.
  • a switch S is connected to the memory SP, with which, for example, the most significant address bit can be switched in order to trigger different images on the screen BS.
  • switch S When switch S is open, for example, a test image is displayed and when the switch is closed an image is built up that corresponds to the image shown in FIG. 3, in which alphanumeric characters can be displayed on the image surface BF.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP84115597A 1984-07-27 1984-12-17 Dispositif de commande d'affichage pour un terminal de visualisation de données Ceased EP0169940A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3427810 1984-07-27
DE3427810 1984-07-27

Publications (1)

Publication Number Publication Date
EP0169940A1 true EP0169940A1 (fr) 1986-02-05

Family

ID=6241777

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84115597A Ceased EP0169940A1 (fr) 1984-07-27 1984-12-17 Dispositif de commande d'affichage pour un terminal de visualisation de données

Country Status (5)

Country Link
US (1) US4731608A (fr)
EP (1) EP0169940A1 (fr)
JP (1) JPS6139094A (fr)
BR (1) BR8503546A (fr)
ZA (1) ZA855634B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237706A2 (fr) * 1986-02-14 1987-09-23 International Business Machines Corporation Système d'affichage électrique

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070157126A1 (en) * 2006-01-04 2007-07-05 Tschirhart Michael D Three-dimensional display and control image

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2075317A (en) * 1980-04-11 1981-11-11 Ampex Computer graphics system

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US3696387A (en) * 1969-06-25 1972-10-03 Hans Georg Nussbaum Circuit arrangement for controlling cathode-ray tubes for the display of alpha-numerical characters
US3617772A (en) * 1969-07-09 1971-11-02 Ibm Sense amplifier/bit driver for a memory cell
US4093221A (en) * 1976-12-13 1978-06-06 Massachusetts Institute Of Technology Simulated video game
JPS5851273B2 (ja) * 1976-12-17 1983-11-15 株式会社日立製作所 カ−ソル表示信号発生方式
US4156238A (en) * 1977-11-25 1979-05-22 Teletype Corporation Display apparatus having variable text row formating
US4163229A (en) * 1978-01-18 1979-07-31 Burroughs Corporation Composite symbol display apparatus
US4283724A (en) * 1979-02-28 1981-08-11 Computer Operations Variable size dot matrix character generator in which a height signal and an aspect ratio signal actuate the same
DE2939458A1 (de) * 1979-09-28 1981-05-21 Siemens Ag System zur lokalisierung von bereichen bei gemischter text-/bildbearbeitung am bildschirm
US4309700A (en) * 1980-05-22 1982-01-05 Technology Marketing, Inc. Cathode ray tube controller
US4352100A (en) * 1980-11-24 1982-09-28 Ncr Corporation Image formatting apparatus for visual display
US4437092A (en) * 1981-08-12 1984-03-13 International Business Machines Corporation Color video display system having programmable border color
US4625202A (en) * 1983-04-08 1986-11-25 Tektronix, Inc. Apparatus and method for generating multiple cursors in a raster scan display system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2075317A (en) * 1980-04-11 1981-11-11 Ampex Computer graphics system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WESCON TECHNICAL PAPERS, Band 26, September 1982, Seiten 33/2 (1-13), North Hollywood, US; J. KAHN: "A VLSI controller for bit-mapped graphics display" *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0237706A2 (fr) * 1986-02-14 1987-09-23 International Business Machines Corporation Système d'affichage électrique
EP0237706A3 (en) * 1986-02-14 1989-11-23 International Business Machines Corporation Electrical display system

Also Published As

Publication number Publication date
US4731608A (en) 1988-03-15
ZA855634B (en) 1986-03-26
BR8503546A (pt) 1986-04-22
JPS6139094A (ja) 1986-02-25

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Inventor name: ROTH, ROLAND, DIPL.-ING.