EP0169940A1 - Display controller for a data display terminal - Google Patents

Abstract

The image control unit (B) generates control signals for the construction of an image with graphic patterns, in particular texts on a display unit (AE). The image is constructed by a large number of lines and the image control unit (B) generates the corresponding horizontal and vertical synchronizing signals (SH, SV) and access signals to a memory (PS) in order to call up stored video signals (VS). The image control unit (B) contains a memory (SP), preferably a programmable read-only memory, in which binary characters assigned to the signals are stored. The binary characters of successive identical control signals are combined into a block and read out several times. The block length of a block can be set by means of control signals in the previous block.

Description

The invention relates to an image control unit for a data display device according to the preamble of patent claim 1.

Image control units for data display devices are generally known and are commercially available in the form of integrated circuits. They are intended for display units, in particular cathode ray tubes with standardized BAS signal inputs. When using display units which do not have these standardized BAS signal inputs, with maximum utilization of the image area and with high image change frequencies, these known image control units can no longer be used without further ado. In addition, when such image control units are connected to microprocessors, there is often additional component expenditure. If it is also necessary to slowly shift the content of the display unit under the designation "soft scroll", further signals must be generated, which must be generated at specified times when the image is being built up.

The invention is therefore based on the object of specifying an image control unit which requires little outlay but which can nevertheless be adapted to different applications and which can be produced inexpensively.

According to the invention the task in the image control unit of the type mentioned by the in the characterizing nenden part of claim 1 specified features solved.

The image control unit according to the invention has the advantage that it can be used very flexibly for different types of image construction on the display unit by exchanging the memory or by changing the memory content. For this purpose, it is advantageous if the memory is designed as an exchangeable, as an electrically programmable read-only memory or as a loadable memory.

To set different block lengths, it is advantageous if the second counter can be set by means of block length signals stored in the memory itself and thus defines the length of the subsequent block. It is particularly advantageous here if the block length signals are stored serially in the memory and are fed to the second counter for presetting. The second counter is expediently followed by a flip-flop, which is set when the second counter is carried over and whose output signal is linked to an end-of-line signal in order to advance the third counter.

For soft-scrolling capability, it is necessary that additional control signals for a pixel memory are stored in the memory. A buffer is expediently connected downstream of the memory, in which binary characters assigned to the control signals can be buffered. Further binary characters can be stored in the memory, which are assigned to video signals of markings or, for example, frames on the display unit.

In the memory, the binary characters can control signals from a variety of different types of image be saved on the display unit and called up by a switch.

• Fig. 1 ein Blockschaltbild eines mit dem Bildgenerator versehenen Datensichtgeräts,
• Fig. 2 ein Blockschaltbild des Bildgenerators,
• Fig. 3 eine Darstellung eines Bildes an einer Anzeigeeinheit,
• Fig. 4 ein Schaltbild einer Bildsteuereinheit,
• Fig. 5 Zeitdiagramme von Signalen an verschiedenen Punkten der Bildsteuereinheit.

An exemplary embodiment of the image control unit according to the invention is explained in more detail below with reference to drawings. Show it

• 1 is a block diagram of a data display device provided with the image generator,
• 2 is a block diagram of the image generator,
• 3 shows an illustration of an image on a display unit,
• 4 is a circuit diagram of an image control unit,
• Fig. 5 timing diagrams of signals at different points of the image control unit.

The data display device shown in FIG. 1 is controlled by a microprocessor MP. An interruption control IS and, on the other hand, a programmable control unit for direct memory access DMA (Direct Memory Access) are connected to the microprocessor MP. A primary memory PS, a secondary memory SS, a keyboard TA, a printer DR, a communication part KT and a display unit AE with a screen BS are connected via a data bus DB and possibly an address bus. The primary memory PS is designed as a semiconductor memory and it serves as a program memory and working memory. The secondary storage SS can be designed as a floppy disk storage and / or as a magnetic bubble storage. The keyboard TA contains keys for entering alphanumeric characters and function keys for performing various functions.

The printer DR is designed in a known manner and contains a type or a mosaic printing unit. The communication part KT is connected to a long-distance line FL and contains transmission units for sending or receiving characters.

When characters are displayed on the screen BS, code characters assigned to these characters are transmitted from the primary memory PS or from the secondary memory SS via the data bus DB to the image generator BG. The image generator BG contains a character generator that. contains data words assigned to the shape of the characters in a manner known per se. Depending on the code characters, the corresponding data words are read from the character generator and transferred to a pixel memory BP. A memory element of the pixel memory is assigned to each pixel on the screen BS. The pixel memory serves as an image repetition memory and from it the data words are read out in accordance with an image change frequency and transmitted to the display unit AE. The screen BS of the display unit AE can be designed as a screen of a cathode ray tube. In this case, corresponding video signals are generated from the binary characters stored in the pixel memory, with which, for example, the electron beam of the cathode ray tube is scanned brightly. If the screen BS is formed from individual picture elements, the video signals are supplied to these picture elements.

The characters on the screen BS are displayed line by line and the characters to be displayed are composed of pixels which are arranged on these lines.

The image generator BG shown in FIG. 2 contains a control unit ST, which, for example, is also a micro processor is trained. The control unit ST is connected on the input side to the data bus DB. When a character is displayed on the screen BS, the code character CZ assigned to this character is transmitted to the image generator BG via the data bus DB. The control unit ST switches the code character CZ through to the character generator ZG, in which data words DW associated with the shape of the character are stored. The character is formed line by line, with each line corresponding to a data word DW. In addition, address signals which are assigned to the coordinates of the character on the screen BS are transmitted via the data bus DB. These coordinates are buffered in two registers XAR and YAR.

The image generator BG contains an image control unit B, which transfers the data words DW into the pixel memory BP, reads out the data words DW from the pixel memory BP for generating the video signals VS and generating signals SV and SH for vertical and horizontal synchronization of the Display unit AE controls.

Further details of the image control unit BS are explained in more detail below with reference to FIGS. 3 to 5.

3, with the screen BS, graphic patterns, for example alphanumeric characters, can be displayed within an image field BF. A cursor SM indicates the position at which the next character is written. Writing is only possible within one writing line, which is identified by the two markings M1 and M2. For the construction of the actual picture, without the characters to be displayed, the signals SV and SH for vertical and horizontal synchronization are blanking pulses for the picture width of for example 82 characters, memory drive signals, such as request signals for the memory controller DMA and for the interrupt controller IS, and line end pulses are required. To display the markings M1 and M2 independently of the screen content, marking signals are also required, which can also be generated in the image control unit. The video signals VS for displaying the characters on the screen BS are generated in the pixel memory BP.

In the circuit diagram shown in FIG. 4, binary characters assigned to the control signals for the image structure are stored in a memory SP. It would be conceivable to provide a line of binary characters in the memory SP for each line on the screen BS. However, this would require a great deal of effort if, for example, a line would require 109 storage spaces and 318 lines could be displayed on the BS screen. For the image area BF, however, only 82 drawing spaces and 300 lines would be used, for example. However, since many lines are of the same design with regard to the image structure, not with regard to the characters to be displayed, it is expedient to combine the binary characters of the same lines into blocks and to store them in a single line of memory in the memory SP and specify how often, according to the block length, this memory line should be read out.

The memory SP is advantageously designed as a read-only memory. It can be exchangeable or can be designed as an electrically programmable read-only memory. The memory SP is addressed cyclically and a corresponding control signal is output at each of its data outputs. Two data outputs are used to control the addressing of the memory SP by a type of microprogramming, which is simultaneously stored in the memory SP.

The memory SP is addressed with the aid of three counters Z1 to Z3, the counter Z1 counting the number of characters along a line, for example 109, the memory Z2 counting the number of identical lines within a block and the counter Z3 indicating the block number.

The memory SP is followed by a buffer R designed as a register, at the outputs of which the signals SV and SH as well as the further control signals are emitted. The image control unit BS also contains a clock generator TG, which outputs clock pulses to the memory SP, the buffer memory R and the counter Z1 and also controls a buffer memory ZS, in which characters are stored by the pixel memory BP and are read out serially in order to transmit the video signal VS. produce.

In the time diagrams shown in FIG. 5, the time t is represented in the abscissa direction by the corresponding number of character clock pulses ZT and in the ordinate direction the instantaneous values of the various control signals. The signals shown in solid lines in FIG. 5 are assigned, for example, to a block which shows 12 lines on the screen BS, namely those 12 lines which are arranged approximately in the center of the screen BS and with which the markings M1 and M2 can be represented. The other blocks usually differ from this block only in that the dashed signal SV for vertical synchronization and the memory control signals DR and IN then have a different course. In addition, a block length signal BL in other blocks contains either no or a different number of pulses.

With the first count clock ZT, the first memory line is removed from the memory SP using the counter Z1 read and buffered in the buffer R. At this time, the signal SV in this block has the binary value 0 and is therefore inactive. The signal SH for horizontal synchronization still has the binary value 0, which in this case is assigned to the active state. A blanking signal A, which defines the area in which characters can be displayed on the screen BS, has the binary value 1 and is inactive. A memory control signal DR, with which the memory PS can be accessed directly, has the binary value 0 and is therefore active in order to retrieve from the memory PS the characters which are displayed using the line to be displayed. The further memory drive signal IN, which is an interrupt signal, can also be active at this point in time if soft scrolling capability is desired.

Using the counting clocks ZT, all 109 character spaces in the memory SP are read out in succession, so that the control signals shown in FIG. 5 are defined for the line to be displayed, which is defined by the lines stored in the counter Z1, and by the block number stored in the counter Z3 occur. At about the counting clock ZT17, the blanking signal A becomes active and prepares the clock generator TG to now convert the data words output from the pixel memory BP into the buffer memory ZS into the video signals VS, which are output to the display unit AE via an OR gate G1. Shortly thereafter, a marking signal MA occurs which serves to represent the writing line marking M1. This marking signal MA is also fed via the gate G1 to the display unit AE as a video signal VS in order to make the screen BS appear dark at this point. Then the signal SH assumes the binary value 1 and thus becomes inactive. It becomes active again at the ZT97 counting cycle and initiates horizontal synchronization. Then the blanking signal A becomes inactive again and blocks the screen BS for a representation of characters. A marking signal MA then occurs again in order to display the right writing line marking M2 on the screen BS.

The line end signal LE occurs at the counting clock ZT109. This switches the counter Z2 on via the OR gate G2. If the line was not the last line of the block shown, the counter Z3 is not affected. The counter Z1, on the other hand, is reset and counted up again, so that the same control signals are generated again. However, if the line shown was the last line of a block, the counter Z2, which has a fixed count length, outputs a carry signal C to a flip-flop F, whereby this is set. The counter Z3 is then advanced via the AND gate G3 and the next block is addressed.

If the next block has the same length, which corresponds to the fixed counting range of the counter Z2, again so many lines are shown until the counter Z2 emits the carry signal C and the next block is addressed. However, if the block has a smaller number of lines, for example 12, the counter Z2, if it has a fixed count length of 16, will be replaced by block length signals BL during the representation of the last line of the previous block by four block length signals BL via the AND gate G4 and the OR gate G2 is counted up, so that when the next block is read out, the carry signal C occurs after 12 signals LE and the counter Z3 is incremented. The counter Z3 has a count length of 32, for example, so that up to 32 different blocks are available for generating the control signals. The counter Z1 has a count length of 128, for example, of which only 109 are used in the present exemplary embodiment.

During the display of the last 15 lines, the control signal SV has the binary value 1 and is therefore activated in order to carry out a vertical synchronization. The signal SV is therefore shown in dashed lines in FIG. 5.

For soft-scrolling capability, the memory control signal IN briefly assumes the binary value 0 and is thus activated in order to trigger a rapid re-storage of the video information assigned to the lines.

A switch S is connected to the memory SP, with which, for example, the most significant address bit can be switched in order to trigger different images on the screen BS. When switch S is open, for example, a test image is displayed and when the switch is closed an image is built up that corresponds to the image shown in FIG. 3, in which alphanumeric characters can be displayed on the image surface BF.

Claims (13)

1. Image control unit for a data display device, in which control signals are generated which are used to build up a line-wise displayed image on a display unit, characterized in that a memory (SP) is provided in which the control signals of each line to be displayed on the display unit (AE) assigned binary characters are stored, that the binary characters of several control signals assigned to successive lines are combined to form a block and are stored by a single sequence of binary characters, that a first counter (Z1) is provided which is connected to the address inputs of the memory (SP) , which can be advanced by a character clock (ZT) and which reads the respective binary characters assigned to a line one after the other from the memory (SP), that a second counter (Z2) is provided which is generated by a line end signal (LE) stored in the memory (SP) ) and which counts and counts the number of lines of a block d that a third counter (Z3) is provided, which can be advanced by signals emitted by the second counter (Z2) and which sends the address to the memory (SP). of the respective block to be read out. 2. Image control unit according to claim 1, characterized in that the memory (SP) is designed as a read-only memory. 3. Image control unit according to claim 1 or claim 2, characterized in that the memory (SP) is designed as an electrically programmable read-only memory. 4. Image control unit according to claim 1 or claim 2, characterized in that the memory (SP) is designed as a loadable memory. 5. Image control unit according to one of claims 1 to 4, characterized in that the second counter (Z2) by block length signals (BL) stored in the memory (SP) is adjustable to the block length of the next block. 6. Image control unit according to claim 5, characterized in that the block length signals can be read out serially from the memory (SP). 7. Image control unit according to one of claims 1 to 5, characterized in that the second counter (Z2) is followed by a flip-flop (F) which is set when the second counter (Z2) is carried over and that by an AND operation (G3 ) the output signal of the flip-flop (F) with the line end signal (LE) the third counter (Z3) can be switched. 8. Image control unit according to one of claims 1 to 7, characterized in that in the memory (SP) synchronization signals (SH, SV) for controlling a screen (BS) of the display unit (AE) are stored. 9. Image control unit according to one of claims 1 to 8, characterized in that blanking signals (A) for the information to be displayed are stored in the memory (SP). 10. Image control unit according to one of claims 1 to 9, characterized in that in the memory (SP) additional memory control signals (DR, IN) for the retrieval of the display unit information from a primary memory (PS) are stored. 11. Image control unit according to one of claims 1 to 10, characterized in that the memory (SP) is followed by a buffer (R) in which the binary characters assigned to the control signals can be buffered. 12. Image control unit according to one of claims 1 to 11, characterized in that binary characters can be stored in the memory (SP), the video signals (MA, VS) of markings (M1, M2) on the display unit (AE) are assigned. 13. Image control unit according to one of claims 1 to 12, characterized in that the binary characters of control signals for the construction of a plurality of images on the display unit (AE) can be stored in the memory (SP).

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