EP0125797A1 - Verarbeitungsgerät für Unterbrechungssignale - Google Patents

Verarbeitungsgerät für Unterbrechungssignale Download PDF

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Publication number
EP0125797A1
EP0125797A1 EP84302530A EP84302530A EP0125797A1 EP 0125797 A1 EP0125797 A1 EP 0125797A1 EP 84302530 A EP84302530 A EP 84302530A EP 84302530 A EP84302530 A EP 84302530A EP 0125797 A1 EP0125797 A1 EP 0125797A1
Authority
EP
European Patent Office
Prior art keywords
input signal
data
interrupt
unit
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84302530A
Other languages
English (en)
French (fr)
Other versions
EP0125797B1 (de
Inventor
John Andrew Niblock
Jayant Patel
Dennis Fisher
Anthony Peter Lumb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gec Plessey Telecommunications Ltd Te Coventry
Gpt International Ltd Te Coventry Groot-Britt
Original Assignee
General Electric Co PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co PLC filed Critical General Electric Co PLC
Publication of EP0125797A1 publication Critical patent/EP0125797A1/de
Application granted granted Critical
Publication of EP0125797B1 publication Critical patent/EP0125797B1/de
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Definitions

  • immediate input signal means an input signal which requires urgent handling by a computer system.
  • non-immediate input signal is an input signal which does not require urgent handling.
  • control logic 3 forwards an immediate interrupt signal to the previously designated one of the computer units 30 to 3N on a respective one of the leads 60 to 6N.
  • control logic 3 may be arranged to commence a timeout once it has applied an interrupt signal on one of the leads 60 to 6N. If the read register 5 has not been addressed before expiry of the timeout then the control logic 3 is arranged to attempt to. interrupt all of the computers 30 to 3N in turn until a response is received. It is here noted that the timeout may be pre - set in the control logic 3 by the operating system by way of the data bus 9. It should also be noted that if the timeout above expires the control logic 3 will generate interrupt data of its own into the interrupt store which the computer unit successfully interrupted will read as part of its read function and which will cause an indication of the failure if required.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
EP84302530A 1983-04-13 1984-04-13 Verarbeitungsgerät für Unterbrechungssignale Expired EP0125797B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8310003 1983-04-13
GB838310003A GB8310003D0 (en) 1983-04-13 1983-04-13 Input signal handling apparatus

Publications (2)

Publication Number Publication Date
EP0125797A1 true EP0125797A1 (de) 1984-11-21
EP0125797B1 EP0125797B1 (de) 1987-10-14

Family

ID=10541038

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84302530A Expired EP0125797B1 (de) 1983-04-13 1984-04-13 Verarbeitungsgerät für Unterbrechungssignale

Country Status (8)

Country Link
US (1) US4638432A (de)
EP (1) EP0125797B1 (de)
AU (1) AU562586B2 (de)
CA (1) CA1212478A (de)
DE (1) DE3466813D1 (de)
GB (2) GB8310003D0 (de)
NZ (1) NZ207809A (de)
ZA (1) ZA842713B (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268052A1 (de) * 1986-10-22 1988-05-25 BBC Brown Boveri AG Verfahren zur Taskumschaltung nach einer Unterbrechnungsanforderung in einem Prozessorsystem
EP0431312A2 (de) * 1989-11-03 1991-06-12 Compaq Computer Corporation Multiprozessor-Unterbrechungssteuerung
US5247685A (en) * 1989-11-03 1993-09-21 Compaq Computer Corp. Interrupt handling in an asymmetric multiprocessor computer system
EP0636973A2 (de) * 1993-07-06 1995-02-01 Tandem Computers Incorporated Prozessorschnittstellenchip für Doppelmikroprozessorsystem

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816990A (en) * 1986-11-05 1989-03-28 Stratus Computer, Inc. Method and apparatus for fault-tolerant computer system having expandable processor section
US4959781A (en) * 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US5291608A (en) * 1990-02-13 1994-03-01 International Business Machines Corporation Display adapter event handler with rendering context manager
US5517624A (en) * 1992-10-02 1996-05-14 Compaq Computer Corporation Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems
US6816934B2 (en) * 2000-12-22 2004-11-09 Hewlett-Packard Development Company, L.P. Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol
US6971043B2 (en) * 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
JP4182948B2 (ja) * 2004-12-21 2008-11-19 日本電気株式会社 フォールト・トレラント・コンピュータシステムと、そのための割り込み制御方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716837A (en) * 1971-04-22 1973-02-13 Ibm Interrupt handling
US3895353A (en) * 1972-05-03 1975-07-15 Robin Edward Dalton Data processing systems
EP0012886A1 (de) * 1978-12-22 1980-07-09 International Business Machines Corporation Eingabe/Ausgabe-Steuereinheit für ein Datenverarbeitungssystem
US4330826A (en) * 1980-02-05 1982-05-18 The Bendix Corporation Synchronizer and synchronization system for a multiple computer system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3908099A (en) * 1974-09-27 1975-09-23 Gte Automatic Electric Lab Inc Fault detection system for a telephone exchange
US4270168A (en) * 1978-08-31 1981-05-26 United Technologies Corporation Selective disablement in fail-operational, fail-safe multi-computer control system
JPS5537641A (en) * 1978-09-08 1980-03-15 Fujitsu Ltd Synchronization system for doubled processor
US4371754A (en) * 1980-11-19 1983-02-01 Rockwell International Corporation Automatic fault recovery system for a multiple processor telecommunications switching control

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716837A (en) * 1971-04-22 1973-02-13 Ibm Interrupt handling
US3895353A (en) * 1972-05-03 1975-07-15 Robin Edward Dalton Data processing systems
EP0012886A1 (de) * 1978-12-22 1980-07-09 International Business Machines Corporation Eingabe/Ausgabe-Steuereinheit für ein Datenverarbeitungssystem
US4330826A (en) * 1980-02-05 1982-05-18 The Bendix Corporation Synchronizer and synchronization system for a multiple computer system

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
AFIPS CONFERENCE PROCEEDINGS, 1979 NATIONAL COMPUTER CONFERENCE, 4th-7th June 1979, New York,, vol. 48, pages 587-593, AFIPS PRESS, Montvale, New Jersey, US; K.A. ELMQUIST: "Architecural and design perspectives in a modular multi-microprocessor, the DPS-1" *
AFIPS CONFERENCE PROCEEDINGS, 1981 NATIONAL COMPUTER CONFERENCE, 4th-7th May 1981, Chicago, pages 27-40, AFIPS PRESS, Arlington, Virginia, US; A. AVIZIENIS: "Fault tolerance by means of external monitoring of computer systems" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 7B, December 1982, pages 3665-3667, New York, US; T.A. STRANKO: "Enhanced sensor tracking" *
NEUES AUS DER TECHNIK, no. 6, 1st December 1972, page 058, Würzburg, DE; "Prioritätsregister in eines Multiprozessor-Kontrolleinheit" *
PATENTS ABSTRACTS OF JAPAN, vol. 6, no. 151, 11th August 1982, page 131, E-124; & JP-A-57 075 047 (HITACHI SEISAKUSHO K.K.) 11-05-1982 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268052A1 (de) * 1986-10-22 1988-05-25 BBC Brown Boveri AG Verfahren zur Taskumschaltung nach einer Unterbrechnungsanforderung in einem Prozessorsystem
CH670714A5 (de) * 1986-10-22 1989-06-30 Bbc Brown Boveri & Cie
EP0431312A2 (de) * 1989-11-03 1991-06-12 Compaq Computer Corporation Multiprozessor-Unterbrechungssteuerung
EP0431312A3 (en) * 1989-11-03 1991-12-11 Compaq Computer Corporation Multiprocessor interrupt control
US5247685A (en) * 1989-11-03 1993-09-21 Compaq Computer Corp. Interrupt handling in an asymmetric multiprocessor computer system
EP0636973A2 (de) * 1993-07-06 1995-02-01 Tandem Computers Incorporated Prozessorschnittstellenchip für Doppelmikroprozessorsystem
EP0636973A3 (de) * 1993-07-06 1995-06-28 Tandem Computers Inc Prozessorschnittstellenchip für Doppelmikroprozessorsystem.
US5539890A (en) * 1993-07-06 1996-07-23 Tandem Computers Incorporated Microprocessor interface apparatus having a boot address relocator, a request pipeline, a prefetch queue, and an interrupt filter
US5778171A (en) * 1993-07-06 1998-07-07 Tandem Computers Incorporated Processor interface chip for dual-microprocessor processor system
US6397315B1 (en) 1993-07-06 2002-05-28 Compaq Computer Corporation Processor interface chip for dual-microprocessor processor system

Also Published As

Publication number Publication date
EP0125797B1 (de) 1987-10-14
US4638432A (en) 1987-01-20
CA1212478A (en) 1986-10-07
AU2676584A (en) 1984-10-18
NZ207809A (en) 1988-02-29
ZA842713B (en) 1984-12-24
GB2139786B (en) 1986-09-24
GB8310003D0 (en) 1983-05-18
AU562586B2 (en) 1987-06-11
DE3466813D1 (en) 1987-11-19
GB2139786A (en) 1984-11-14
GB8409719D0 (en) 1984-05-23

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