Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
  • G01N21/84—Systems specially adapted for particular applications
  • G01N21/88—Investigating the presence of flaws or contamination
  • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
  • G01N21/956—Inspecting patterns on the surface of objects
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T7/00—Image analysis
  • G06T7/0002—Inspection of images, e.g. flaw detection
  • G06T7/0004—Industrial image inspection
  • G06T7/001—Industrial image inspection using an image reference approach
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T7/00—Image analysis
  • G06T7/70—Determining position or orientation of objects or cameras
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T2207/00—Indexing scheme for image analysis or image enhancement
  • G06T2207/30—Subject of image; Context of image processing
  • G06T2207/30108—Industrial image inspection
  • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

• the invention relates generally to the inspection of semiconductor wafers during manufacture, and in particular to a method and apparatus for the automatic inspection of semiconductor wafers during manufacture to determine the quality of the post-development photoresist and post-etch material structure.
• VLSI Very Large Scale Integration
• Such inspection typically requires a method for finding defects such as relatively small feature distortions and small size particulate contaminates.
• the defects to be identified during semiconductor manufacture generally come from either the photolithographic process employed during manufacture or the properties of the photoresist with which the photolithographic process interacts.
• the mask through which the semiconductor is exposed can have acquired a defect during handling or the photoresist can develop in a non-uniform manner thereby causing a defect to occur on the semiconductor surface.
• Other defects can occur due to particulate contaminates such as dirt particles which "land" on the semiconductor wafer surface during processing. Contaminates may also result from a "dirty" developer photoresist.
• This early identification enables individual wafers containing critical defects to be disposed of at a stage prior to the completion of the manufacturing process.
• information can be employed for monitoring the various stages of the fabrication process and can significantly affect the yield of the production line and hence the cost of manufacture. For example, early detection of a defect may allow the wafer to be reworked and the defect corrected.
• inspection is performed either manually on selected semiconductor wafers or by machine.
• the manual or machine inspection processes often make decisions based only upon the relative feature differences between repeating patterns on the wafer surface.
• An object of the invention is therefore an automatic inspection method and apparatus for semiconductor wafers which reliably and automatically identify sub-micron defects on the surface of the semiconductor element during manufacture.
• Other objects of the invention are a method and apparatus for the automatic inspection of semiconductor surfaces which detect both distortions or anomolies in the geometry on the surface as well as the presence of particulate contaminates.
• a further object of the invention is a method and apparatus for the automatic inspection of wafer surfaces which operate in real time and which reduce the manufacturing cost of the fabrication process.
• the invention relates to a method and apparatus for the automatic inspection of a semiconductor wafer surface.
• the apparatus features an illumination system for illuminating the wafer surface to be inspected.
• the illumination system employs dark field illumination for highlighting the material edges of the surface.
• a scanning system is provided for forming in a storage array a representation of the spatial distribution of illumination energy reflected from the surface. This spatial distribution represents, when dark field illumination is employed, the material edges of the wafer which has been illuminated.
• the scanning system moves the wafer for scanning the inspection area' while maintaining the optical illumination and receptor system stationary.
• An edge analysis circuit automatically analyzes the reflected energy spatial distribution, which is represented in the array, for determining edge boundaries occurring on the wafer surface.
• a comparison circuit then compares the located edge boundaries (found by the analysis circuit) with a reference pattern which describes the expected geometrical layout of the wafer surface.
• the comparison circuit determines the location of boundary disagreements between the analysis circuit edge boundaries and the reference pattern description.
• the boundary disagreements are then output, for example visually shown on a display, whereby the equipment user can personally view the defects.
• the invention features a circuit employing an edge threshold level to discriminate between potential edge boundaries of different intensities, that is, to discriminate signal from noise. Thresholding acts as an amplitude filter.
• the boundaries are preferably spatially filtered (as described hereinafter) to form a more continuous edge pattern.
• the apparatus further features a circuit for classifying the boundary disagreements and in particular for providing a class for "killer defects", that is, defects which prevent proper operation of a completed semiconductor circuit.
• the apparatus further features circuitry for automatically determining, for a wafer having a repeating reticle pattern thereon (that is, a pattern formed using a reticle and which repeats on the wafer surface), whether a defect in the reticle has occurred and therefore whether the reticle should be cleaned or replaced. Furthermore, the apparatus provides circuitry for automatically repositioning the wafer surface for visual inspection of the surface at a selected boundary. In addition, circuitry is preferably provided to enable a more tolerant thereshold to be applied to matching edge corners on the wafer surface to the reference pattern.
• the invention in another aspect, relates to a method for the automatic inspection of a semiconductor wafer surface.
• the method features the steps of illuminating the wafer surface to be inspected, preferably employing dark field illumination for highlighting the edges of the surface.
• the method further features forming, in a storage array, a representation of the spatial distribution of illumination energy reflected from the surface; automatically analyzing the reflected energy spatial distribution for determining edge boundaries occurring on the wafer surface; comparing the edge boundaries found by the analysis step with a reference pattern description which describes the expected geometrical layout of the wafer surface; and then determining the location of boundary disagreements between the analysis edge boundaries and the reference pattern description.
• the boundary disagreements are then output, for example shown on a display, whereby the equipment user can view the defects.
• the method features locating potential edge boundaries on the wafer using local differences in reflection values and then employing a threshold level to determine which edge boundaries are to be maintained and stored.
• the illustrated method also features spatially filtering the edge boundaries to form a more continuous edge pattern.
• the method features classifying the various boundary disagreements, and in particular provides for a class for "killer defects", that is, defects which prevent proper operation of the semiconductor circuit.
• the method further features, in the illustrated embodiment, automatically determining, for a wafer surface having a repeating reticle pattern thereon, whether a defect in the reticle has occurred and therefore whether the reticle should be cleaned or replaced.
• the illustrated method provides for automatic repositioning the wafer surface for visual inspection at a selected boundary and for providing a more tolerant threshold to be applied to matching corner edges of the wafer to the reference pattern.
• Figure 1 is a schematic representation of the automatic inspection apparatus according to a preferred embodiment of the invention.
• FIG. 2 is a more detailed schematic of the image storage array according to a preferred embodiment of the invention.
• Figure 3 is a diagrammatic representation of the convolution functions employed in connection with a preferred embodiment of the invention.
• Figure 4 is a flow chart of the edge detection section according to a preferred embodiment of the invention.
• Figure 5 is a flow chart of the edge pruning section according to a preferred embodiment of the invention.
• Figure 6 is a flow chart of the edge comparison and report section according to a preferred embodiment of the invention.
• Figure 7 is a diagrammatic representation of a lessening of tolerance with respect to a corner edge detection;
• Figure 8 is a schematic circuit diagram of the automatic detection apparatus according to a preferred embodiment of the invention.
• an automatic inspection apparatus 10 has an optical section 12, an image storage array 13, an image processing and analysis section 14, and a display section 16.
• a semiconductor wafer 18 having a surface 20 to be inspected is mounted in a stable jig structure 22.
• the wafer surface is illuminated by the optical section 12.
• the preferred embodiment employs a 360° dark field presentation to highlight the edge structure present on the semiconductor surface. (In many applications bright field illumination can also be employed.)
• Reflected light is directed through the central image forming optics 26 of a microscope 27 (for example a Leitz Ergolus), and is focused on a photosensitive sensor 28 which may be for example a Fairchild Model CCD-133 having a 1024 x 1 linear element arrangement.
• the wafer surface is moved, by a step and repeat mechanism 30 attached to jig 22, in a direction transverse to the length of the optical array. Thereby, the image of the wafer surface scans across the sensor 28.
• the output of optical sensor 28 is stored in the storage array 13.
• the image processing and analysis circuitry 14 accesses the stored data of array 13 and processes the data to locate edge boundaries on the semiconductor wafer surface. These edge boundaries may be photoresist edge conductors, or other material edges on the semiconductor surface. Circuitry 14 can be implemented in either hardware, software, or a combination of the two. When a software implemention is employed, illustrated circuitry 14 is implemented using a general purpose digital computer, such as a Digital Equipment Corporation Model PDP-11/23 computer.
• the image processing and analysis section 14 determines the locations of the edge boundaries on the wafer, smoothes and links those boundaries to form a more continuous edge pattern, and compares the edge boundary locations with a reference pattern of the design structure of the wafer surface. Any distortions from or disagreements with the expected pattern are flagged and become potential boundary disagreements. Each of the possible boundary disagreements is preferably classified and a disagreement list results therefrom.
• the group of boundary disagreements resulting from the analysis of a scanned frame by the image processing and analysis section is displayed, for example on a visual display.
• the visually presented information can describe the class and location of the defects or can automatically display the actual defects for visual inspection.
• the present invention can be employed for monitoring a VLSI semiconductor fabrication.
• integrated circuits are fabricated by forming the circuit directly on a silicon crystal substrate.
• the substrate is typically a circular wafer, having a diameter of between three and six inches, and on each wafer will be fabricated several hundred complete circuits of the same type.
• Each complete circuit is on a die or chip which is generally rectangular in shape, several millimeters on a side.
• the wafer is scribed to obtain the individual die for packaging or integration onto a more complex circuit.
• Each of the die patterns is typically made by using either a mask or a reticle.
• the term "mask" is used to denote a patterned target which contains the patterns of all of the die on the wafer.
• the mask is generally a one-to-one image of the entire wafer and when a wafer is exposed through a mask, the entire wafer is effectively exposed at once.
• the term "reticle" is generally used to denote a patterned target which contains the pattern of at most a few die on the wafer. In the limit, the reticle may contain the pattern for only one die on the wafer.
• the entire wafer is exposed by a step and repeat process. That is, one part of the wafer is exposed; the wafer is then stepped in a known direction; and the exposure is then repeated. By continuing the process, the entire wafer is covered with a repeating pattern.
• a defect in the reticle affects every group of die on the wafer made with that reticle. Since the VLSI technology is moving the industry away from masks and toward reticles, the inspection of the wafer surface for reticle defects is extremely important.
• the semiconductor wafer 20 is assumed to have thereon a developed photoresist pattern.
• the photoresist pattern is being automatically inspected for defects such as geometric anomalies. Geometric anomalies occur, for example, as a result of errors or defects on the mask or reticle, particles which settle on or near the mask or reticle during exposure, particles which settle on the wafer during exposure, or development induced defects.
• the inspection process is designed to detect and locate dimensional errors, which can occur when the photoresist pattern is geometrically correct but has certain critical dimensions which are out of specification, and particulate contaminates, that is, particles which fall onto a patterned photoresist.
• the developed photoresist is illuminated, with dark field illumination in this preferred embodiment of the invention, for highlighting the edge information available on the wafer surface, and a digital image of the area to be inspected is acquired.
• the digital image is processed to generate or derive a description of the area being inspected in terms of the edges in the area.
• the edge information is presumed to completely define the boundaries of the photoresist and/or particulate contaminates lying thereon.
• the edges can be closely spaced to define conductors or can be spaced much further apart to define active areas such as the base or emitter of a transistor. With respect to particulate contaminates, the edges are spaced apart somewhat and form, generally speaking, a relatively ragged closed loop.
• the illustrated illumination system is a reflective or incident dark field illumination system which directs light energy from a source 40 onto a beam splitter 42 and through a mirrored collar 44 of the microscope 27 and onto the wafer surface 18 at an oblique angle.
• the incident illumination is then reflected back into and is collected by the microscope optics 26.
• the illuminated wafer surface image is focused by the microscope objective and subsequent optics 48 (if needed) onto the surface of the optical sensor 28.
• the wafer Because the wafer is opaque, it can only be imaged by light which is reflected from the surface. In dark field illumination, light is directed onto the object at a highly oblique angle through the mirrored collar 44 which surrounds the image forming lens system 26 of the objective. The light energy from source 40 is directed toward beam splitter 46 in an annulus configuration toward the sample semiconductor wafer. An opaque blocking member 50 is employed to prevent energy from being directed into the microscope image forming optics 26.
• the effect of using dark field illumination is to provide a highly specular reflection from an optically smooth, mirror-like surface such as is typical of the polished surface of an unpatterned silicon wafer.
• an optically rough surface that is, one in which there are material discontinuities
• the reflection is diffuse and in that case, reflective rays are scattered in all directions.
• Some of the reflected energy is captured by the microscope objective and the object appears bright at these areas.
• the unpatterned or optically smooth silicon substrate surface appears dark while the photoresist edges and particulate contaminates appear bright. (If bright field illumination had been employed, the silicon substrate would have appeared bright, while the photoresist edges would have appeared dark. Later image processing would proceed accordingly.)
• the dark field image is formed by the microscope optics 26, and further focusing optics 48 if needed, at the image plane of the electro-optical sensor or detector 28.
• the sensor converts the reflected illumination incident thereon into an electrical signal which is later scaled and quantized into a discrete set of levels. Each level represents a small interval of illumination power and in the illustrated invention the total illumination range has two hundred and fifty-six levels.
• Sensor 28 is preferably a solid state sensor and in the illustrated embodiments is a linear photoresistive array. An alternate sensor could be a television-type vidicon camera.
• the linear array approach thus employs a solid state image sensor having a plurality of distinguishable elements arranged in a rectilinear array.
• the sensor 28 provides 1,024 distinguishable elements arranged in a straight line linear array.
• the area of the wafer imaged upon the array (a scan line) is thus spatially quantized into the 1,024 picture elements (pixels).
• Each pixel in the illustrated embodiment corresponds to 0.5 microns on the wafer surface.
• the illumination falls onto the array for a preset integration time during which light produced charge is collected in each of the distinguishable elements. At the end of the integration time, the charge accummulated at each element is read out and transduced into a voltage signal.
• the voltage is then scaled (or amplified) and quantized with the result being a spatial (1,024 elements) and voltage (256 levels) quantization of the line of the image.
• relative movement must be provided between the array and the wafer. Either the array must be moved across the stationary image or the image must be moved across the stationary array (a combination of the two could also be employed).
• the image is moved across the array.
• a mechanical stage 52 supporting the wafer 18 and jig 22 moves in a direction perpendicular to the array line under the control of a step and repeat mechanism.
• An alternate approach which reduces the movement required to produce a two-dimensional image of a selected surface area, is to employ an area array solid state sensor such as the Fairchild Model CCD-221. This sensor has a 488 x 380 element array.
• the storage array 13 has first and second random access memory (RAM) elements 54 and 56, one of which is being filled by the sensor 28 of scanning system while the other memory is being processed by the image processing and analysis section 14.
• Switches 58 and 60 which control the flow of data into and from elements 54 and 56, are preferably digital gating structures.
• the raw image data stored in memory array 13 represents the image as a two-dimensional matrix of numbers.
• the "numbers" represent the image intensity across the spatial extent of the wafer surface being scanned.
• the image processing and analysis circuitry operates upon this raw image data to derive a description of the image in terms of potential edge boundaries (the edge finding procedure). Thereafter the edge boundary data (which identifies potential edge boundaries) is pruned or massaged to eliminate false boundaries and "clean-up" true boundaries (edge boundary pruning) . Finally the edge boundaries are compared against a reference pattern, and defects or disagreement boundaries are recorded (edge boundary comparison).
• the process of edge finding is implemented using convolution masks (or filters) operating along orthogonal axes.
• these masks align with the horizontal and vertical axes with which most of the edges of the image will also align.
• a photoresist or other material edge when illuminated with dark field illumination, produces a bell-shaped light intensity distribution (intensity as a function of distance) in a direction perpendicular to the edge.
• the edge runs parallel to one orthogonal axis, the light distribution profile will be exclusively directed parallel to the other orthogonal axis.
• An optically rough particle (such as a contaminant) will produce, in response to dark field illumination, a signal waveform (representing light intensity versus distance), having a rising and a falling edge plus an intermediate region of relatively constant high intensity.
• a peak finding convolution pattern w is designed to provide a zero crossing when the peak of an intensity distribution is crossed.
• l i represents a new sequence of numbers created by convolving an original sequence of numbers (h i ) with the weighting sequence w i corresponding to the convolution mask.
• the second convolution mask W a step finding function, provides a data set for finding the edge boundaries of a particle contaminant.
• a similar convolution approach is employed; however, the convolution mask is modified to provide a zero crossing where the edge has the appearance of a step with relatively wide pateaus extending from the step in both directions.
• the step finding convolution mask is designed to provide zero crossings at the center of an edge bounding a relatively large area or plateau.
• the results of using these convolution masks with a photoresist edge structure and a particle contaminate edge structure are illustrated in Figure 3.
• the acquired image represented by block 60 is first spatially smoothed to help eliminate the noise "ripples" inherent in the digitization process of a noisy analog signal.
• the spatial filter provides low pass filtering which also helps eliminate invalid peaks due to system noise.
• the spatial filtering, represented by block 62 is applied along each of the orthogonal axes.
• a Gaussian function could be used, however it is much simpler to approximate the Gaussian by a weighting function having weights: 1/4, 1/2, 1/4.
• the value of each picture element intensity is replaced by an average equal to 1/4 of the previous value, plus 1/4 of the succeeding value, plus 1/2 of the present value.
• the smoothed data resulting from the operation indicated by block 62 is preferably stored in the same memory as the acquired raw image data.
• the smoothed image is convolved in both the horizontal and vertical directions with the peak finding and step finding convolution functions respectively. This is indicated at blocks 64, 66, 68, and 70.
• the reuslt of the respective convolution processes is then searched for possible zero crossings. This is indicated at blocks 72, 74, 76, and 78.
• the strength of the crossing is, for example, set equal to the peak amplitude of the other convolution function for that axis and within a small range of pixels of the zero crossing.
• the strengths are stored, as indicated at 80, 82, 84, and 86, preferably in the same storage array which originally stored the raw image data.
• the strengths resulting from the step finding convolution are made positive. This is indicated at 88 and 90. Also, the zero crossings for the peak finding convolution result are reviewed by eliminating invalid zero crossings, i.e., those zero crossings representative of noise. These are generally weak zero crossings which do not have associated with them strong related zero crossings. This is represented by blocks 92 and 94 of Figure 4.
• the edge detection process by eliminating weak zero crossings of the peak finding convolution, discriminates between noise and potential photoresist edges.
• the strength measurement discriminator in the illustrated embodiment, is a threshold value fixed prior to processing and in general depends upon the materials being employed. In other embodiments, the threshold value can be varied dynamically during processing to take account of local variations in both noise and signal strength as a result of the semiconductor fabrication process.
• the strength measurement for a zero crossing is, in the illustrated embodiment, the maximum value of the step finding convolution output within plus or minus one picture element of where the peak finding convolution output goes through zero.
• the strength of the step finding convolution will not be "confused" with noise since it is not a peak finding element but instead effectively locates inflection points, that is, the position at which the first derivative of the image signal passes through a minimum or maximum.
• the strengths are coded at 96, 98, 100, and
• Coding can be accomplished by allocating to each word of the array (one word representing one pixel), preassigned bits representing the vertical and horizontal axes, and the peak finding or step finding strength result. Alternately, the word can be divided to indicate whether the strength stored there is strong or weak, is the result of a step or peak finding convolution, and is for the horizontal or vertical axis.
• the horizontal and vertical strengths for the peak finding convolutions, and the horizontal and vertical strengths for the step finding convolutions are summed. This accommodates edge boundaries which are neither horizontal nor vertical but at an angle oblique thereto such as at a 45° angle.
• the stored and coded zero crossing strengths are then analyzed to detect valid edge boundaries and to discard invalid boundaries. This is referred to as the pruning process and is indicated at block 106 of Figure 4.
• the step finding zero crossing is eliminated (Block 112). This occurs because it is assumed that the step finding zero crossing is erroneous, and it occurred in connection with and in the middle of a relatively wide photoresist area. Similarly, there might occur between two distant step finding convolution zero crossings, a peak finding convolution zero crossing. This can occur for example in the middle of a particle contaminant. In this case, the peak finding convolution zero crossing would be discarded (Block 110) although it is not generally necessary for later processing to do so.
• edge boundaries because the discarded zero crossings will have been "zeroed".
• the edge boundaries which remain however may or may not be complete and continuous.
• the gap may occur because the edge point had a small strength.
• these apparent discontinuities are smoothed and filtered by filling in the gaps between edge boundary points so that the edge is continuous along its boundary. This is indicated at block 116 of Figure 5.
• the "pruned" edge boundaries are available to a comparison circuit as indicated at block 118.
• the "pruned” edge boundaries are aligned with a reference pattern (block 120).
• the reference pattern is provided from a reference data source such as a computer aided design (CAD) tape which is processed at 122 to provide data to the reference pattern, block 120.
• CAD computer aided design
• the alignment, indicated by block 124, is achieved primarily by "dead reckoning". That is, two relatively long edge boundaries, one parallel to one orthogonal axis and the other parallel to the other orthogonal axis, are selected in the reference pattern and the corresponding edge boundaries are "found" in the pruned edge boundary data memory.
• the alignment search is carried out over a very small section of the memory and can be performed in a short time.
• the result of the alignment search is to provide horizontal and vertical offsets between the reference pattern and the stored data.
• edges in the reference block and the stored data are compared.
• Corresponding points, that is, points appearing in the same location in both patterns are eliminated from the storage array 13, and, in the illustrated embodiment, non-corresponding points, that is, points in the reference pattern which do not appear in the storage array are written into the storage array at their appropriate locations. Points in the storage array which do not have a corresponding point in the reference pattern are kept.
• the matching indicated by block 126 is completed, there results in the storage array 13 a set of disagreement boundaries which define distortions and particle contaminants, if any, on the image surface.
• the disagreements are examined at block 128; and as a result, the disagreements or defects are classified.
• One particularly important class of defects or disagreements are those disagreements which materially affect proper operation of the semiconductor circuitry. These defects, if critical, are called
• killer defects and can be determined by defined areas of activity whose location can be provided by the reference pattern 120. Thus, a particle contaminant at a location spaced apart from the operating circuitry of the semiconductor wafer does not normally affect circuit operation whereas a contaminant on the circuit itself may cause the circuit to fail. In either case, a report is compiled, in the illustrated embodiment at block 130, and is provided to the display device 16 of Figure 1.
• the "defined areas of activity" provided by reference pattern 120 will relate not only to activity on the layer being formed, but also to the effect of a defect on a subsequently, or previously formed layer.
• the CAD tape or other reference source which is processed at 122 to provide the multi-layer activity volumes in which a defect can have an adverse effect, and in particular where the defect is properly classified as a "killer defect".
• a major concern which occurs during the comparison process of block 126 relates to the physical processes by which corners are formed during the semiconductor fabrication process. Due to the frequency response of the optical system employed in forming the photoresist corners, and further due to the effects of the chemical process by which the photoresist is layed down and developed, corners generally become rounded so that a truly "squared" edge does not occur. As a result, corners would almost always be "flagged” as a defect absent any provision for loosening the tolerance of the system at the photoresist corner. As a result, referring to Figure 7, a loosening of the tolerance, or a window, is provided at the corner 132 defined by the reference pattern. The tolerance is illustrated by dashed lines 134, which allow the physical phenomena of a rounded corner represented by the dot-dash line 136 to be accommodated without being flagged defect. Clearly other tolerance windows could be employed although the illustrated window is particularly easy to implement.
• the illustrated embodiment can also be employed to implement automatic focusing of the optical system, by testing for the "sharpness" of the image at the optical sensor 28.
• the automatic focusing mechanism adjusts the microscope optics to provide as sharp an image as possible at the image plane of sensor 28. This can be accomplished for example by mounting the microscope illumination system on a jig as indicated by dotted lines 140 (Fig. 1) and moving the jig up or down under the control of a drive mechanism 142.
• the drive mechanism 142 is controlled by the image processing and analysis section 14.
• the step and repeat mechanism 30 can, under the control of the image processing and analysis section 14, reposition the semiconductor wafer to provide for a visual review of a defect on the semiconductor surface by the apparatus operator.
• the defect review can be accomplished using either the dark field illumination employed in connection with edge detection or bright field illumination for visual inspection.
• edge detection it is the trend in today's VSLI technology to use a repeating pattern on a semiconductor wafer surface.
• the apparatus herein is arranged to review the disagreements at block 128 for repeating patterns to find repeating defects, if any. Repeating defects are then reported as a possible and likely reticle defect which must be cured, for example, by cleaning the reticle or replacing it with. a new element. This is accomplished at block 128 of Figure 6.
• the entire analysis system can be implemented in either hardware or software.
• hardware is employed since the throughput and process time can be decreased by use of special purpose hardware such as an array processor employing a pipeline processing approach. Nevertheless, a software implementation can also be satisfactory.
• the flow charts of Figures 4, 5, and 6 have been implemented in using a Digital Equipment Corporation PDP-11/23.
• the software programs, including interactive operating system programs, are attached hereto as Appendix A. While the programs themselves do not form part of the invention, they do provide one particular implementation of the concepts and structure of the invention. In addition, the invention can be implemented in hardware as described in detail hereinafter.
• the automatic inspection system of the invention can also be implemented in hardware.
• the hardware embodiment employs a process control and sequence timing circuit 148 adapted to provide an orderly transition of the data from the microscope optics illustrated by block 150 to the eventual report generation and display.
• the process control and timing circuit can be a hardwired apparatus, as is well known in the art, adapted to fix the timing of a plurality of elements or can be a special or general purpose computer which provides greater flexibility in changing the timing and control of the apparatus.
• the image from the illumination optics 150 is provided through the sensor element which forms part of an image acquisition section 152.
• the image acquisition provides the scanned image for storage in a dual memory storage array 154 corresponding to image storage array 13.
• the scanning of the wafer is under the control of a wafer scan control circuit 156 as is well known in the art which is interactive with the process control and sequence timing circuit 148.
• the image, once stored, is continually modified within the storage element so that minimal additional RAM storage is needed. Therefore, the raw data stored in memory 154 is filtered using a spatial filtering network 158.
• the spatial filtering network is adapted to sequentially read out the raw data from memory 154, and to effectively low pass filter it as described above using its digitial hardwired circuitry.
• the smoothed image data is convolved, by a convolution circuit 158 operating under the control of the control and timing circuit 148, for each of the convolution functions described in connection with Figure 3 so that a peak finding and step finding data is read into memory 154.
• the convolution circuit 158 is preferably built around an array processor employing pipelined processing.
• the convolved (or filtered) data in this illustrated embodiment, is then "pruned" for noise and similar anomalies by an edge pruning circuit element 162.
• the edge pruning circuit removes invalid edge points using the criteria described above in connection with Fig. 5.
• an edge boundary comparison circuit 164 also operating under the control of the process control and timing circuit 148, compares the data stored in the image storage array 154 with the reference model stored in a reference memory circuit 166.
• the output of the comparison is stored back in storage array 154.
• This stored information is then analyzed by the classification network 168.
• This network after reference to memory 166, maps the boundary disagreements into classes depending in part upon the effect of the defect upon semiconductor operation, and provides detailed information regarding the defect and its classification to a report generating circuit 170.
• the report generating circuit provides a suitable format for either a visual or printed display.
• a display element 172 can thus be either a visual monitor which is preferred or a printer, or both.
• a CAD model is stored in memory, for example a disk memory 174 and the memory 174 is read and processed by a controller 176 for providing to the memory 166 both a suitable definition of the edge boundaries and a definition of the active volumes of the final semiconductor structure which can be severely and adversely affected by defects in or near those reference boundaries.
• the key to proper operation of the hardware is to provide sufficient timing and control via the process control and timing network 148 to enable the various elements to operate in a sequential manner and to use pipeline array processing as needed, such as, for example, the time consuming convolution process which involves a series of time consuming multiplications.
• MASTER TASK MASTERT.TSK
• BUFF contains: TASK1 , TASK2 , 0 or -2 . #ARGS , argl , arg2 , .. argn , subrout ine
• WTLOS ( 2 , MASK ) end define DELAY integer DTIM MRKT$ ( 23. , DTIM * 6 , 1 , 0 ) WAIT ( 23. ) end
• SYNC1 ( TAPTR ) SYN1 ;
• BUFF ( 1 ) SYN2 CLEAR ( SYNC1 ( TAPTR ) ) CLEAR ( SYNC2 ( TAPTR ) ) with TASK ( TAPTR ) SDRCS ( TAS ( 0 ) , TAS ( 1 ) BUFF bytewd 16. 2 ) 0 0 ) ;; ioerr WAIT ( SYNC2 ( TAPTR ) ) increment TAPTR atterm endif end
• BUFF ( 1 ) cmdcnt - 2 mvstr ( ARG . ptr ( BUFF ( 2 ) ) )
• VAITLO wait for flag from any task
• MEM_REC M_IPSDB Memory blocks for model access.
• MEM_REC M_EDGE for creation of EDGE IMAGE Region
• MEM_REC M_MATCH for creation of IMAGE region for MATCHT and DEFECT.
• ASCRS PARNAM , PARNM
• WNDAPR urshift ( APR , 5 ) ; APR in the upper byte
• WNDSZ WNSIZ ; MUST BE LESS THAN 4K
• WNDST 202K ; MAP IT AND ALLOW WRITE ACCESS
• CREGION REGNAM , PARNAME , REGSIZ ) create a 32kwords dynamic region.
• CWNDOW VADDR , REG ID , 200K , 0 ) ; create a window at VADDR absolute address ; of 4k words. Map it at the offset 0 in the ; region end
• ID DES_RET integer DES_SITE ; (1..15) integer DES_FRAME ; integer DES_ILLUM ; Bright , Dark integer DES_MAGNF ; (1x .. 500x) integer OES_LAYER integer DES_PATTERN
• INITRG ( "IPSDBR” , “GEN “ , 200K , 160000k )
• VIDEOT 41. 42.
• VIDEOT Initialize the Video Monitor Task VIDEOT print "MATCHT is being connected.”
• CVSAVE integer FNAME CALL "VIDEOT” "VSAVE” FNAME end define CFILLREG integer FEDGE CALL “VIDEOT” "FILLREG” FEDGE end define CREGFILL integer FEDGE CALL “VIDEOT” "REGFILL” FEDGE ' end define CWFMAP integer X0 Y0 SZ CALL "VIDEOT” "WFMAP” 0 X0 Y0 SZ ; DI SPLAY_WAFER_MAP end define CDISPMODEL integer X0 Y0 CALL “VIDEOT” "DISPMODEL” 0 X0 Y0 end define CBNDRCTS i n t eg er X0 Y0 CALL "VIDEOT” "BNDRCTS” 0 X0 Y0 end define STF-VIDEOT ; disconnect "VIDEOT” task and attached to the terminal integer TERM
• WTASK ( "CEDGET” ) end define STP-EDGET ; disconnect "EDGET” task and attached to the terminal integer TERM
• WTASK ( "STAGET” ) end define CCALSTG calibrate the stage
• VTASK ( "STAGET” ) end define CSTAGEM ; stage move according to inspection plan
• DISPLAY_INSFECTION_DIE CUR_LAYER : DES_LAYER with LAYERS ( CUR_LAYER ) with DTL_LAYER_REV ( #_REVS - 1 ) print "Mask revision number is .... " , str ( L_REV_# ) print "Mask layer description is .. " , str ( L_DESCR ) print "View screen to see preconfigured inspection die” print " The blue reticle is the reference die” print " The red reticles are the die to inspect" end
• ROW . INSP_R ( 0 ) : ROW
• VDT_IN "Hit (return) to continue " )
• ROW : INSP_R ( 1 ) : ROW
• MOD_FRAME : CUR_FRAME end define GMLRGR ; gat and display the model and register local char PNAME ( 30. ) print str ( MDLBASE ) , tp 60k , #i 2 , MOD_FRAME , ".MDL' #n encode ( FNAME )
• VDT_IN ( "Please contemplate and evaluate! !" ) end define CONFIRM_INSPECT iter #_SITES with INSP_FR ( i ) iter #_FS with F_DEFCTS ( i ) if ( #_DFCTS )
• loop loop end integer NOFRAMES &&& FOR TESTING PURPOSE ONLY integer NOSITES ; &&&
• I -MODE CONFIRM mvstr ( 'CLN , IMBASE ) mvstr ( 'RCL . RIMBASE )
• CUR_ILLUM : BRIGHT if ( YESNO ( "Do you want to calibrate the stage ? " ) )
• IPLANE 252.
• DSLLU RED + BLUCL + I , 255 , RED + BLUGL + I , 255 )
• DSLLU ( BLUE + BLUGL + I , 255 , BLUE + BLUGL + I , 255 )
• MVBYWD BYTE_ARRAY , BYTE_OFFSET , WORD_ARRAY , #_BYTES ) *> entry MVBYWD mov (msp ) + r0 ; Get number of bytes to transfer. mov (msp ) + r1 ; Get pointer to word array. mo v (msp > + r2 ; Cet pointer to byte array add (msp ) + r2 ; plus the offset.
• MVBYWD ( BYTE_ARRAY , BYTE_OFFSET , WORD_ARRAY , #_WORDS ) *> entry MVWDBY mo v (msp ) + r0 ; Get number of bytes to transfer. mov (msp ) + r1 ;Get pointer to word array. mov (msp) + , r2 ; Get pointer to byte array add (msp ) + , r2 ; plus the offset.
• Integer WNDADR VIRTUAL BASE ADDRESS IN TASK'S VIRTUAL SPACE integer WNDSZ ; WINDOW SIZE IN 32WORD BLOCKS integer WNDREG ; REGION ID integer WNDOFF ; OFSSET IN REGION IN 32 WORD BLOCKS integer WNDL ; LENGTH TO MAP IN 32WORD BLOCKS integer WNDST ; WINDOW STATUS WORD integer WNDSRB ; SEN/RECEIVE BUFFER ADDRESS endrecord
• ASCRS ( REGNAM , REGNM ) drop
• ATRG ( RGDB ) ; create the region and attache it ioerr end
• WNDAPR urshift ( APR , 5 ) ; APR in the upper byte
• WNDSZ WNSIZ ; MUST BE LESS THAN 4K
• WNDST 202K ; MAP IT AND ALLOW WRITE ACCESS CRAW ( WNDB ) ; CREATE AND MAP THE WINDOW IOERR END
• the region can be viewed as 256 x 256 area where each byte corresponds to a (X,Y) set of coordinates.
• the main access routnes will be:
• MPPIX ( X , YREL , PIXVAL ) gives the value of the pixel given the relative coodinate in the window and the X. * > entry MPPIX mov (msp)+ , r2 ; value to be written mov (msp)+ , r1 ; Y-coo mov (msp)+ , r0 ; X-coo swab r1 ; Y * 256.
• ⁇ * define REMAP integer integer YCOO if ( not elm ( YCOO , YLOW , YHIGH > )
• YLOW : Ishift ( urshift ( YCOO , 5 ) , 5 ) ; YCOO / 32.*32.
• YHIGH : YLOW + 31. ; 32 rasters per window
• MAPW ( WNDB ) ; remap the window in the same region endif
• mov r1 , -(msp) Push active address add # so WNDAPR , (msp) ; + WNDAPR offset (WNDB pointer) .
• mov # base MAPW , r3 Load base address of MAPW routine. jsr pc , xeq ; Execute the MAPW (Remap).
• ⁇ * FILLREC ( IMFILE ) fills the region with the data provided from the image file IMFILE.
• RED, GREEN, and BLUE are the memory locations in the Lexidata memory at which the lookup tables start for each color. ALL is a wildcard to effect action for each color.
• TPLANE, GFLANE, and IPLANE are arguments for DSCHAN, the channel enabling primitive.
• CL maps the intensity index (GLIN) into the intensity value (CLOUT) to be represented by the Lexidata.
• GS sets a ramped lookup table with a variety of arguments. GS takes as input (1) no arguments (2) 1-3 color names (RED, GREEN, or BLUE) or (3) ALL.
• GS will set up the black-and-white lookup table, from 0 to 255.
• TEMP1 1024 * 1 iter 256 CL ( TEMP1 + I , I' ) loop ( TEMP2 ) loop eIse iter cmdcnt iter 256
• the first two arguments are the indices to set to the maximum and the third is the color table in which to work.
• STEP -- a limited version of RECT in which all indices are divided into two regions, instead of three.
• the first input is the index before which all values should be xero and after which all values should be set to 255 NOTA BENE: the first input is a RELATIVE index, from 0 to 255, not from 0 to 4095.
• DSCHAN TPLANE , GPLANE , IPLANE
• DSCLR TPLANE + GPLANE
• DSLLU 0 , 0 , 255 . 255
• WDOAS DCHAD ( ARGl ) ) WDOAS ( ARG2 ) WDOAS ( -- ARG3 ) WDOAS ( BYTEWD ( ARG5 , ARG4 ) ) END *>
• ⁇ * Define DELAY function using RSX Mark Time directive and Wait for Global Event Flag directive. make 'MRKTS rsxcall bytewd ( 5 , 23. ) make 'STSES rsxcall bytewd ( 2 , 135. )
• Subroutne 22 BADDR does a conversion of the 16-bit virtual address supplied as argument into a full 22-bit physical address of the O-bus.
• the MMU user map registers are used for this purpose so this subroutine must be used in a magic/I environment linked to the I/O page.
• input 16 bit word representing the virtual address
• output long(32-bit) word representing the 22-bit address as foil owing :
• CONTROLLER build by Zvi Orbach More bit manipulations might be required if used with other devices, calling sequence: long 22b i taddr s
• mov (msp ) , r 0 get the virtual address mov r0 , r1 ; rol r0 ; isolate the APF ( Active Page Field ) rol r0 rol r0 rol ro ; bic # 177770k , r0 ; in r0 asI r0 .
• APF Active Page Field
• PHYADR 22ADDR ( BUFF ) poke ( 130000k + X0 - 1 , DBR ) poke ( 114000k + Y0 . DBR ) poke ( -- XL / 2 , WCR ) ; poke ( -- ( XL * YL ) , WCR ) poke ( lsword ( PHYADR ) , BAR > poke ( 0 , DBR ) poke ( msword ( PHYADR ) + 1 , CSR ) end
• VDRAW integer FNAME X0 Y0 local integer BUFPTR IMAGEFN ( FNAME ) VCH : open ( PNAME , 'r ) BUFPTR off do Y0 , Y0 + 255. if ( rds ( VCH , OUTLN , 256. ) ⁇ > 256. ) print "WARNING: Unexpected end of file" exit
• VDRAW ( IFN ) end define VSAVE integer FNAME local integer BUFF1 BUFF2 with M_EDCE
• RDLN ( BUFF2 , 128. , 256. , i , 1 )
• DMAW ( OUTLN , X0 , 256. , Y0 + i - 128. , 1 )
• ⁇ * Define executive directives to be used for tasking with Control *> make 'WAIT rsxcall bytewd ( 2 , 41. ) make 'CLEAR rsxcall bytewd ( 2 , 31. ) make 'READ rsxcall bytewd ( 2 , 37. ) make 'SET rsxcall bytewd ( 2 , 33. ) make 'RCVDs rsxcall bytewd ( 4 , 75. ) make 'SDATs rsxcall bytewd ( 5 , 71. )
• BUFF contains. TASKl , TASK2 , 0 or -2 , #ARGS , arg1 , arg2 , .. argn , subroutine
• BUFFER Receive data from that task we are connected to and put it in a buffer Call: RECEIVE ( BUFFER ) Note: if these routines are overlaid , BUFFER must be global. The buffer must be at least 15 words. BUFFER contains:
• RCVDs ( 0 , 0 , BUFF ) ;; ioerr iter 2
• EXT DISPMODEL EXT WFMP EXT BLBDISP ; blob bounding rectangles EXT HAROLD ; &&& integer STPFLAG integer VIDCBF ( 15. )
• parameter MAX_#_ENT 20 ; Maximum # of permissible entities.
• parameter *POINTS 25 ; Maximum # of points permitted within ; an entity .
• integer MPX0 , MPY0 the origin x,y of the wafer map on the screen integer MPRAD ; the map size on the screen real MPSCL ; # pixel/micron integer XPI YPI ; the pit ches integer STH AVW ; str and ave sizes integer DIH DIW ; die sizes integer XROW YROW ; current row to display integer GLDI E ; the gray level at which the die boundaries are display ed integer GLCIR ; the gray level of the circle integer CROSX ( MAX_RETICLES ) ; x location of the marker for the die being ins pected integer CROSY ( MAX_RETICLES ) ; y location of the marker for the die being ins
• YROW : MPY0 * ROW * YPI end define GTORG integer X0 Y0 SZ with FLAT_TO_ORIGIN
• DSVEC ( XDI + DIV , YR0 , XDI + DIW , YR0 + DIH , GL ) end define WFMAP
• GLDIE GRNGL
• GLCIR : GRNGL with INSP_PLN with HEADER with INSE_DATA_BASE
• MPSCL float ( MPRAD / ( float ( WAFER_SZ ) * 500.0 )
• XPI : f i x ( D I E_X * MPSCL )
• YP I : fix ( DIE_Y * MPSCL ) with LAYERS ( CUR_LAYER ) with DTL_LAYER_REV ( #_REVS - 1 ) with L_RETICLE with RETICLE_DIE
• GTORG ( X0 Y0 MPRAD ) iter #_DIE_ROWS with WAFER_MAP ( i ) CROWCOO ( i , IST_D_* )
• DSCIR ( ( X0 + MPRAD ) , ( Y0 + MPRAD ) , MPRAD , GLCIR ) with REFERENCE_DIE GROWCOO ( ROW , CLMN ) : GET COORDINATES OF REFERENCE_DIE BOX ( XROW , YROW , BLUGL ; DRAW IT IN RED with L_INSPECTION ; GET RETICLES TO INSPECT iter #_TO_INSP with INSP_R ( i )
• GROWCOO ( ROW , CLMN )
• CROSY ( i ) YROW t DIH / 2 - 3
• BOX ( XROW , YROW , REDGL ) loop
• DREGION end define DISPX integer X0 Y0 GL DSSAO ( X0 Y0 GL 0 1 ) DSTXT ( "X" ) end define SHOWDIE
• DISPX ( CROSX ( PRIMARY ) , CROSY ( PRIMARY ) , 0 ) DISPX ( CROSX ( CONFIRM ) , CROSY ( CONFIRM ) , REDGL ) endif
• DREGION end define DMESSAGE address MESS
• VDRAW JOE 32. 256.
• PAUSE end define LMAG
• VDRAV ( "RNF03 32. 0 )
• AADD ( DBF ( 26 ) , DBF ( 18 ) , DBF ( 18 ) ) ; hor . conv
• AADD ( DBF ( 26 ) DBF ( 26 ) , DBF ( 17 ) ) ; ⁇ DBF ( 26 )
• AADD ( DBF ( 26 ) DBF ( 26 ) , DBF ( 19 ) )
• AADD ( DBF ( 30 ) , DBF ( 29 ) , DBF ( 26 ) ) ; VO — > DBF ( 29 )
• AADD ( DBF ( 26 ) , DBF ( 16 ) , DBF ( 20 ) ) ;
• AADD ( DBF ( 30 ) , DBF ( 17 ) . DBF ( 19 ) ) ; vert . conv .
• AMULS ( DBF ( 30 ) , DBF ( 30 ) , 5 ) ; with even mask.
• AADD ( DBF ( 30 ) , DBF ( 30 ) , DBF ( 26 ) ) ; VE — > DBF ( 30 )
• AADD ( DBF ( 26 ) , DBF ( 30 ) . DBF ( 26 ) ) ;
• AHIAB FCBCHN . 8. , N
• ACHN ( ptr ( N ) , FCBCHN . 500. ) AHIAB ( BOT , DBF ( 31 ) , 128. ) AUPAK ( DBF ( 20 ) , DBF ( 31 ) ) ADNSN ( DBF ( 20 ) )
• ADBDB ( DBF ( 36 ) DBF ( 29 ) )
• ADBDB ( DBF ( 37 ) DBF ( 30 ) )
• ADBDB ( DBF ( 34 ) DBF ( 35 ) )
• AHIAB FCBCHN . 8. , N
• AFRUN ( DBF ( 9 ) , DBF ( 10 ) , DBF ( 11 ) , DBF ( 12 ) , ⁇
• AABHI TOP , DBF ( 15 ) , 256. , 0 )
• MVWDBY ( TOP , 0 , TOP , 256. )
• DOEDGE COUNT off INIT_DBF Initilixe AP DBF values ZERO_DBF READ INIT xvser ( WNDADR , 256. )
• MAPW ( WNDB ) ptr ( LINE_REC ) : WNDADR + 1024.
• APRUN ( DBF ( 9 ) , DBF ( 10 ) , DBF ( 11 ) , DBF ( 12 ) , ⁇
• AABHI TOP . DBF ( 15 ) , 256. , 0 )
• AABHI TOP , DBF ( 15 ) , 256. , 0 )
• MVWDBY TOP , 0 , TOP , 256.
• loop mvrer ( TOP , 256. )
• This routine sets up the buffers required by the AP .
• AUFAK ( DBF1 , DBF ( 31 ) )
• ADNSN ( DBF1 ) ; Determine Normalizing Coeff.
• AHIAB FCBCHN , 8. , N
• AXCHN 8.
• ARLDB 8. ) end define ZERO_DBF

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