EP0089720B1 - Single transistor, single capacitor mos random access memory - Google Patents

Single transistor, single capacitor mos random access memory Download PDF

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Publication number
EP0089720B1
EP0089720B1 EP83200370A EP83200370A EP0089720B1 EP 0089720 B1 EP0089720 B1 EP 0089720B1 EP 83200370 A EP83200370 A EP 83200370A EP 83200370 A EP83200370 A EP 83200370A EP 0089720 B1 EP0089720 B1 EP 0089720B1
Authority
EP
European Patent Office
Prior art keywords
line
row
field plate
bit line
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83200370A
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German (de)
English (en)
French (fr)
Other versions
EP0089720A2 (en
EP0089720A3 (en
Inventor
Joannes Joseph Maria Koomen
Roelof Herman Willem Salters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0089720A2 publication Critical patent/EP0089720A2/en
Publication of EP0089720A3 publication Critical patent/EP0089720A3/en
Application granted granted Critical
Publication of EP0089720B1 publication Critical patent/EP0089720B1/en
Expired legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Definitions

  • the invention relates to a memory array, comprising:
  • MOS random access memories In usual metal oxide semiconductor (MOS) random access memories (RAMS) as known from the U.S. Patent 4050061 and utilizing a single capacitor and a single MOS transistor in a memory cell, one side of the capacitor, the side referred to as the field plate, is conventionally connected directly to the power line, and the sensing is accomplished by charging and discharging of the capacitor on the opposite side through a switch driven by the word line into a bit line that is precharged to a certain voltage level.
  • the small change in the bit line voltage due to charging and discharging of the capacitor is sensed in a sense amplifier against a reference signal.
  • the reference signal is roughly one half the value of the cell signal caused by the charge and discharge of the cell capacitor, so the sensed signal is one half the cell signal.
  • the invention has for its object to provide a memory array of single transistor, single capacitor memory cells having an improved operation and reliability due to the sensed signal in the memory array, which sensed signal is roughly twice the cell signal sensed in known conventional memories having single transistor, single capacitor memory cells.
  • the field plate is not connected directly to a fixed potential, but instead is precharged to a voltage level exactly equal to that to which the bit line is precharged. Furthermore, the field plate is connected to the other input of the sense amplifier, the bit line being connected to the normal input in the usual way.
  • the charge and discharge of the cell capacitor not only causes a small voltage change on the bit line, but also a small equal and opposite change on the field plate. Therefore, the cell signal is increased by the amount of signal on the field plate, and will be roughly twice the cell signal resulting from the conventional arrangement. As in the conventional arrangement, this cell signal is sensed against a reference signal which is roughly one half the amount of the cell signal, and thus the sensed signal is twice that of the sensed signal obtained in the conventional arrangement.
  • EP-A-0,037,262 From the EP-A-0,037,262 it is known to arrange memory cells between a bitline BL and a power supply line having variable potential.
  • the gate of the access transistor of the cell is connected to a corresponding wordline.
  • a dummy cell is connected to the corresponding bitline BLB and substrate.
  • Such arrangement increases the differential signal to be sensed by the sense latch, which is connected to the two bitlines BL and BLB. Further a rather critical timing of several clock- and control pulses is necessary to achieve the increased differential signal.
  • FIG. 1 there is shown a memory array of an M number of rows of field plate lines FP(1, ..., M) and bit lines BL(1, ..., M).
  • Each row contains an N number of memory cells, each of which cells includes a capacitor 10 and a transistor 12 coupled in series between the field plate line FP and bit line BL, respectively.
  • one side of the memory cell capacitor 10 is connected directly to the field plate line FP, and the other side of the capacitor 10 is connected to or disconnected from the bit line BL through the memory cell transistor 12.
  • the gates of the transistors 12 in a given column are all connected to one of a number of word lines WL(1,..., N), there being one word line WL for each of the N columns of memory cells.
  • the word lines WL may be selectively actuated by signals fed from a column decoder 14 so that upon actuation of a given word line WL, all of the transistors 10 in the column will be connected to the bit lines BL.
  • the field plate lines FP are each connected to or disconnected from a power supply rail 16 through a precharge transistor 18.
  • Each of the bit lines BL are also connected or disconnected from the power supply rail 16 through another precharge transistor 20.
  • the precharge transistors 18 and 20 are switched on or off by a signal applied to a precharge line PC connecting the gates of the transistors 18 and 20.
  • Each row contains a reference cell which includes a reference capacitor 22 and a reference transistor 24 connected in series between the bit line BL and the field plate line FP. It is essential that opposite to the cell configuration 10, 12 the reference cell 22 is connected to the bit line and the reference transistor 24 is connected to the field plate line FP.
  • the gates of the reference transistor 24 are connected to a reference word line RWL.
  • a switching transistor 26 is connected between each reference cell node RCN (1,..., M), the junction between reference capacitor 22 and reference transistor 24, and a ground line GND.
  • a reference cell preset line RPC connecting all the gates of the switching transistors 26 is used to reset the reference cells to zero volts.
  • the capacitance of the reference cell capacitor 22 has a value 1/2C that is 1/2 the value C of the capacitance of the memory cell capacitor 10.
  • Each field plate line FP of a row is coupled to one node 1 of a sense amplifier through a connecting transistor 28.
  • each bit line BL of a row is coupled to the other node 2 of the sense amplifier through another connecting transistor 30.
  • the sense amplifier is a cross coupled transistor pair 32 and 34. The sides of the sense amplifier transistors opposite the nodes 1 and 2 are connected to a sense amplifier pulldown line ⁇ s .
  • the sense amplifier nodes 1 and 2 of only one row are connected to a pair of data buses DB1 and DB2 by a decoded pulse selected from M number of lines ⁇ y (1,..., M), emanating from a row decoder 36. This is accomplished by feeding the decoded pulse to the gates of transistors 38 and 40 connected between the sense amplifier nodes 1 and 2 and the data bus pair DB1 and DB2.
  • the data buses DB1 and DB2 connect to data input/output circuitry 42.
  • the field plate lines FP, bit lines BL,the data bus pair DB1 and DB2 and the sense amplifier common node ⁇ s are connected to the supply voltage V cc appearing on the power supply rail 16, in this example equal to 5V.
  • V cc the supply voltage appearing on the power supply rail 16
  • the precharge line PC is at zero volts.
  • the reference cell reset line RPC is switched to zero volts, isolating the reference cell capacitor nodes RCN(I) through RCN(M).
  • the wordline WL(I) will be selected by the column decoder 14 and together with the reference word line RWL switched to 7.5V. Assume that the transistor threshold voltage is 1V.
  • the memory cell node CN (J, I) has a voltage of zero volt.
  • the cell node voltage will be raised to the bit line voltage. Because both the field plate line and the bit line capacitances (C F p and C BL ) are much larger than the memory cell capacitance C (J, I) the memory cell capacitor charge CV cc will be dumped on the field plate line FP(J), and the same but opposite charge will be extracted from the bit line BL(J).
  • the cell node CN (I, J) has a voltage of 5 volts prior to event time t 2 .
  • the memory cell capacitor (I, J) has no charge and thus will neither dump nor extract charge on the field plate line FP(J) and from the bit line BL(J).
  • the reference cell capacitor22 will still dump its charge on the bit line BL(J) and extract the same amount from the field plate line FP(J).
  • lines ⁇ 1 and ⁇ 2 still have 7.5 volts. So also the voltage V(1) and V(2) on sense amplifier nodes 1 and 2 on each row differ by a voltage ⁇ AV according to the contents of the cell of the row and selected by column line I.
  • Both the field plate line FP and bit line BL of each row are disconnected from the sense amplifier nodes 1 and 2 at event time t 3 . See Figure 2A (c and d). At this time lines ⁇ 1 and ⁇ 2 are switched to zero volt.
  • the voltage difference between the field plate line FP and bit line BL and also between the sense amplifier nodes 1 and 2 will stay constant but all nodes will experience a small but identical voltage dip because of capacitive coupling.
  • the voltage difference AV between V(1) and V(2) on nodes 1 and 2 on each row is sensed and amplified by the sense amplifier by applying a proper "pull down" signal ⁇ s on the common node of all sense amplifiers, as shown in Figures 2A and B (e.g., h, j and k). Then after sufficient time (t s ) the bit lines BL of all rows are reconnected to node 2 by line ⁇ 2 . Just prior to time t s the data bus pair DB1 and DB2 are disconnected from the power supply V cc and are floating at 5V.
  • nodes 1 and 2 of row J are connected to the data bus pair DB1 and DB2 by the decoded pulse ⁇ y (J).
  • the status of the data bus pair voltages is further transmitted to the output pin by the data 10 circuitry, see Figures 2A and B (f-1).
  • the field plate line FP voltage must not be allowed to drop considerably below the power supply voltage, or else the cell charge will be lost.
  • the write cycle is similar to the read operation in all the rows but the selected row (J).
  • event time t s the write operation of row (J) is the same as the read operation.
  • the status of the data bus pair DB1 and DB2 voltages is a result of the cell contents.
  • the status of the data bus pair DB1 and DB2 is forced from the data 10 circuitry 42 and further transmitted to the cell (J, I). From then on the write operation is again similar to the read operation.
  • the memory array configuration is only one possibility out of several possibilities. This is the case also for the mode of operation and the timing of the waveforms. Moreover, there are other alternatives for the reference cell arrangement and the type of sensing circuitry, which will be apparent to those skilled in the art.
  • Figure 3 shows a prior art memory cell and sense amplifier arrangement in which a memory cell includes a capacitor 50 and a transistor 52 connected in series across a field plate line FP and a bit line BL. Both the field plate line FP and bit line BL are connected directly to a power supply rail 54 that is furnished a supply voltage V cc .
  • the transistor 52 has its gate actuated by the word line WL(I), signifying selection of the Ith cell in an array.
  • the bit line BL is interrupted and has its memory cell side connected to one node 1 of a sense amplifier including cross coupled transistors 56 and 57 and has the other side connected to the other node 2 of the sense amplifier SA.
  • a reference cell On the second node 2 of the bit line BL a reference cell includes a reference capacitor 58 and a reference transistor 60 connected in series between the field plate line FP and bit line BL.
  • the reference capacitor 58 has a capacitance value 1/ 2C and the memory cell capacitor 10 has a capacitance value C.
  • the reference cell node RCN is connected in series with a transistor 62, the gate of which is coupled to a reference cell preset line RPC.
  • a reference word line RWL couples to the gate of the reference cell transistor 60.
  • the bit line capacitance is shown labelled C BL .
  • a sense amplifier pull down line ⁇ s is connected to the common side of the sense amplifier transistors 56 and 57.
  • the memory cell extracts the charge CV cc from the bit line BL, because C BL is C. This causes a voltage drop of -AV on the bit line BL.
  • the reference cell extracts the charge 1/2 CV cc from the bit line connected to the other side, node 2 side, of the sense amplifier SA, causing the voltage on this bit line to drop -1/2 ⁇ V. So the net voltage difference between the bit lines and across the sense amplifier is 1/2 AV after word line selection.
  • this signal is sensed and amplified by applying a proper pulldown pulse ⁇ s .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
EP83200370A 1982-03-19 1983-03-17 Single transistor, single capacitor mos random access memory Expired EP0089720B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US360088 1982-03-19
US06/360,088 US4420822A (en) 1982-03-19 1982-03-19 Field plate sensing in single transistor, single capacitor MOS random access memory

Publications (3)

Publication Number Publication Date
EP0089720A2 EP0089720A2 (en) 1983-09-28
EP0089720A3 EP0089720A3 (en) 1986-10-15
EP0089720B1 true EP0089720B1 (en) 1990-02-28

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ID=23416535

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83200370A Expired EP0089720B1 (en) 1982-03-19 1983-03-17 Single transistor, single capacitor mos random access memory

Country Status (8)

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US (1) US4420822A (es)
EP (1) EP0089720B1 (es)
JP (1) JPS58171789A (es)
KR (1) KR910000967B1 (es)
CA (1) CA1194234A (es)
DE (1) DE3381265D1 (es)
IE (1) IE54669B1 (es)
MX (1) MX155995A (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE151898T1 (de) * 1984-01-05 1985-11-21 Mostek Corp., Carrollton, Tex. Verfahren und anordnung zur ausgleichung einer speicherzelle.
JPS60239993A (ja) * 1984-05-12 1985-11-28 Sharp Corp ダイナミツク型半導体記憶装置
JPS60258795A (ja) * 1984-06-04 1985-12-20 Sharp Corp ダイナミツク型半導体記憶装置
JPS60258793A (ja) * 1984-06-04 1985-12-20 Sharp Corp ダイナミック型半導体記憶装置
JPS60258796A (ja) * 1984-06-04 1985-12-20 Sharp Corp ダイナミツク型半導体記憶装置
JPS60258794A (ja) * 1984-06-04 1985-12-20 Sharp Corp ダイナミツク型半導体記憶装置
JPS6177193A (ja) * 1984-09-25 1986-04-19 Toshiba Corp ダイナミツク型メモリ
JPS6196594A (ja) * 1984-10-16 1986-05-15 Toshiba Corp 半導体記憶装置
JPS61144795A (ja) * 1984-12-17 1986-07-02 Mitsubishi Electric Corp 半導体記憶装置
JPS61178795A (ja) * 1985-02-01 1986-08-11 Toshiba Corp ダイナミツク型半導体記憶装置
JPH0731909B2 (ja) * 1986-06-20 1995-04-10 富士通株式会社 半導体記憶装置の動作方法
JPH0250393A (ja) * 1988-08-12 1990-02-20 Toshiba Corp ダイナミック型ランダム・アクセス・メモリ
GB9007793D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Dram cell plate and precharge voltage generator
KR960009959B1 (ko) * 1994-03-11 1996-07-25 현대전자산업 주식회사 디램 셀 접속방법
KR100275107B1 (ko) 1997-12-30 2000-12-15 김영환 강유전체메모리장치및그구동방법
JP2000187990A (ja) * 1998-12-24 2000-07-04 Nec Corp センスアンプ回路及びそれを用いた記憶装置並びにそれに用いる読出し方法
DE10017368B4 (de) * 2000-04-07 2005-12-15 Infineon Technologies Ag Verfahren zum Betrieb eines integrierten Speichers

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US3760381A (en) * 1972-06-30 1973-09-18 Ibm Stored charge memory detection circuit
JPS5088944A (es) * 1973-12-10 1975-07-17
GB1523752A (en) * 1974-08-28 1978-09-06 Siemens Ag Dynamic semiconductor data stores
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
US4031522A (en) * 1975-07-10 1977-06-21 Burroughs Corporation Ultra high sensitivity sense amplifier for memories employing single transistor cells
US4050061A (en) * 1976-05-03 1977-09-20 Texas Instruments Incorporated Partitioning of MOS random access memory array
DE2739086C2 (de) * 1977-08-30 1986-01-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Betrieb eines dynamischen Halbleiter-Speicherelementes und Schaltungsanordnung zur Durchführung des Verfahrens
JPS5948477B2 (ja) * 1980-03-31 1984-11-27 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPS58171789A (ja) 1983-10-08
KR910000967B1 (ko) 1991-02-19
IE54669B1 (en) 1990-01-03
CA1194234A (en) 1985-09-24
MX155995A (es) 1988-06-13
EP0089720A2 (en) 1983-09-28
EP0089720A3 (en) 1986-10-15
DE3381265D1 (de) 1990-04-05
US4420822A (en) 1983-12-13
JPH0256756B2 (es) 1990-12-03
IE830569L (en) 1983-09-19
KR840004292A (ko) 1984-10-10

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