EP0055570A2 - Circuit logique - Google Patents

Circuit logique Download PDF

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Publication number
EP0055570A2
EP0055570A2 EP81305982A EP81305982A EP0055570A2 EP 0055570 A2 EP0055570 A2 EP 0055570A2 EP 81305982 A EP81305982 A EP 81305982A EP 81305982 A EP81305982 A EP 81305982A EP 0055570 A2 EP0055570 A2 EP 0055570A2
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EP
European Patent Office
Prior art keywords
circuit
fet
logic
gate
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP81305982A
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German (de)
English (en)
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EP0055570A3 (fr
Inventor
Koichi Nishiuchi
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Fujitsu Ltd
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Fujitsu Ltd
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Priority claimed from JP55183430A external-priority patent/JPS57106234A/ja
Priority claimed from JP55183447A external-priority patent/JPS57106235A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0055570A2 publication Critical patent/EP0055570A2/fr
Publication of EP0055570A3 publication Critical patent/EP0055570A3/fr
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type

Definitions

  • This invention relates to a logic circuit, and more particularly to an integrated logic circuit which uses a transistor as a load element.
  • MOS integrated circuit forms have heretofore been used, each form having its particular features and merits and demerits.
  • an inverter circuit which is the basic gate of a logic circuit, is provided by connecting a load element to a single driving transistor.
  • an MOS transistor is ordinarily employed as the load element.
  • Various aspects of performance and other features are provided by the different sorts of load transistors, operating mechanisms, etc., and the different forms of MOS integrated circuits are classified in accordance with those aspects and features.
  • E/E type circuit an enhancement - enhancement type circuit
  • E/D type circuit an enhancement - depletion type circuit
  • C-MOS circuit a complementary MOS circuit
  • An E/E type circuit is a circuit which uses enhancement-mode MOS transistors for both a driving transistor and a load transistor. As illustrated in Fig. 1A of the accompanying drawings, which is a circuit diagram, the gate terminal of a load transistor 2 is usually fixed to a power source potential.
  • an E/D type circuit employs an enhancement-mode MOS transistor as a driving transistor and a depletion-mode MOS transistor as a load transistor.
  • Fig. 1B of the accompanying drawings which is a circuit diagram, the gate terminal of a load transistor 2 is connected to an output terminal 3.
  • the E/E type and E/D type circuits are very simple in their circuit arrangement, and they are constructed of only MOS transistors, of either n-channel or p-channel polarity, and they are suitable for IC implementation and are extensively utilised. With these circuits, however, as will be apparent from the above explanation of their operation, in order to provide an L level of a sufficiently low magnitude at the output when the driving transistor is "on", the current of the load transistor needs to be set at a low magnitude, below about 1/10 of the current of the driving transistor.
  • the load transistor is normally in the "on” state in the above E/E type and E/D type circuits. Accordingly, in a gate circuit in which the driving transistor is "on", load current normally flows from the power source potential on to the ground side, and power is normally consumed in order to maintain a logical status. Especially in recent years, high-speed operation has been required together with large-scale integration. In such circuits, operating current level needs to be made high, so that power consumption is increased. In its turn, power consumption has become even the most important factor limiting the scale of integration.
  • FIG. 2A of the accompanying drawings is a circuit diagram of a C-MOS circuit. This circuit is so arranged that transistors of both polarities, an n-channel MOS transistor 1 and a p-channel MOS transistor 2, are symmetrically connected. An output terminal 3 is led out from the node between the drains of the two transistors, whilst an input terminal 5 is connected to the gate terminals of the two transistors. In operation, when the input is of H level, the n-channel transistor 1 is "on”, and the p-channel transistor 2 is "off", so that L level appears at the output.
  • the C-MOS circuit In contrast when the input is of L level, the n-channel transistor 1 turns “off” and the p-channel transistor 2 turns “on”, so that H level appears at the output. In this manner, in the C-MOS circuit, in either of the "on” and “off” states of the gate, one of the two transistors ' is “off” and a current path from the power source to ground level is not formed. Accordingly, the C-MOS circuit has the feature of very low power consumption. Regarding the operating current, currents of equal values alternately flow through the n-channel and p-channel transistors during the "on” and “off” states of the gate as illustrated in Figs. 2B and 2C.
  • both the charging and discharging processes of a load capacitance 4 can be performed with large currents, and a C-MOS circuit can offer improved switching speed. Since, however, a C-MOS circuit requires transistors of both polarities, n-channel and p-channel as stated above, its manufacture usually becomes very complicated, and a decrease in the available percentage (manufacturing yield), and a rise in cost, etc. are inevitable.
  • a logic circuit comprising a first logic gate, comprising at least one logic gate circuit having a plurality of logical input terminals, and a second logic gate, comprising at least one logic gate circuit to which a logical output signal of the first logic gate is applied, the second logic gate having at least one driving field-effect transistor (FET), and load FET's at least equal in number to the logical input terminals of the first logic gate, the said at least one driving FET being connected between a logical output terminal of the second logic gate and one power-source terminal, and having its gate terminal connected to receive the logical output signal of the first logic gate means, the load FET's being connected between the logical output terminal of the second logic gate and another power-source terminal, and having their gate terminals connected with corresponding logical input terminals of the first logic gate means.
  • FET field-effect transistor
  • a logic circuit having a plurality of unit logic gate circuits, each unit logic gate circuit comprising at least one driving field-effect transistor (FET) means and at least one load FET means, the driving and load FET means being in series between supply voltage-feeding terminals, a signal output end of one unit logic gate circuit being connected to an input terminal of the driving transistor means of another unit logic gate circuit, a signal input end of the said one unit logic gate circuit, capable of affording an inverted signal at a signal output end thereof, being connected to an input terminal of the load transistor means in the said other unit logic gate circuit, characterised in that the load FET means is composed of an enhancement-mode FET and a depletion-mode FET whose sources, drains and gates are respectively connected in common.
  • FET driving field-effect transistor
  • An embodiment of this invention can provide a logic circuit of high operating speed and low power consumption, and can further provide a logic circuit of high operating speed and low power consumption which is capable of multistage connection.
  • An embodiment of this invention provides a logic circuit in which an output of a first logic circuit having a plurality of inputs is applied to a first input of a second logic circuit, and a plurality of input signals entering the first logic circuit are applied to a plurality of second inputs of the second logic circuit, whereby high operating speed and low power consumption can be provided.
  • An embodiment of the present invention can further provide a logic circuit in which FET's connected to a power source consist of an enhancement-mode FET and a depletion-mode FET having their sources; drains and gates connected in common, respectively, whereby the logic circuit is capable of multistage connection.
  • FIG 3 is a diagram of a known inverter circuit which has a high operating speed.
  • Q 1 designates a driving MOS transistor, and T 1 a load MOS transistor. While both the transistors are of the enhancement mode here, the load transistor T 1 may alternatively be of the depletion mode, as will be described later.
  • G 1 indicates a gate circuit at the preceding stage for applying a signal to the inverter circuit.
  • the output signal terminal of the preceding-stage gate circuit G 1 is connected to the gate terminal of the driving transistor Q 1 , whilst the input signal terminal of the preceding-stage gate circuit G 1 is connected to the gate terminal of the load transistor T 1 .
  • complementary input signals are applied to the gate terminals of the respective transistors Q 1 and T 1 with a phase shift which corresponds to the propagation delay time of the preceding-stage gate circuit G 1 .
  • the driving and load transistors Q 1 and T 1 are connected in series with one another between a power source voltage (V DD ) feed terminal and a ground terminal in a conventional fashion.
  • V DD power source voltage
  • the junction between the two transistors, namely, the node between the drain terminal of the driving transistor Q 1 and the source terminal of the load transistor T 1 is used as a signal output terminal.
  • the relationship between levels is one of inversion between the level at point B, being the signal input end of the inverter circuit, and the level at point C, being the signal output end, so that inverting operations are attained.
  • the operation of the circuit is that, with either of the input levels(H or L), one of the transistors Q 1 and T 1 is in a non-conductive state steadily without fail. This indicates that, in the steady state, current flowing from the power source voltage (V DD ) feed terminal to the ground terminal is substantially null, only an infinitesimal leakage current flowing during non-conduction between the two terminals.
  • V DD power source voltage
  • the power consumption of the circuit of Figure 3 is very low.
  • the circuit of Fig. 3 has an ideal operation, similar to that of a C-MOS circuit, as a switching circuit. Further, a-C-MOS circuit needs transistors of both polarities, n-channel and p-channel, and requires isolation between the elements, etc., resulting in a manufacturing process of considerable complexity and a low density of integration. In contrast, the circuit of Figure 3 can be constructed of transistors of a single polarity. Therefore, the circuit of Figure 3 is superior to a C-MOS circuit so far as ease of manufacture and packaging density are concerned.
  • This push-pull type circuit is apparently similar in arrangement to the above logic circuit.
  • This push-pull type circuit is employed in an output buffer, etc.
  • This circuit is so arranged that an input signal from a signal input end is inverted by an inverter circuit and the inverted input signal is applied to the gate terminal of an MOS transistor on the load side.
  • one of a driving transistor and a load transistor is normally held in a non-conductive state, and the other in a conductive state.
  • power consumption is reduced, or load drivability is enhanced.
  • the push-pull type circuit needs an added inverter circuit and is clearly different from the simple arrangement of Figure 3 in which an inverted signal is obtained from the input end of the preceding-stage gate circuit.
  • the signal which is applied to the gate terminal of the load transistor has a phase lag corresponding to the delay time of the inverter circuit, with respect to the input signal to the driving transistor.
  • the phase shift relationship is the reverse of that of the circuit of Figure 3.
  • the load transistor turns “on” and then the driving transistor turns “off” in the circuit of Figure 3, whereas the driving transistor turns “off” and then the load transistor turns “on” in the push-pull type circuit described above.
  • both the load transistor and the driving transistor can be turned"off” in this manner, which indicates that the change of output from L level to H level is slow.
  • the circuit of Figure 3 has a superior operating speed characteristic as compared with the push-pull type circuit or with the conventional E/E type or E/D type circuit and even as compared with the C-MOS circuit.
  • the high operating speed of the circuit of Figure 3 is based not only on the phase shift relationship described above, but also on the fact that charging and discharging currents for a load capacitance during switching transient periods can be made large. The details of the reason for this will be apparent from the following description of transient operation.
  • Figure 4 is a time chart showing potential variations at points A, B and C in the circuit of Figure 3 and showing the variation of the potential difference A-C between point A and point C.
  • an operation is taking place when the preceding-stage gate circuit G 1 is connected to a gate circuit of the further preceding stage having the same arrangement as that of the circuit of Figure 3.
  • the point A is at L level.
  • the point B being the signal input terminal of the inverter circuit in Figure 3, is at H level. Accordingly, the point C at the output end becomes L level, and the potential difference A-C between the gate and source of the load transistor T 1 is 0 (zero).
  • this level change precedes by a time interval t 1 , corresponding to the delay time of the preceding-stage inverter circuit G 1 , the timing at which the point B, being the signal input end, starts to shift from H level to L level.
  • a time interval t 2 in which the point B shifts to L level and the driving transistor Q 1 turns "off” the level of the output end or the point C remains low.
  • the potential difference between the gate and source of the load transistor T 1 is at high level, and the load transistor T 1 is in the conductive state.
  • the gate potential of the load transistor T 1 becomes lower than the level of the source potential thereof, namely, the potential of the point C, and this transistor falls into a perfectly non-conductive state.
  • the level of the point B or the gate terminal potential of the driving transistor Q 1 rises during a time interval t 5 , charges in the load capacitance are discharged through the driving transistor Q 1 having reached the conductive state, and the level of the point C, being the output end, rises during a time interval t 6' Meantime, the load transistor T 1 is perfectly non-conductive. Therefore, the driving transistor Q 1 in the "on” state discharges the stored charges of the load capacitance rapidly, thereby to lower the level of the output end point C at high speed.
  • a signal the inverse of the input signal to the driving transistor is applied in advance to the gate terminal of the load transistor T 1 , whereby the charging and discharging of the load capacitance are quickly effected to achieve a high-speed switching operation.
  • Such operation is basically similar to C-MOS circuit operation, and charging and discharging currents of the load capacitance at switching can be made to achieve values which are, for example, 10 or more times greater than in the E/E type circuit or the E/D type circuit.
  • the circuit of Figure 3 can make the charging and discharging currents greater immediately after the initiation of charging and discharging of the load capacitance, and it can realise an operation of higher speed.
  • the phase of the gate input signal to the load side transistor lags the delay time component provided by the inverter circuit. Therefore, the effect of increasing the charging and discharging currents of the load capacitance during transient operations does not occur at all.
  • each of the time intervals t 1 - t 6 corresponds to a delay time per gate stage.
  • the preceding-stage gate circuit G 1 or the preceding-stage gate circuit anterior thereto has the same arrangement as that of the logic gate circuit in Figure 3, its delay times t 1 , t 2 or t 41 t 5 will be identical to the delay times t 3 , t 4'
  • the load transistor T 1 is an enhancement-mode MOS transistor, it may equally well be of depletion mode.
  • the load transistor is of the depletion mode, a steady state in which current flows through the load transistor steadily is provided, but charging capability for the load capacitance is further enhanced and a still higher operating speed can be realised.
  • the inverted signal is impressed on the gate terminal of the load transistor before the input signal is applied to the gate circuit, and at switching, the conductance of the load transistor is changed in advance in directions suitable for the rapid charging and discharging operations of the load capacitance, whereby a high-speed operation is achieved.
  • the circuit of Figure 3 has the ideal operating mechanism in which the driving and load transistors switch “on” and “off” alternately as in the C-MOS circuit, and it has the special feature of high-speed operation at very low power consumption as compared with the E/E type circuit and the E/D type circuit.
  • the circuit of Figure 3 since it can be constructed of transistors of only a single polarity, it does not involve the problems of complicated manufacturing processes, reduced density of integration due to a requirement for isolation between the elements, and malfunctions attributed to parasitic thyristor action, etc., as with a C-MOS circuit. Accordingly, the circuit of Figure 3 has ideal characteristics and properties as a logic integrated circuit.
  • circuit of Figure 3 is an inverter circuit which is the basic gate of logic circuit, a logic gate circuit with a plurality of inputs having an AND function and an OR function is needed in order actually to perform complicated logical functions. To apply the circuit of Figure 3 to a multi-input logic gate circuit, special contrivances are further required.
  • a 2-input NOR gate circuit in which the circuit of Figure 3 is applied is shown in Figure 5. Although the number of inputs is two in the case of Figure 5, it is to be understood from the ensuing description that the arrangement can be extended to a multi-input arrangement having three or more inputs.
  • Q 2 and Q 3 designate driving transistors which are connected to ground side in parallel with one another
  • T 2 and T 3 designate load transistors which are connected to the power source (V DD ) side in series with one another.
  • all these transistors are enhancement-mode MOS transistors.
  • G 2 and G 3 designate preceding-stage gate circuits which apply signals to the inputs m and n of the 2-input NOR gate respectively, and which are illustrated as inverter circuits in this case.
  • the output terminals m and n of the preceding-stage gates G 1 and G 2 are respectively connected to the driving transistors Q 2 and Q 3 , whilst the inputs a and b of the preceding-stage gate circuits G 2 and G 3 are respectively connected to the gate terminals of the load transistors T 2 and T 3 .
  • the output terminal X of this NOR gate circuit is provided at the node between the drains of the driving transistors Q 2 and Q 3'
  • FIG. 6 a 2-input NAND circuit in which the circuit of Figure 3 is applied is shown in Figure 6. Also in regard to Figure 6, although only two inputs are shown, it is a matter of course that the number of inputs can be readily increased to three or more.
  • Q 4 and Q 5 are enhancement-mode MOS driving transistors which are connected in series, whilst T 4 and T 5 are load transistors which are connected in parallel between a power source terminal VDD and an output terminal X.
  • Q 4 and Q 5 represent preceding-stage gate circuits, the output ends m and n of which are respectively connected to the gates of the driving transistors Q 4 and Q 5 being the signal input ends of the NAND circuit and the inputs a and b of which are respectively connected to the gate terminals of the load transistors T 4 and T 5 .
  • logical signals which are opposite in level (H or L) are applied respectively to the driving elements and the load elements.
  • transient signals are applied to the load elements earlier in time than the signals are applied to the driving elements, by an interval corresponding to one logic gate stage.
  • the circuit arrangement of Figure 6 operates in steady state with signal statuses as indicated in Table 3 below, and it will be understood that a NAND function is provided. Except for transient operation, a transistor in the "off" state is always interposed between the supply voltage V DD and the ground potential, so that the power consumption becomes very low. Further, charging and discharging of load capacitance can proceed quickly during the transient operation, so that the switching operation is carried out at high speed.
  • Figure 7 shows the circuit of a first embodiment of the present invention, being an inverter circuit in which a 2-input NOR gate circuit G 6 is a preceding-stage gate circuit. Even in a case in which the preceding-stage NOR gate circuit G 6 has three or more inputs, an arrangement embodying the present invention may be provided which is similar to the arrangement of Figure 7.
  • Q 6 is a driving transistor which is operated by the output of the NOR gate G 6 .
  • T 6 and T 6 1 are load transistors which are connected in parallel with one another and the gate terminals of which are respectively supplied with the inputs b and a of the preceding-stage NOR gate G 6 .
  • the load elements T 6 and T 6 ' are supplied with two signals which precede in time an input signal applied at a point m, being the input end of the present inverter circuit, by a component (time period) corresponding to one stage of the NOR gate G 6 , and at least one of which signals is inverted with respect to the signal at point m. Accordingly, as will be apparent from the following table 4 indicative of the logic operations of the present circuit, any of the driving transistor Q 6 and the load transistors T 6 and T 6 ' is infallibly in the "off" state in a path extending from a supply voltage V DD to the ground potential, and the circuit operates so as to block the current path:
  • FIG. 8 As another example of connection from a multi-input gate, a second embodiment of the present invention, in which an inverter is driven with outputs from a 2-input NAND gate, will be described with reference to Figure 8. It will be readily understood that the example of Figure 8 can of course be extended to an arrangement whose preceding-stage is a multi-input NAND gate having three or more inputs.
  • Q 7 is a driving transistor
  • T 7 and T 7 ' are load transistors
  • G 7 is a 2-input NAND gate circuit.
  • load transistors equal in number to the inputs of the preceding-stage gate circuit may be disposed in such a manner that the input terminals of the preceding-stage gate circuit are respectively connected to the gate terminals of the load transistors.
  • the preceding-stage gate circuit is a NOR circuit
  • tha load transistors are connected in parallel with one another, and when it is a NAND circuit, they are connected in series.
  • Figure 9 shows a third embodiment of the present invention in which preceding-stage circuits are a 3-input NOR circuit G 8 and a 2-input NOR circuit Gg and which provides NOR OR logic between the outputs of the NOR circuits G 8 and G 9 .
  • the drains and sources of load transistors T 8 , T 8 ' and T 8 " are respectively connected in common.
  • the gates of the load transistors T 8 , T 8 ' and T 8 " are respectively connected to input terminals c, d and e which are connected to the inputs of the NOR circuit G 8 .
  • drains and sources of load transistors T 9 and T 9 ' are respectively connected in common, and the gates thereof are respectively connected to input terminals g and f which are connected to the inputs of the NOR circuit G 9 .
  • the drains and sources of driving transistors Q 8 and Q 8 ' are respectively connected in common, and the gates thereof are respectively connected to the outputs of the NOR circuits G9 and G 8 .
  • the load transistors T 8 , T 8 ' and T 8 " have their drains connected to a power source V DD , and have their sources connected to the drains of the load transistors T 9 and T 9 '.
  • the driving transistors Q 8 and Q 8 ' have their drains connected to an output terminal X and also to the sources of the load transistors Tg and Tg', and they have their sources grounded.
  • all the inputs c, d and e are of L level
  • all the load transistors T 8 , T 8 ' and T 8 turn “off", and current from the power source is cut off.
  • the driving transistor Q 8 ' turns "on", and the output becomes L level.
  • both the inputs f and g are of L level
  • both the load transistors T 9 and T 9 turn “off", and the current from the power source is cut of
  • the driving transistor Q 8 turns "on", and the output becomes L level.
  • both the outputs of the NOR circuits G 8 and G 9 become L level, and the driving transistors Q 8 and Q 8 ' turn “off”.
  • the load transistors T 8 , T 8 ' and T 8 turns “on” and at least one of the load transistors T 9 and T 9 ' turns "on", so that the output X becomes H level.
  • both the driving transistors Q 8 and Q 8 ' are "off".
  • the reverse case that is, when at least one of the driving transistors Q 8 and Q 8 ' is "on", all the load transistors T 8 , T 8 ' and T 8 " are “off” or both the load transistors T 9 and T 9 ' are "off". During the steady state, therefore, no power is consumed within the circuit.
  • Figure 10 shows a fourth embodiment of the present invention.
  • preceding-stage circuits are a 2-input NAND circuit G 10 and a 3-input NOR circuit G 11 , and NOT AND logic between the'outputs of the circuits G 10 and G 11 is provided at the output of the fourth embodiment.
  • a load transistor T 10 has its drain connected to a power source V DD , and has its source connected to the drain of a load transistor T 10 '.
  • the gates of these load transistors T 10 and T 10 ' are respectively connected to inputs i and h with which the inputs of the NAND circuit G 10 are connected.
  • the sources and drains of load transistors T 11' T 11 ' and T 11 " are respectively connected in common, and the drains are connected to a power source V DD . Further, the gates of the load transistors T 11 , T 11 ' and T 11 " are respectively connected to inputs l, k and j with which the inputs of the NOR circuit G 11 are connected. The gates of driving transistors Q 9 and R 9 ' are respectively connected to the outputs of the NAND circuit G 10 and the NOR circuit G 11 . The drain of the driving transistor Q 9 is connected to the source of the load transistor T 10 ' and also to the sources of the load transistors T 11 , T 11 ' and T 11 ".
  • the driving transistor Q 9 ' has its drain connected to the source of the driving transistor Q 9 , and has its source grounded. In the circuit of the fourth embodiment, no steady current flows as in the first, second and third embodiments described before. More specifically, when at least one of the inputs of the NOR circuit G 11 is of H level, the driving transistor Q 9 ' turns “off", and conversely at least one of the load transistors T 11 , T 11 ' and T 11 " turns "on", so that the output X becomes H level. When both the inputs h and i are of H level, the output of the AND circuit G 10 becomes L level, with the result that the driving transistor Q 9 turns "off".
  • both the load transistors T 10 and T 11 are "on", so that the output X becomes H level.
  • both the driving transistors Q 9 and Q 9 ' turn “on”.
  • all the load transistors i T 11' T 11 ' and T 11 " are "off” and one of the load transistors T 10 and T 10 ' is "off", so that current does not flow through the driving transistors via the load transistor.
  • no power is consumed in the steady state,. and an integrated circuit of low power consumption is realisable.
  • the “on” and “off” timings of the first, second, third and fourth embodiments are the same as the “on” and “off” timings of the load transistor and the driving transistor in the prior-art circuit shown in Figure 3, and the operating speed is rendered high.
  • FIG 11 shows an example of a circuit in which inverter gate circuits G 12 - G 15 are connected in cascade.
  • the inverter circuit G 12 of the first stage is of the conventional E/E type, whereas the second stage G 13 and the succeeding stages are constructed on the basis of a fundamental circuit arrangement embodying the present invention.
  • Q 12 Q 15 designate driving transistors
  • T 12 - T 15 are enhancement-mode MOS transistors for loads. They are assumed to have common gate threshold values V th' respectively.
  • the output of the inverter circuit G 12 at the first stage becomes H level.
  • the actual potential of the H level is a potential (V DD - V th ) which is lower than the supply voltage V DD applied to the gate of the load transistor T 12 , by the threshold value V th of this transistor.
  • the L level input of the first-stage gate G 12 is applied to the gate of the load transistor T 13 of the second-stage gate G 13 and brings this transistor into the "off" state.
  • the output signal of the level (V DD - V th ) is also applied to the gate of the driving transistor Q 13 .
  • the transistor Q 13 when the gate threshold value of the driving transistor Q 13 is smaller than the output signal level (V DD - V th ), the transistor Q 13 turns "on", and an L level signal substantially equal to the ground potential is provided at the output end of the second-stage gate G 13 .
  • the L level signal substantially equal to the ground potential is applied to the gate of the.driving transistor Q 14 , so that the transistor Q 14 falls into the "off" state.
  • the gate of the load transistor T 14 is supplied with the output signal of the first-stage gate G12, the level of this signal being (V DD - V th ).0 Therefore, the output end potential of the third-stage gate G 14 rises, but only a level (V DD - 2 V th ), which is still lower than the gate potential of the transistor T 14 by V th ' is obtained as the output potential.
  • This problem of the reduction of signal level can be eliminated by, for example, employing depletion-mode transistors as load transistors. In that case, however, it is difficult to attain the effect of a marked reduction in power consumption by providing that either the load element or the driving element is infallibly brought into the non-conductive state in steady state conditions.
  • load elements are constructed of an enhancement-mode transistor and a depletion-mode transistor whose sources, drains and gates are respectively connected in common.
  • FIG 12 is a circuit diagram showing the fifth -a embodiment of the present invention which provides / logic circuit employing such load elements.
  • the embodiment is such that the construction of the load elements is applied to a fundamental circuit arrangement in which two inverter circuits are connected in cascade as in the example of Figure 3.
  • Q is a driving transistor
  • T and T' are enhancement-mode and depletion-mode MOS transistors for loads, respectively
  • G designates an inverter circuit at the preceding stage.
  • the depletion-mode load transistor T' is intended to refresh the signal level, and its gate threshold value assumes a negative value (in case of the n-channel type).
  • the depletion-mode load element T' is provided for the purpose of raising the output level of the logic circuit of Figure 12 up to a supply voltage YDD in a state in which the logic circuit steadily provides H level.
  • the purpose can be achieved only if the element T' is capable of causing a slight current to flow.
  • L level that is, in the state in which H level is applied to the gate terminal of the driving transistor Q and L level is applied to the load transistors T and T'
  • the enhancement-mode load element T is a load transistor for the original push-pull operation, it has its current capacity made large in order to permit a high-speed transient change. To this end, the gate width of the load element T is made approximately equal to that of the driving element Q. In this case, it does not arise in the steady state that both the enhancement-mode load element T and the driving transistor Q fall into the "on" states, and excess power consumption is not brought about thereby.
  • a second feature of embodiments of the present invention consists in that an enhancement-mode load is employed in the fundamental operation in order to realise low power consumption and high operating speed through push-pull operation, whilst a depletion-mode load of small current capacity is employed in order to refresh the signal level, in other words, in order to provide a level not affected by the gate threshold value.
  • the load elements may well be constructed by interconnecting discrete enhancement-mode and depletion-mode transistors, a unitary load element is readily fabricated within an integrated circuit.
  • the plan structure of a practicable unitary element in a sixth embodiment of the present invention is shown in Figure 13.
  • Shown in Figure 13 is an example of a practicable plan structure of a portion which corresponds to one stage of an inverter circuit embodying this invention.
  • 10 is an element' region which is surrounded with a field region
  • 11 is a source region of a driving element (n-channel type MOS transistor)
  • 12 is a region which serves both as a drain region of the driving element and as a source region of a load element
  • 13 is a drain region of the load element
  • 14 is a gate electrode of the driving element
  • 15 is the gate electrode of the load element.
  • 16, 17 and 18 are connection portions for a ground lead, an output end lead and a power source (V DD ) lead, respectively.
  • the load element has its greater part fabricated similarly to an enhancement-mode MOS transistor, but that it is fabricated so as to exhibit depletion characteristics in a part region 21.
  • the formation of the depletion region 21 is easy.
  • the ions of a donor impurity such as arsenic may be injected by the use of an appropriate mask such as photoresist layer for exposing the region 21, so as to form a thin n-type layer in a part surface under the gate electrode 15.
  • Figures 14 to 17 illustrate seventh to tenth embodiments of the present invention.
  • the embodiments of Figures 14 and 15 illustrate cases in which the present invention is applied to the previously proposed logic circuits shown in Figures 5 and 6, respectively.
  • the embodiments in Figures 16 and 17 are such that ⁇ the use of depletion and enhancement-mode transistors is further applied to the first and second embodiments shown in Figures 7 and 8, respectively.
  • depletion-mode MOS transistors are connected in parallel with load transistors or enhancement-mode MOS transistors.
  • the drain,source and gate of a transistor S 3 are respectively connected to those of a load transistor T 3 ; the drain source and gate of a transistor S 2 are respectively connected to those of a load transistor T 2 ; and the drain, source and gate of a transistor S 5 are respeqtively connected to those of a load transistor T 5 .
  • the operations of the depletion-mode MOS transistors provide for logic circuits whose outputs X are not affected by the threshold values of input gates and which are capable of multi-stage connection.
  • the present invention relates to a logic circuit of high operating speed and low power consumption, and a logic circuit of high operating speed and low power consumption can be provided by applying this invention. Further, the logic circuit can be manufactured by a simple process and at low cost.
  • an embodiment of the present invention provides a logic circuit comprising a multi-input NOR gate, a plurality of load FET's and a driving FET, the load FET's and driving FET being connected in series with each other between power sources of the circuit and the logical output being derived from the connection point of a load FET and the driving FET.
  • the inputs of the NOR gate are equal in number to the load FET's.
  • the inputs of the NOR gate are connected to the gates of corresponding load FET's and the output of the NOR gate is connected to the gate of the driving FET.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
EP81305982A 1980-12-24 1981-12-21 Circuit logique Ceased EP0055570A3 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP183447/80 1980-12-24
JP183430/80 1980-12-24
JP55183430A JPS57106234A (en) 1980-12-24 1980-12-24 Logical operation circuit
JP55183447A JPS57106235A (en) 1980-12-24 1980-12-24 Logical operation circuit

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EP0055570A2 true EP0055570A2 (fr) 1982-07-07
EP0055570A3 EP0055570A3 (fr) 1983-01-26

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0090421A2 (fr) * 1982-03-30 1983-10-05 Nec Corporation Circuit logique
EP0101896A2 (fr) * 1982-07-30 1984-03-07 Kabushiki Kaisha Toshiba Circuit logique MOS
EP0188709A1 (fr) * 1984-12-04 1986-07-30 CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. Circuit de précharge de bus pour composants MOS intégrés
EP0432472A2 (fr) * 1989-11-15 1991-06-19 Kabushiki Kaisha Toshiba Circuit CMOS comportant des transistors bipolaires dans l'étage de sortie
WO2015008067A1 (fr) * 2013-07-17 2015-01-22 Pragmatic Printing Ltd Circuits électroniques

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JPS59218042A (ja) * 1983-05-26 1984-12-08 Toshiba Corp 半導体集積回路
DE4324519C2 (de) * 1992-11-12 1994-12-08 Hewlett Packard Co NCMOS - eine Hochleistungslogikschaltung
EP0653843A3 (fr) * 1993-11-17 1996-05-01 Hewlett Packard Co Circuits CMOS à seuil de tension adaptatif.
US5557219A (en) * 1994-01-31 1996-09-17 Texas Instruments Incorporated Interface level programmability
JP2009105848A (ja) * 2007-10-25 2009-05-14 Mitsumi Electric Co Ltd 論理ゲート及びこれを用いた半導体集積回路装置
US8362806B2 (en) * 2009-06-26 2013-01-29 Intel Corporation Keeper circuit

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JPS5239354A (en) * 1975-09-23 1977-03-26 Toshiba Corp Drive circuit

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JPS5520394B2 (fr) * 1973-11-10 1980-06-02
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JPS6035756B2 (ja) * 1977-12-27 1985-08-16 日本電気株式会社 論理回路
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JPS5239354A (en) * 1975-09-23 1977-03-26 Toshiba Corp Drive circuit

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0090421A2 (fr) * 1982-03-30 1983-10-05 Nec Corporation Circuit logique
EP0090421A3 (fr) * 1982-03-30 1984-07-04 Nec Corporation Circuit logique
EP0101896A2 (fr) * 1982-07-30 1984-03-07 Kabushiki Kaisha Toshiba Circuit logique MOS
EP0101896A3 (en) * 1982-07-30 1985-07-31 Kabushiki Kaisha Toshiba Mos logic circuit
US4716308A (en) * 1982-07-30 1987-12-29 Tokyo Shibaura Denki Kabushiki Kaisha MOS pull-up or pull-down logic circuit having equalized discharge time delays and layout avoiding crossovers
EP0188709A1 (fr) * 1984-12-04 1986-07-30 CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A. Circuit de précharge de bus pour composants MOS intégrés
EP0432472A2 (fr) * 1989-11-15 1991-06-19 Kabushiki Kaisha Toshiba Circuit CMOS comportant des transistors bipolaires dans l'étage de sortie
EP0432472A3 (en) * 1989-11-15 1991-08-21 Kabushiki Kaisha Toshiba Signal output circuit having bipolar transistor in output stage and arranged in cmos semiconductor integrated circuit
US5066874A (en) * 1989-11-15 1991-11-19 Kabushiki Kaisha Toshiba Signal output circuit having bipolar transistor in output stage and arranged in cmos semiconductor integrated circuit
WO2015008067A1 (fr) * 2013-07-17 2015-01-22 Pragmatic Printing Ltd Circuits électroniques
US9768782B2 (en) 2013-07-17 2017-09-19 Pragmatic Printing Limited Electronic circuits
EP3716485A1 (fr) * 2013-07-17 2020-09-30 Pragmatic Printing Ltd Circuits électroniques

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EP0055570A3 (fr) 1983-01-26
US4489246A (en) 1984-12-18

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