EP0052884A1 - Garde-temps comprenant une chaîne de diviseurs au rapport de division ajustable - Google Patents

Garde-temps comprenant une chaîne de diviseurs au rapport de division ajustable Download PDF

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Publication number
EP0052884A1
EP0052884A1 EP81109870A EP81109870A EP0052884A1 EP 0052884 A1 EP0052884 A1 EP 0052884A1 EP 81109870 A EP81109870 A EP 81109870A EP 81109870 A EP81109870 A EP 81109870A EP 0052884 A1 EP0052884 A1 EP 0052884A1
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EP
European Patent Office
Prior art keywords
chain
dividers
time
frequency
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81109870A
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German (de)
English (en)
French (fr)
Inventor
Mario Dellea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SSIH Management Services SA
Original Assignee
SSIH Management Services SA
Societe Suisse pour lIindustrie Horlogere Management Services SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SSIH Management Services SA, Societe Suisse pour lIindustrie Horlogere Management Services SA filed Critical SSIH Management Services SA
Publication of EP0052884A1 publication Critical patent/EP0052884A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/027—Circuits for deriving low frequency timing pulses from pulses of higher frequency by combining pulse-trains of different frequencies, e.g. obtained from two independent oscillators or from a common oscillator by means of different frequency dividing ratios

Definitions

  • the invention relates to a timepiece comprising a low-frequency oscillator as a time base supplying a first chain of frequency dividers with adjustable division ratio for displaying the time and a high-frequency oscillator supplying a second chain of frequency dividers frequency.
  • a high-frequency crystal oscillator which, in order to reduce the current consumption, comprises a circuit equipped with a crystal oscillator low frequency, means for producing a correction signal which is used to control a programmable frequency divider and an electronic switch for periodically interrupting the high frequency quartz oscillator.
  • a high-frequency quartz oscillator of 1 MHz or more has a temperature and aging stability which is more favorable than that of a conventional low-frequency quartz oscillator at 32 kHz.
  • this high-frequency quartz oscillator with the frequency divider which is linked to it has a substantially higher current consumption, which requires frequent battery replacements.
  • the invention cited above proposes an oscillator which has all the advantages of a high-frequency oscillator but whose consumption does not exceed that shown by a low-frequency oscillator.
  • the cited publication uses an electronic switch which periodically activates (every 15 minutes) for a relatively short time (16 seconds) the HF oscillator.
  • the signals emitted by the HF and LF oscillators feed each of the secondary frequency dividers which each produce at their output a signal whose period is approximately 16 seconds. These two signals feed a beat generator, the output result of which corresponds to the difference existing between the LF period to be set and the HF reference period. This difference is then used to correct the division ratio of the main frequency divider.
  • a beat generator the output result of which corresponds to the difference existing between the LF period to be set and the HF reference period. This difference is then used to correct the division ratio of the main frequency divider.
  • every 15 minutes we question the division ratio of the main divider and, in the case where the frequency of the low-frequency oscillator has varied, we correct said division ratio by a signal from a learning circuit consisting of a beat generator.
  • the system whose operation has just been recalled has several drawbacks. The first is to require several secondary frequency dividers, which complicates the construction. Then to transform the signals from the HF and BF oscillators to produce a beat, instead of using them directly as they exist in binary form, which decreases the precision. Finally, that of not taking into consideration that, for cost price reasons, the HF quartz can be roughly adjusted around a nominal frequency, in which case means must be used to memorize the existing difference.
  • the present invention proposes to regulate the running of the timepiece comprising a frequency divider with the adjustable division ratio by adjustment means which appear in the claims.
  • Figure 1 shows how the timepiece object of the invention is arranged. It includes a low-frequency oscillator, generally with quartz crystal 1, which attacks via an inhibition circuit 2 a chain of frequency dividers 3. Inhibition circuit and chain of dividers together form a system with adjustable ratio. In known timepieces and if the frequency of the LF oscillator is of the order of 33 kHz, it will take fifteen divisors by two to obtain a frequency of 1 Hz at the display control output (1 s) to display the time (HMS). Here chain 3 is extended by ten additional dividers to provide additional outputs at 4.8 and 1024 seconds. Thus in the example given, the chain 3 totals twenty-five binary divisors.
  • the inhibition circuit 2 is controlled by blocks 4 and 18 which make it possible to suppress a certain proportion of the pulses supplied by the time base and thus to lower the command frequency of the actuating motor. display up to the desired value.
  • FIG. 1 also shows that the arrangement comprises, in addition to the oscillator BF, a second high-frequency oscillator 5, generally with quartz crystal, which, through a NOR gate 6, feeds a second chain of frequency dividers 7.
  • this second chain comprises eleven dividers by two and the HF oscillator is equipped with a quartz at 4 MHz.
  • the HF oscillator is capable of being engaged or triggered periodically by the line OS, that the NOR gate 6 receives on its second input a signal BL capable of blocking or unblocking the chain 7 and that said chain can be reset through the RC line.
  • the binary word that is found at the output of the chain 7 consists, in the example chosen, of eleven bits which can be transferred by line 8 into a first memory 9 when a transfer order Tt is given to said memory 9.
  • the signals OS, BL, RC and Tt come from a logic servo control circuit 10 itself controlled by signals 11 to 15 coming from the division chain 3.
  • the binary content memory 9 is used, during the normal running of the timepiece, to adjust the division ratio of the chain of dividers 3, either directly or indirectly via a comparison circuit 16 which compares the content of the first memory 9 with the content of a second memory 17.
  • a system is proposed according to the invention where the frequency controlled by a BF quartz is periodically controlled by a frequency controlled by an HF quartz more stable in temperature. Means are implemented so that outside of the control periods the HF circuits are triggered.
  • a period controlled by the frequency is measured, by means of reference pulses generated by the HF oscillator or quartz. BF to be corrected. The difference is measured by counting the number of reference pulses contained in the period to be corrected.
  • the division chain on which the measurement is made is not the one whose value must be corrected, but the reference measured by means of a false period.
  • the system which is the subject of the invention requires a BF oscillator which is the time base used for displaying the time for which it is a question of correcting the imprecision and an HF oscillator which serves to reference for. making this correction.
  • the total adjustment period (inhibition) in seconds will last 2 d2 / f (BF) min.
  • the same measurement cycle will start again at time t 6 where the duration t 6 - t 0 (1024 s) is found to represent the control cycle.
  • the signals OS, RC, BL and Tt come from the logic circuit of the servo control 10 and are the result of the combination of the signals fa, fm, fos, f R o and ft coming of the BF 3 chain. These are represented at the top of the diagram in FIG. 2.
  • Figure 3 shows a possible arrangement to achieve this combination.
  • the diagram presented consists of elementary logic circuits: inverters, NOR and NAND gates, flip-flop, which form the content of block 10 shown in FIG. 1. It contains the signals fa, fm, fos, f R o and ft applied to the respective inputs 15, 14, 13, 12 and 11.
  • Those skilled in the art will understand, without explanations being given here, how the arrangement of the various logic circuits is made to reach the signals RC, BL, OS and Tt present at the output of the block.
  • the inhibition period is determined by the signal fi (whose duty cycle is 1) from the chain 3 and acting on the inhibition command 18 as shown in Figure 1.
  • the inhibition is executed when this signal is in state 0, which is the case for only half a period.
  • At the start of the other half-period during which no other inhibition takes place periodically corresponds the start of a control period fa which is also the start of a measurement. This coincidence is automatic because the inhibition signal fi is generated by the same division chain 3 which also generates the servo signal fa.
  • FIG. 4 shows what happens during the duration of the period to be corrected. This period, originating from the chain B F , begins at time t l as soon as the signal BL goes to state 0 and stops at time t 2 as soon as said signal returns to state 1. From time t l , the HF chain starts to count the pulses emitted by the HF oscillator.
  • FIG. 4 shows the signals present at the output (HF 1 to HF 5 ) of five successive dividers of the HF chain (which normally includes eleven in the example cited here). To make the diagram explicit, it will be understood that it was necessary to choose another time scale to represent in superposition the LF period (4 s) and the HF pulses whose lowest frequency, after eleven divisions, is still 4 kHz.
  • time t x At a certain time (time t x ), all the HF divisors are at 0 and this before the period to be corrected BL is over. This is due to the fact that an HF quartz with more distant tolerances (for example + 140 to + 4140 ppm) has been chosen than the tolerances for BF quartz (for example +60 to + 100 ppm). From this instant t x , the HF chain will start a counting cycle again, which will be interrupted at time t 2 . At this moment, the logical state of all the HF divisors is a measure of the difference separating the moment (t x ) when all the HF divisors have passed through 0 and that when the period to be corrected ends (t 2 ). In the figure, the five dividers shown have the binary value 00110 when the chain counting stops. This value is temporarily retained by the chain 7 before being transferred by the line 8 from time t 3 to the first memory 9, as shown in FIG. 2.
  • the HF oscillator delivers an exact nominal frequency.
  • the BF - HF difference could be used to act directly on the inhibition control circuit 4, as is proposed by the Swiss inventories cited above.
  • the output of the memory 17 has a binary value which is expressed with bits of weight identical to those from the first memory 9. It is therefore possible to compare the difference BF - HF with the HF difference - Nom. in a subtractor circuit 16 so as to obtain a binary signal at the output of the subtractor which represents the difference BF - Nom. to act on the inhibition control circuit 4.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Paper (AREA)
  • Helmets And Other Head Coverings (AREA)
EP81109870A 1980-11-26 1981-11-25 Garde-temps comprenant une chaîne de diviseurs au rapport de division ajustable Withdrawn EP0052884A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH8742/80 1980-11-26
CH874280A CH643106B (fr) 1980-11-26 1980-11-26 Garde-temps comprenant une chaine de diviseurs au rapport de division ajustable.

Publications (1)

Publication Number Publication Date
EP0052884A1 true EP0052884A1 (fr) 1982-06-02

Family

ID=4344194

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81109870A Withdrawn EP0052884A1 (fr) 1980-11-26 1981-11-25 Garde-temps comprenant une chaîne de diviseurs au rapport de division ajustable

Country Status (4)

Country Link
US (1) US4456386A (enrdf_load_stackoverflow)
EP (1) EP0052884A1 (enrdf_load_stackoverflow)
JP (1) JPS57116288A (enrdf_load_stackoverflow)
CH (1) CH643106B (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590607A1 (en) * 1992-09-29 1994-04-06 Oki Electric Industry Co., Ltd. Low-power baud rate generator
EP0586256A3 (en) * 1992-09-04 1996-03-27 Nokia Mobile Phones Ltd Time measurement system
WO2000079349A2 (en) 1999-06-18 2000-12-28 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction
WO2001088635A3 (en) * 2000-05-16 2002-06-13 Ericsson Inc Methods, systems, wireless terminals, and computer program products for calibrating an electronic clock using a base reference signal and a non-continuous calibration reference signal having greater accuracy than the base reference signal
EP1004948A3 (de) * 1998-09-22 2006-02-15 Siemens Aktiengesellschaft Kostengünstige Uhr

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH661833GA3 (enrdf_load_stackoverflow) * 1985-12-18 1987-08-31
US4737944A (en) * 1986-04-08 1988-04-12 Seiko Instruments Inc. Electronic timepiece
US4890270A (en) * 1988-04-08 1989-12-26 Sun Microsystems Method and apparatus for measuring the speed of an integrated circuit device
US5204845A (en) * 1988-12-19 1993-04-20 Alcatel N.V. Clock synchronization
AU631153B2 (en) * 1988-12-19 1992-11-19 Alcatel Australia Limited Clock synchronization
US5412624A (en) * 1991-12-16 1995-05-02 Abb Power T & D Company, Inc. Real-life timer interval adjustment
US6408388B1 (en) 1993-05-05 2002-06-18 Addison M. Fischer Personal date/time notary device
US5422953A (en) * 1993-05-05 1995-06-06 Fischer; Addison M. Personal date/time notary device
JPH07154243A (ja) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp 電子式時計装置ならびに補正値決定装置および方法
JPH07219672A (ja) * 1994-01-28 1995-08-18 Fujitsu Ltd 高精度時計回路
DE19618094C2 (de) * 1996-05-06 1999-06-02 Sgs Thomson Microelectronics Steuerschaltung mit nachstimmbarem Standby-Oszillator
US6009319A (en) * 1996-09-06 1999-12-28 Telefonaktiebolaget Lm Ericsson Method and apparatus for reducing power consumption in a mobile radio communication device
JP3930773B2 (ja) * 2002-07-19 2007-06-13 沖電気工業株式会社 周波数補正回路
KR100498839B1 (ko) * 2002-11-26 2005-07-04 삼성전자주식회사 아날로그 시계 내장형 단말기의 아날로그 시계 시각 조정방법 및 장치
JP2013034174A (ja) * 2011-06-28 2013-02-14 Seiko Instruments Inc 電子機器

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364439A (en) * 1966-10-07 1968-01-16 Tele Signal Corp Frequency corrected digital clock with memory in phase control loop
CH534913A (fr) * 1970-02-17 1972-08-15 Centre Electron Horloger Garde-temps
FR2197265A1 (enrdf_load_stackoverflow) * 1972-08-24 1974-03-22 Dynacore Sa
CH554015A (enrdf_load_stackoverflow) * 1971-10-15 1974-09-13
CH570651A (fr) * 1971-10-15 1975-12-15 Centre Electron Horloger Garde-temps comprenant un divisuer de frequence au rapport de division ajustable par des moyens l'etalonnage externes et procede de mise en action de ce garde temps.
US4115687A (en) * 1976-04-14 1978-09-19 Siemens Aktiengesellschaft Circuit arrangement for controlling the pulse repetition frequency of a signal
JPS5557181A (en) * 1978-10-20 1980-04-26 Citizen Watch Co Ltd Electronic watch
EP0015873B1 (de) * 1979-03-09 1983-04-13 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Oszillator mit einem Niederfrequenz-Quarzresonator

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6035637B2 (ja) * 1975-06-05 1985-08-15 シチズン時計株式会社 電子時計
GB1570659A (en) * 1976-06-30 1980-07-02 Suwa Seikosha Kk Electronic timepiece
CH621680B (de) * 1979-05-22 Suisse Horlogerie Oszillator mit temperaturkompensation.
JPS55160891A (en) * 1979-06-01 1980-12-15 Seiko Instr & Electronics Ltd Temperature correcting circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364439A (en) * 1966-10-07 1968-01-16 Tele Signal Corp Frequency corrected digital clock with memory in phase control loop
CH534913A (fr) * 1970-02-17 1972-08-15 Centre Electron Horloger Garde-temps
CH554015A (enrdf_load_stackoverflow) * 1971-10-15 1974-09-13
CH570651A (fr) * 1971-10-15 1975-12-15 Centre Electron Horloger Garde-temps comprenant un divisuer de frequence au rapport de division ajustable par des moyens l'etalonnage externes et procede de mise en action de ce garde temps.
FR2197265A1 (enrdf_load_stackoverflow) * 1972-08-24 1974-03-22 Dynacore Sa
US4115687A (en) * 1976-04-14 1978-09-19 Siemens Aktiengesellschaft Circuit arrangement for controlling the pulse repetition frequency of a signal
JPS5557181A (en) * 1978-10-20 1980-04-26 Citizen Watch Co Ltd Electronic watch
US4264967A (en) * 1978-10-20 1981-04-28 Citizen Watch Co., Ltd. Unit time producing system
EP0015873B1 (de) * 1979-03-09 1983-04-13 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Oszillator mit einem Niederfrequenz-Quarzresonator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Jahrbuch der Deutschen Gesellschaft fur Chronometrie, Vol. 28, 1977, Stuttgart (DE) H. EFFENBERGER: "Digitale Temperaturkompensation von Schwing-Quarzoszillatoren mit Automatischem Prequenzabgleich", Pages 9-15 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0586256A3 (en) * 1992-09-04 1996-03-27 Nokia Mobile Phones Ltd Time measurement system
EP0590607A1 (en) * 1992-09-29 1994-04-06 Oki Electric Industry Co., Ltd. Low-power baud rate generator
US5398007A (en) * 1992-09-29 1995-03-14 Oki Electric Industry Co., Ltd. Low-power baud rate generator including two oscillators
EP1004948A3 (de) * 1998-09-22 2006-02-15 Siemens Aktiengesellschaft Kostengünstige Uhr
WO2000079349A2 (en) 1999-06-18 2000-12-28 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction
WO2000079349A3 (en) * 1999-06-18 2001-05-25 Ericsson Telefon Ab L M Method and apparatus for real time clock frequency error correction
US6304517B1 (en) 1999-06-18 2001-10-16 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction
WO2001088635A3 (en) * 2000-05-16 2002-06-13 Ericsson Inc Methods, systems, wireless terminals, and computer program products for calibrating an electronic clock using a base reference signal and a non-continuous calibration reference signal having greater accuracy than the base reference signal
US6545950B1 (en) 2000-05-16 2003-04-08 Ericsson Inc. Methods, systems, wireless terminals, and computer program products for calibrating an electronic clock using a base reference signal and a non-continuous calibration reference signal having greater accuracy than the base reference signal

Also Published As

Publication number Publication date
JPS57116288A (en) 1982-07-20
CH643106GA3 (enrdf_load_stackoverflow) 1984-05-30
US4456386A (en) 1984-06-26
CH643106B (fr)

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Inventor name: DELLEA, MARIO