EP0045848B1 - Circuits intégrés semiconducteurs planaires comportant des structures de transistors bipolaires et procédé de fabrication correspondant - Google Patents

Circuits intégrés semiconducteurs planaires comportant des structures de transistors bipolaires et procédé de fabrication correspondant Download PDF

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Publication number
EP0045848B1
EP0045848B1 EP19810105228 EP81105228A EP0045848B1 EP 0045848 B1 EP0045848 B1 EP 0045848B1 EP 19810105228 EP19810105228 EP 19810105228 EP 81105228 A EP81105228 A EP 81105228A EP 0045848 B1 EP0045848 B1 EP 0045848B1
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Prior art keywords
layer
semiconductor
insulating material
region
conductivity type
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German (de)
English (en)
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EP0045848A1 (fr
Inventor
Arnold Reisman
Victor Joseph Silvestri
Denny Duan-Lee Tang
Siegfried Kurt Wiedmann
Hwa Nien Yu
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors

Definitions

  • This invention relates to planar semiconductor integrated circuits including bipolar transistors and to methods of fabricating such circuits.
  • the area of the top junction of vertical bipolar transistors is always smaller than the area of the lower junction due to the contact area to the base region, and/or the magnitude of alignment tolerances needed. Therefore high performance is obtainable only when such a device is operated in a downward mode. Even then, however, parasitic diode effects limit the performance of the transistor. Parasitic diodes also affect the performance of lateral transistors.
  • the article on pages 2761 to 2762 of the IBM Technical Disclosure Bulletin, Volume 21, no. 7, December 1978 entitled "Self-aligned Bi- polar Transistor”, discloses a self-aligned bi- polar transistor comprising a buried insulating region with an opening having parallel side walls.
  • the insulating region confines an N collector region within the opening which is contiguous with the same conductivity type semiconductor region lying underneath the insulating region.
  • An outer semiconductor layer of P conductivity type is provided over the insulating region and PN junctions of a symmetrical bi-polar transistor structure are formed in a region defined in the outer layer by the opening in the insulating region.
  • the PN junctions have substantially the same areas.
  • Bipolar transistor technology has recently been enhanced by an improved process utilizing the concept of simultaneous growth of epitaxial silicon on single crystal silicon and polycrystalline silicon on silicon dioxide. This results in a transistor structure with somewhat reduced parasitic diode effects. This concept is described by Davies et al in the article entitled “Poly 1 2 L - A High-Speed-Linear-Compatible Structure", IEEE J. Solid State Circuits, Vol. SC-12, No. 4, August 1977, pp. 367-375.
  • the present invention seeks to provide an integrated circuit including bipolar transistor structures in which the formation of parasitic diodes is avoided.
  • a planar semiconductor integrated circuit including a layer of isolating material disposed over a semiconductor substrate of one conductivity type, the isolating layer being provided with a first hole therethrough having substantially parallel sidewalls and containing semiconductor of the opposite conductivity type, an outer layer of semiconductor of said one conductivity type overlying the isolating layer and a symmetrical vertical bipolar transistor structure comprising a pair of PN junctions formed in a region defined in said outer layer of semiconductor by the hole in the isolating layer, the PN junctions being of substantially equal area and confined to the intrinsic region of the transistor, the circuit being characterised by further including a doped region of semiconductor of said opposite conductivity type formed in the substrate in such a position that it is contiguous with the semiconductor of said opposite conductivity type in the first hole in the isolating layer, and by further including a second symmetrical bipolar transistor structure comprising a pair of PN junctions formed in a region defined in said outer layer of semiconductor by a second
  • a method of fabricating a planar semiconductor integrated circuit including a vertical bipolar transistor having first and second PN junctions of substantially equal area and a lateral bipolar transistor having first and second PN junctions of substantially equal area comprises the steps a to k defined in claim 6.
  • the top junction is always smaller than the lower junction by the amount of alignment tolerance and the contact area to the base region.
  • the transistor of FIG. 1.1 provides high performance only when it is operated downwards, that is, when the top n+ region 2 is used as the emitter.
  • 1.1 is operated upwards, that is, when the lower n+ region 4 is used as the emitter such as in Merged-Transistor-Logic or 1 2 L circuits, the current gain is lower (by approximately a factor of three) and the switching speed is slower (by approximately a factor of three) due to the existence of the parasitic diodes formed by the area 6 outside the intrinsic base region 31 of the lower junction where area 6 contacts the extrinsic base region area 32 as shown in the equivalent circuit of FIG. 1.2 wherein the parastic diodes 8 are illustrated.
  • the lateral transistor illustrated in FIG. 2.1 has large parasitic diodes at both junctions which degrade performance.
  • the equivalent circuit of the lateral transistor is illustrated in FIG. 2.2.
  • FIG. 3 An integrated circuit embodying the invention and including a symmetrical transistor structure (STS) wherein the area of the top junction is substantially equal to the area of the lower junction is illustrated in FIG. 3.
  • the structure of FIG. 3 includes a vertical bipolar npn transistor 3, a lateral pnp transistor 5 and contiguous self-aligned conductive regions 7.
  • the upper and lower junctions of the vertical bipolar transistor 3 are substantially equal in area as a result of self-aligned fabrication steps to be later described.
  • the structure of FIG. 3 is shown with a buried oxide type isolation 9, however, any other conventional isolation schemes (for isolating the n ⁇ sublayer islands of each device) may be used.
  • FIGS. 4.1 through 4.12 illustrate an embodiment of a preferred method.
  • An n+ subcollector region 12 (FIG. 4.1) is ion-implanted in a p-type silicon substrate 10 in a non-critical manner using a first mask.
  • the dopant for the implant may, for example, be arsenic.
  • the structure shown in FIG. 4.1 may be provided with any conventional isolation (not shown), such as recessed oxide or deep trench, to isolate the structure from other devices on an integrated circuit chip.
  • a layer of oxide or other suitable insulator 14 is formed on the substrate 10 and subcollector 12 by any suitable technique such as thermal growth, chemical vapour or deposition plasma.
  • a thin layer or skin of silicon 1 6 is then formed on insulator layer 14 by chemical vapour deposition, sputtering, or other suitable technique, if the semiconductor is silicon as in the general example given. Since its function, if it is employed, is solely as a nucleating layer, layer 16 may or may not be the same as the semiconductor in which the devices are to be built, so long as it serves this function.
  • the layer 16 which functions as a nucleating layer may be of the order of 100 to 800 Angstroms thick when it is silicon. Layer 16 is not however, a critical element in the structure and its use may be eliminated in other embodiments.
  • an opening for the active region of the device is defined by etching through layers 16 and 14 using a second mask.
  • a layer of lightly doped n-type silicon 18 is deposited.
  • One deposition technique which may be employed uses silicon tetrachloride and hydrogen wherein SiC1 4 + H 2 forms Si + 4HCI.
  • the result of this step is that silicon grows simultaneously over the insulator region 14 and over the n+ subcollector 12 regions.
  • the regions grown over the insulator are generally polycrystalline, regions 18A, while the regions grown over the subcollector, regions 18B, are single crystal in nature. It is the case that the single crystal regions partially overgrow the insulator.
  • Laser melting techniques may be employed, if desired, to convert any poly- crytalline regions to single crystal regions using the single crystal regions as seed or nucleating sites.
  • silicon layer 18 is to use silane (SiH 4 ) which decomposes into Si and hydrogen.
  • SiH 4 silane
  • the thin layer 16 of silicon of step 4.2 is not required.
  • dopant would be incorporated.
  • a thin layer of insulator for example silicon dioxide 20 and a thin layer of second insulator, for example, silicon nitride 22 which functions as an oxidation mask, in the case given, are deposited over the semiconductor layer 18, and then the surface of the structure is planarized by spinning on a layer of photoresist 24 or other suitable planarizing material (FIG. 4.6).
  • planarizing layer 24 is then uniformly etched for example by reactive ion etching (using CF 4 + H Z ) or plasma etching.
  • the nitride and oxide layers 22 and 20 respectively over the regions 1 8A will then be etched away and the etching is stopped when the regions 18A are exposed, leaving regions of planarizing material 24 and nitride 22 and oxide 20 over the regions 18B as illustrated in FIG. 4.7.
  • a dopant such as boron is ion implanted into the silicon regions 18A to produce p+ conductivity in the case of silicon based vertical npn and lateral pnp structures.
  • the remaining planarizing material 24, nitride layer 22 and oxide layer 20 over the regions 18B function as an implant mask which serves to self-align the region 18B with the p+ conductive regions 18A.
  • the planarizing material 24 is stripped away and the boron is driven in to regions 18A to form p+ contact regions. Then, using a third mask, the region 18A is delineated to separate base regions of different vertical npn transistors as is shown on the left side of FIG. 4.8, feature 26.
  • an oxide layer 28 is grown over the structure, however, the regions 18B will not be oxidized because of the nitride layer 22, which functions as a self-aligned oxide mask.
  • the nitride layer over the epi regions 18B is stripped away. Then the thin layer of oxide 20 under the nitride is dip etched away forming a self-aligned top oxide opening over the regions 1 8B.
  • a layer of photoresist 30 is formed and exposed through a fourth mask and then etched to cover the active region of the vertical bipolar device area of the structure.
  • the collector reach through region is then ion-implanted with an n+ dopant, for example with phosphorus.
  • the vertical bipolar top emitter 32 and base 34 as shown in FIG. 4.12 are then formed by ion-implantation, for example, by implanting boron and arsenic at different dosage and energies after first removing the photoresist mask 30.
  • contact holes are formed in the structure of FIG. 4.12 in a conventional manner using a fifth mask, and the structure is metallized conventionally using a sixth mask.
  • FIGS. 4.1 through 4.12 The fabrication steps just set forth relative to FIGS. 4.1 through 4.12 are related to the formation of a vertical bipolar transistor having junction areas of substantially the same size such that the vertical transistor can be operated symmetrically upwards or downwards with equal effectiveness.
  • the oxide layer 20 and nitride layer 22 are not removed and phosphorus is not implanted, so the region 18B remains lightly doped. Instead, a sufficient heat cycle is performed so that the dopant boron in the p+ regions 1 8A on each side of the n-type region 18B of the device out-diffuses into the n-type region 18B and forms lateral p-n junctions inside the region 18B. After opening contact holes over the p+ regions 18A and metallizing, the lateral p-n-p transistor 5 shown in FIG. 3 is obtained.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Claims (9)

1. Circuit intégré à semiconducteurs planar comprenant une couche de matériau isolant (9) disposée sur un substrat semiconducteur d'un premier type de conductivité, cette couche isolante étant traversée par une première ouverture à parois latérales sensiblement parallèles et contenant un semiconducteur du type opposé de conductivité, une couche extérieure (7) de semiconducteur du premier type de conductivité recouvrant la couche isolante et une structure (3) de transistor bipolaire vertical symétrique comprenant une paire de jonctions p-n formées dans une région déterminée dans la couche extérieure de semiconducteur par l'ouverture formée dans la couche isolante, les jonctions p-n ayant une superficie sensiblement égale et étant limitées à la région intrinsèque du transistor, ce circuit étant caractérisé en ce qu'il comprend en outre une région dopée (12) de semiconducteur du type opposé de conductivité, formée dans le substrat en un endroit tel qu'elle est contiguë au semiconducteur du type opposé de conductivité dans la première ouverture faite dans la couche isolante; et en ce qu'il comprend en outre une deuxième structure (5) de transistor bipolaire symétrique comportant une paire de jonctions p-n formées dans une région définie dans la couche extérieure de semiconducteur par une deuxième ouverture faite dans la couche isolante, cette deuxième ouverture ayant des parois latérales sensiblement parallèles et contenant un semiconducteur du type opposé de conductivité qui est contigu à la région dopée, cette deuxième structure de transistor bipolaire symétrique étant une structure de transistor latéral comprenant une région de base du type opposé de conductivité, formée dans la couche extérieure et recouvrant et contiguë au semiconducteur du type opposé de conductivité, contenu dans la deuxième ouverture faite dans la couche isolante, les jonctions p-n entre la région de base et le semiconducteur du premier type de conductivité de la couche extérieure étant sensiblement perpendiculaires à la couche extérieure et ayant des superficies sensiblement égales.
2. Circuit intégré suivant la revendication 1, dans lequel la couche extérieure de semiconducteur est pôlycristalliné lôrsqû'elle est contiguë à la couche isolante.
3. Circuit intégré suivant la revendication 1, dans lequel la couche extèrieure de semiconducteur est monocristalline.
4. Circuit intégré suivant l'une quelconque des revendications 1 à 3, dans lequel le substrat est constitué de silicium de type p, la région dopée se compose de silicium de type n, la couche isolante est constituée de silice et la couche extérieure de semiconducteur se compose de silicium de type p.
5. Circuit intégré suivant l'une quelconque des revendications 1 à 3, dans lequel le substrat est constitué de silicium de type n, la région dopée se compose de silicium de type p, la couche isolante est constituée de silice et la couche extérieure de semiconducteur se compose de silicium de type n.
6. Procédé de fabrication d'un circuit intégré à semiconducteurs planar comprenant un transistor bipolaire vertical ayant une première et une deuxième jonctions p-n de superficies sensiblement égales et un transistor bipolaire latéral ayant une première et une deuxième jonctions p-n de superficies sensiblement égales, ce procédé comprenant les stades de:
a) fourniture (figure 4.1) d'un substrat semiconducteur composé d'un matériau d'un premier type de conductivité et dans la surface duquel est implantée une région dopée composée d'un matériau d'un deuxième type de conductivité opposé au premier;
b) formation (figure 4.2) d'une couche (14) d'un premier matériau isolant par croissance sur le substrat et sur la région dopée implantée dans le substrat;
c) attague (figure 4.3) d'une ouverture à travers cette couche de premier matériau isolant au-dessus de la région dopée à l'intérieur du substrat afin de former une ouverture dans le premier matériau isolant vers une région active du dispositif;
d) dépôt (figure 4.4) d'une couche (18) de matériau semiconducteur légèrement dopé, du deuxième type de conductivité, sur la couche de premier matériau isolant et l'ouverture faite dans ce matériau isolant afin de former simultanément une couche de matériau semiconducteur dans la région active du dispositif sur la région dopée formée dans le substrat, et une couche conductrice sur le premier matériau isolant;
e) formation (figure 4.5) d'une couche mince (20, 22) d'un deuxième matériau isolant sur la couche conductrice et sur le matériau semiconducteur;
f) planarisation (figure 4.6) de la surface de la structure par application d'une couche (24) de matériau de planarisation sur la couche mince du deuxième matériau isolant;
g) enlèvement par attaque d'une partie de la couche de matériau de planarisation et du deuxième matériau isolant afin de mettre à nu la couche conductrice (18a) au-dessus du premier matériau isolant (14) et afin de laisser une partie de la couche du deuxième matériau isolant et du matériau de planarisation sur la couche (18b) de matériau semiconducteur dans l'ouverture formée dans le premier matériau isolant;
h) implantation (figure 4.7) d'un dopant du premier type de conductivité dans la couche conductrice (18a) disposée sur le premier matériau isolant, la couche (1 8b) de matériau semiconducteur dans l'ouverture formée dans le premier matériau isolant étant masquée par la couche (20, 22) du deuxième matériau isolant, cette dernière couche du deuxième matériau isolant ayant pour fonction d'auto-aligner le matériau semiconducteur dans l'ouverture faite dans le premier matériau isolant avec la couche conductrice du premier type de conductivité;
i) enlèvement (figure 4.8) du matériau de planarisation sur la couche (20, 22) du deuxième matériau isolant et formation (figure 4.9) d'une couche d'oxyde (28) sur la première couche conductrice (18a), la couche de matériau semiconducteur dans l'ouverture formée dans le premier matériau isolant étant masquée de l'oxydation par la couche de deuxième matériau isolant;
j) formation (figure 4.12) d'une première et d'une deuxième régions (34) de transistor dans l'ouverture faite dans le premier matériau isolant par implantation d'au moins un dopant du première région de transistor étant du couche de matériau semiconducteur légèrement dopé du deuxième type de conductivité, en créant de ce fait une première jonction à l'intérieur du matériau semiconducteur, la première région de transsistor étant du deuxième type de conductivité tandis que la deuxième région de transistor est du premier type de conductivité.
k) formation (figure 4.12) d'une troisième région (32) de transistor par implantation d'au moins un dopant du deuxième type de conductivité à l'intérieur de la couche de semiconducteur dans la deuxième région de transistor, en formant de ce fait une deuxième jonction entre cette deuxième région de transistor et la troisième région de transistor, la première région de transistor, la deuxième région de transistor et la troisième région de transistor formant un transistor bipolaire vertical dont la première et la deuxième superfices de jonction ont la même dimension déterminée par la largeur de la région active du dispositif dans le premier matériau isolant.
7. Procédé de fabrication d'un circuit intégré suivant la revendication 6, dans lequel le substrat semiconducteur mentionné au stade a) est constitué de silicium, le premier matériau isolant mentionné au stade b) est formé de silice, et le deuxième matériau isolant mentionné au stade e) est du nitrure de silicium.
8. Procédé de fabrication d'un circuit intégré suivant l'une des revendications 6 ou 7, dans lequel le substrat semiconducteur mentionné au stade a) est constitué de silicium monocristallin de type p, la région dopée à l'intérieur du substrat mentionné au stade a) est composée de silicium de type n, le matériau isolant mentionné au stade b) est de la silice, la couche de semiconducteur légèrement dopé mentionnée au stade d) est du silicium monocristallin de type n, la première région de transistor mentionnée au stade j) est du silicium de type n, la deuxième région de transistor mentionnée au stade j) est du silicium de type p, et la troisième région de transistor mentionnée au stade k) est du silicium de type n.
EP19810105228 1980-08-08 1981-07-06 Circuits intégrés semiconducteurs planaires comportant des structures de transistors bipolaires et procédé de fabrication correspondant Expired EP0045848B1 (fr)

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US17638680A 1980-08-08 1980-08-08
US176386 1980-08-08

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EP0045848B1 true EP0045848B1 (fr) 1984-11-21

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CA (1) CA1161964A (fr)
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US3904450A (en) * 1974-04-26 1975-09-09 Bell Telephone Labor Inc Method of fabricating injection logic integrated circuits using oxide isolation
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US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation

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EP0045848A1 (fr) 1982-02-17
JPS5734365A (en) 1982-02-24
DE3167300D1 (en) 1985-01-03
CA1161964A (fr) 1984-02-07
JPS6150390B2 (fr) 1986-11-04

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