JPS5734365A - Symmetrical bipolar transistor - Google Patents
Symmetrical bipolar transistorInfo
- Publication number
- JPS5734365A JPS5734365A JP8977181A JP8977181A JPS5734365A JP S5734365 A JPS5734365 A JP S5734365A JP 8977181 A JP8977181 A JP 8977181A JP 8977181 A JP8977181 A JP 8977181A JP S5734365 A JPS5734365 A JP S5734365A
- Authority
- JP
- Japan
- Prior art keywords
- bipolar transistor
- symmetrical bipolar
- symmetrical
- transistor
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17638680A | 1980-08-08 | 1980-08-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5734365A true JPS5734365A (en) | 1982-02-24 |
JPS6150390B2 JPS6150390B2 (ja) | 1986-11-04 |
Family
ID=22644151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8977181A Granted JPS5734365A (en) | 1980-08-08 | 1981-06-12 | Symmetrical bipolar transistor |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0045848B1 (ja) |
JP (1) | JPS5734365A (ja) |
CA (1) | CA1161964A (ja) |
DE (1) | DE3167300D1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952521A (en) * | 1985-04-26 | 1990-08-28 | Fujitsu Limited | Process for fabricating a semiconductor device with selective growth of a metal silicide |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59161867A (ja) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | 半導体装置 |
JPS59217364A (ja) * | 1983-05-26 | 1984-12-07 | Sony Corp | 半導体装置の製法 |
FR2547954B1 (fr) * | 1983-06-21 | 1985-10-25 | Efcis | Procede de fabrication de composants semi-conducteurs isoles dans une plaquette semi-conductrice |
EP0208795A1 (en) * | 1985-07-12 | 1987-01-21 | International Business Machines Corporation | Method of fabricating a self-aligned metal-semiconductor FET |
GB2179787B (en) * | 1985-08-26 | 1989-09-20 | Intel Corp | Buried interconnect for mos structure |
US4792837A (en) * | 1986-02-26 | 1988-12-20 | Ge Solid State Patents, Inc. | Orthogonal bipolar transistor |
JPH0239340Y2 (ja) * | 1986-06-13 | 1990-10-22 | ||
US4860077A (en) * | 1987-09-28 | 1989-08-22 | Motorola, Inc. | Vertical semiconductor device having a sidewall emitter |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1352044A (en) * | 1971-04-21 | 1974-05-15 | Garyainov S A Glazkov I M Raik | Planar semiconductor device |
US3904450A (en) * | 1974-04-26 | 1975-09-09 | Bell Telephone Labor Inc | Method of fabricating injection logic integrated circuits using oxide isolation |
FR2369652A1 (fr) * | 1976-10-29 | 1978-05-26 | Radiotechnique Compelec | Memoire morte programmable a transistors |
US4098618A (en) * | 1977-06-03 | 1978-07-04 | International Business Machines Corporation | Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation |
-
1981
- 1981-06-12 JP JP8977181A patent/JPS5734365A/ja active Granted
- 1981-07-06 DE DE8181105228T patent/DE3167300D1/de not_active Expired
- 1981-07-06 EP EP19810105228 patent/EP0045848B1/en not_active Expired
- 1981-07-07 CA CA000381224A patent/CA1161964A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952521A (en) * | 1985-04-26 | 1990-08-28 | Fujitsu Limited | Process for fabricating a semiconductor device with selective growth of a metal silicide |
Also Published As
Publication number | Publication date |
---|---|
DE3167300D1 (en) | 1985-01-03 |
EP0045848B1 (en) | 1984-11-21 |
CA1161964A (en) | 1984-02-07 |
EP0045848A1 (en) | 1982-02-17 |
JPS6150390B2 (ja) | 1986-11-04 |
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