EP0021250B1 - Dispositif de signalisation de circulation - Google Patents

Dispositif de signalisation de circulation Download PDF

Info

Publication number
EP0021250B1
EP0021250B1 EP80103250A EP80103250A EP0021250B1 EP 0021250 B1 EP0021250 B1 EP 0021250B1 EP 80103250 A EP80103250 A EP 80103250A EP 80103250 A EP80103250 A EP 80103250A EP 0021250 B1 EP0021250 B1 EP 0021250B1
Authority
EP
European Patent Office
Prior art keywords
signal
time
question
groups
signal group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80103250A
Other languages
German (de)
English (en)
Other versions
EP0021250A1 (fr
Inventor
Heinrich Dipl.-Ing. Brunner
Karin Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19792925333 external-priority patent/DE2925333A1/de
Priority claimed from DE19792938528 external-priority patent/DE2938528A1/de
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT80103250T priority Critical patent/ATE1961T1/de
Publication of EP0021250A1 publication Critical patent/EP0021250A1/fr
Application granted granted Critical
Publication of EP0021250B1 publication Critical patent/EP0021250B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/097—Supervising of traffic control systems, e.g. by giving an alarm if two crossing streets have green light simultaneously

Definitions

  • the invention relates to a traffic signal system having a plurality of signal groups which can be switched by means of setting signals, in which a setting signal causing the release of a free signal by a signal group (entry signal group) is made dependent on the passage of intermediate times, each individually with respect to signal groups hostile to the entry signal group in question are defined and recorded in memories and their expiry is time-controlled.
  • Such a traffic signal system is known from DE-A-2 348 666.
  • this known traffic signal system mutual signal security between enemy signal groups is ensured while simultaneously forming the required intermediate times.
  • the respective intermediate times are stored with the aid of time counters which are assigned to each entry signal group and which can be set in motion via an AND link of a green command and release commands. During its expiry, the time counter in turn issues release or lock commands.
  • the green switch-on signal can be tapped off at such a time by such a time counter. The enable and disable commands of a time counter are returned to the AND logic circuits that are assigned to the other signal groups.
  • a prematurely arriving green signal command at an AND logic circuit can therefore only become effective if release commands are available from the time counters assigned to the enemy signal groups.
  • this traffic signal system it is possible to individually set different intermediate times. For this purpose, connections are made on a special printed circuit board between sets of conductor tracks running at right angles to one another, the one set of conductor tracks being arranged on one side and the other set of conductor tracks on the other side of the printed circuit board.
  • the object of the present invention is to provide a traffic signal system in which the definition and assurance of the intermediate times takes place in a manner which is particularly suitable for enabling the control of the traffic signal system by a microcomputer.
  • this object is achieved in that only the largest of the intermediate times in question is additionally recorded in a special memory and is reduced in a clock-controlled manner in that a memory comparison between the content of the special memory and the content of the data is made in the rhythm of the clock cycle the interim-containing memory is carried out so that the point in time of the beginning of each intermediate time is determined by a zero difference resulting from such a memory comparison, and that a blocking setting signal which causes the blocking signal group to be emitted by the respective blocking signal group is generated at the respective starting points in time and that finally, with the simultaneous end of all intermediate times, the generation of the setting signal for emitting a free signal is effected by the relevant entry signal group.
  • certain entry signal groups are assigned specially marked intermediate times, that the expiry of such a marked intermediate time is effected together with the start of the smallest unmarked intermediate time and that such marked intermediate time only has its end for generating a free signal of the relevant entry signal group effecting setting signal is evaluated.
  • a query circuit is connected to an intermediate time matrix containing the intermediate times, which in each case reads the intermediate times of the relevant entry signal groups with respect to the hostile signal signal groups from the intermediate times matrix and this in the respective entry signal groups associated registers and the largest intermediate time of these intermediate times is additionally stored in a separate memory associated with the entry signal group in question, where the stored value of the relevant largest intermediate time can be reduced rhythmically to zero, that the registers and the memory are subordinated to the subtractor circuits, the difference between the Memory content and the register contents form that the query circuit is connected to its control with counters, one of which has entry signal groups due to its counter positions and the other of which has its counter positions which correspond to the respective E designated infahr signal group hostile clearing signal groups and that the counters are connected to a control device for their setting, that separate registers are provided for storing the specially marked intermediate times, which with a control input only reduce their respective intermediate times in value control pulses from a linkage arrangement the beginning of an unmarked intermediate time, that the logic arrangement has
  • Fig. 1 The intersection shown in Fig. 1 has four approaches, with respect to which only three traffic flows 1, 2 and 4 are indicated. As can be seen, the two traffic flows 1 and 2 are hostile to the traffic flow 4. To enable or stop the traffic flows 1, 2 and 4 indicated in FIG. 1, these individual signal generators Sg1 or Sg2 or Sg4 are associated. In the case of a traffic intersection, these signal transmitters may contain green and red signal lamps in the simplest case.
  • the circuit arrangement according to FIG. 2 contains, inter alia, an intermediate time matrix ZM, for example associated with the intersection shown in FIG. 1, which contains information about intermediate times between mutually hostile traffic flows or signal groups.
  • an intermediate time matrix ZM for example associated with the intersection shown in FIG. 1, which contains information about intermediate times between mutually hostile traffic flows or signal groups.
  • entry signal groups Sge are indicated in the top line of the intermediate time matrix ZM - these are signal groups that release their associated traffic flows (i.e. receive green signals).
  • So-called clearing signal groups Sgr are listed in the left outer column of the intermediate time matrix ZM - these are those signal groups which block their associated traffic flows (ie receive red signals).
  • the intermediate time matrix ZM contains an indication of the time after which the respective entry signal group can receive a green signal if the respective evacuation signal group is hostile to it Sgr has received a green end signal.
  • the intermediate time matrix ZM is connected to an interrogation circuit, which essentially consists of two read circuits Rc1, Rc2. These read circuits Rc1, Rc2 are indicated as circuits containing AND gates GU11 to GU1n and GU21 to GU2n, which are connected with their one inputs to one of two output sides of the intermediate time matrix ZM.
  • the interrogation circuit Rc1 is connected to the cells of the intermediate time matrix ZM designated by the individual clearing signal groups Sgr.
  • the interrogation circuit Rc2 is connected with its one input side to the cells of the intermediate time matrix ZM designated by the individual entry signal groups Sge.
  • the two interrogation circuits Rcl, Rc2 each have their own counter Cnt1 and Cnt2, which can be set by a control device PC.
  • the counter Cnt1 determines the clearing signal group Sgr by means of its respective counter position, with respect to which information can be read out from the intermediate time matrix ZM by means of the query circuit Rc1.
  • the arrangement can be made such that all the information entered with regard to a clearing signal group Sgr in the intermediate time matrix ZM is read out from this matrix by means of the query circuit Rc1 and that the signals or information thus obtained with the counter setting of the counter Cnt2 in separate AND gates GUr1, GUr2 are linked. This then ensures a clear assignment of the information representing the intermediate times of the respective clearing signal group to the friendly entry signal group Sge.
  • the respective counter position of the counter Cnt2 also determines the entry signal group Sge with which the query circuit Rc2 reads information from the intermediate time matrix ZM.
  • the interrogation circuit Rc2 should be designed such that it only reads out the largest numerical value for each entry signal group Sge from the intermediate time matrix ZM. In the case of the entry signal group Sge denoted by “4”, only the value “6” is thus read out of the intermediate time matrix ZM by means of the query circuit Rc2.
  • This largest intermediate value which is decisive for the respective entry signal group, is output by the query circuit Rc2 to a memory cell of a memory Spe which is individually associated with the entry signal group in question.
  • the value 6 is stored in a memory cell Sp4e of the memory Spe.
  • the memory Spe in question can be directly connected with its memory cells to corresponding outputs of the query circuit Rc2.
  • On one input labeled ST is supplied to the memory Spe in a fixed cycle of, for example, 1 sec. control pulses, upon the occurrence of which the content of each memory cell of this memory Spe is reduced by a certain value, for example by 1.
  • Registers Sp1t and Sp2t are connected on the input side to the outputs of the AND gates GUr1 and GUr2 already considered. These registers Splt, Sp2t are permanently assigned to the entry signal group labeled “4”. This is indicated by a 4 in the right part of the respective register Splt, Sp2t.
  • the clearing times representing the clearing times are entered, which have the clearing signal groups Sgr designated “1” or “2” in the intermediate times matrix ZM with respect to the entry signal group Sge designated “4”. Accordingly, the value 3 is entered in the register Sp1t, and the value 6 is entered in the register Sp2t.
  • Subtractor circuits with their one inputs are connected to the outputs of the two registers last viewed.
  • a subtracting circuit Sub1 is connected to the one input side of the output side of the register Sp1t.
  • a subtraction circuit Sub2 is connected with its one input side. With their respective other input side, the subtracting circuits Sub1 and Sub2 are jointly connected to the output of one of the memory cells of the memory Spe. This is the memory cell which belongs to the entry signal group and to which the registers Splt, Sp2t connected to the subtracting circuits Sub1, Sub2 also belong.
  • An evaluation circuit Sw1, Sw2 or Sw4 is connected to the outputs of the subtracting circuits Sub1, Sub2 and to the output side of the memory cell Sp4e of the memory Spe.
  • These evaluation circuits may be threshold value circuits which emit a binary signal “H” on the output side when they are supplied with an input signal which is characteristic of a difference value of zero between two subtracted numbers or for a time specification reduced to zero.
  • the relevant evaluation circuits may output a corresponding binary signal “H” on the output side even if the difference signal supplied to them on the input side is characteristic of a negative difference between the numbers subtracted from one another.
  • the signal circuits Sg1, Sg2 and Sg4 already mentioned in connection with FIG. 1 are associated with the evaluation circuits Sw1, Sw2, Sw4 just considered.
  • the signal generator Sg1 is connected on the input side to outputs Q, Q of a bistable flip-flop BK1, which is connected directly to a reset input R and to a set input S via a negation element GN1 at the output of the evaluation circuit Sw1.
  • the signal generator Sg2 is connected on the input side in a corresponding manner to outputs Q, Q of a bistable flip-flop BK2, which is connected directly to a reset input R and to a set input S via a negation element GN2 at the output of the evaluation circuit Sw2.
  • the signal generator Sg4 is finally connected in a corresponding manner on the input side to the outputs Q, Q of a bistable flip-flop BK4, which is connected directly to the output of the evaluation circuit Sw4 with its set input S and with its reset input R via a negation element GN4.
  • the circles in the signal transmitters Sg1, Sg2, Sg4 indicated in FIG. 2 and provided with a horizontal line are intended to indicate the respective green signal lamp; however, a circle with a vertical line should indicate the red signal lamp in the respective signal transmitter.
  • the query circuits Rc1 and Rc2 read time information from the intermediate time matrix ZM and into the relevant registers such as the registers Sp1t, Sp2t, and into a memory cell or a memory section, such as Sp4e, of the memory Spe is stored. This is followed by a subtraction in the subtracting circuits Sub1, Sub2 between the corresponding times.
  • the two bistable flip-flops BK1 and BK2 may be set so that the two signal generators Sg1 and Sg2 light up their green signal lamps. It is further assumed that the bistable flip-flop BK4 is reset, so that the red signal lamp of the signal generator Sg4 lights up.
  • the subtracting circuit represents Sub2 immediately there is a zero difference between the subtracted numerical values.
  • the evaluation circuit Sw2 then outputs a binary signal “H” on the output side, upon the occurrence of which the bistable flip-flop BK2 is reset. As a result, the green signal lamp of the signal generator Sg2 goes out, and instead the red signal lamp of this signal generator Sg2 lights up. This time corresponds to the time t0 in FIG. 3.
  • the subtracting circuit Sub1 Since - as already explained above - the numbers or time values stored in the memory cells of the memory Spe are cyclically successively reduced, for example in a rhythm of one second, the subtracting circuit Sub1 will successively form a smaller and smaller difference between the time values subtracted from each other. If the value of the time values stored in the memory cells of the memory Spe is reduced by a value of 1 each in a rhythm of one second, the subtracting circuit Sub1 after three seconds from the aforementioned time t0 likewise becomes the presence of a zero difference between them determine subtracted time values.
  • the evaluation circuit Sw1 then outputs a binary signal "H", which leads to the resetting of the bistable flip-flop BK1.
  • the green signal lamp of the signal generator Sgl then goes out, and the red signal lamp of this signal generator Sg1 now lights up. This time corresponds to time t3 according to FIG. 3.
  • the evaluation circuit Sw4 connected to this memory cell inputs on the output side Binary signal »H «.
  • the bistable flip-flop BK4 is set, as a result of which the red signal lamp which was lit up to this point in the signal transmitter Sg4 goes out, and instead the green signal lamp of this signal transmitter Sg4 lights up. This time corresponds to time t6 according to FIG. 3.
  • the two counters Cnt1, Cnt2 of the circuit arrangement shown in FIG. 1 are connected to the output of a control device PC.
  • the two counters receive their counter setting signals from this control device PC.
  • the delivery of these counter setting signals will take place in accordance with the overall signal plan to be processed, with respect to which the required intermediate times between the individual signal groups which are hostile to one another are contained in the intermediate time matrix ZM.
  • the control device PC therefore only needs to set the two counters Cnt1, Cnt2 at the time t0 according to FIG. 3.
  • the control device PC can contain information about the required meter settings (these are the meter setting signals) in a correspondingly defined schedule. In this case, the relevant control device PC will provide the corresponding information in good time.
  • traffic flows 1 and 2 which are hostile to traffic flow 4, first stop traffic flow 2 and only then traffic flow 1 is stopped.
  • the traffic flow 2 has a longer clearing time than the traffic flow 1, based on the release of the traffic flow 4.
  • Such a different stopping of the traffic flows 1, 2 with respect to the release of the traffic flow 4 can thus optimally do justice to actual conditions .
  • the intersection shown in FIG. 4 has four approaches, with respect to which only four traffic flows 1, 2, 4 and 5 are indicated. As can be seen, the two traffic flows 1 and 2 are hostile to the two traffic flows 4 and 5. To enable or stop the traffic flows 1, 2, 4 and 5 indicated in FIG. 1, these individual signal generators Sg1, Sg2, Sg4 and Sg5 are associated. In the case of a traffic intersection, these signal transmitters may contain green and red signal lamps in the simplest case.
  • FIG. 5 shows a circuit arrangement according to a second embodiment of the invention.
  • This circuit arrangement which essentially corresponds to the circuit arrangement shown in FIG. 1, allows the signal generators Sg1, Sg2, Sg4 and Sg5 indicated in FIG. 4 to be controlled in a manner which will be explained in more detail below.
  • the circuit arrangement in question contains, inter alia, an intermediate time matrix ZM, for example associated with the intersection shown in FIG. 4, which contains information about intermediate times between mutually hostile traffic flows or signal groups.
  • the top line of the split times matrix ZM so-called entry signal groups Sge specified - these are signal groups that release their associated traffic flows (i.e. receive green signals).
  • So-called clearing signal groups Sgr are listed in the left outer column of the intermediate time matrix ZM - these are those signal groups which block their associated traffic flows (ie receive red signals).
  • the intermediate time matrix ZM contains an indication of the time after which the respective entry signal group can receive a green signal when the friendly clearing signal group Sgr received a green end signal.
  • the entry signal group Sge labeled "4" can receive a green signal at a point in time which is three seconds after the end of the green of the clearing signal group Sgr labeled 1 "" and which lies, for example, six seconds after the end of green of the clearing signal group Sgr designated "2".
  • the entry signal group Sge designated “5” is to receive a green signal at a time which is eight seconds after the end of green of the two clearing signal groups Sgr1 and Sgr2.
  • the intermediate time matrix ZM is connected to an interrogation circuit, which essentially consists of two read circuits Rc1, Rc2. These read circuits Rc1, Rc2 are indicated as circuits containing AND gates GU11 to GU1n and GU21 to GU2n, which are connected with their one inputs to one of two output sides of the intermediate time matrix ZM.
  • the interrogation circuit Rc1 is connected to the cells of the intermediate time matrix ZM designated by the individual clearing signal groups Sgr.
  • the interrogation circuit Rc2 is connected with its one input side to the cells of the intermediate time matrix ZM designated by the individual entry signal groups Sge.
  • the two interrogation circuits Rc1, Rc2 each have their own counter Cnt1 and Cnt2, which can be set by a control device PC.
  • the counter Cnt1 defines the clearing signal group Sgr by means of its respective counter position, with respect to which information can be read out from the intermediate time matrix ZM by means of the query circuit Rc1.
  • the arrangement can be such that the query circuit Rc1 in each case reads out all the information entered with regard to a clearing signal group Sgr in the intermediate time matrix ZM from this matrix and that the signals or information obtained in this way with the counter setting of the counter Cnt2 in separate AND gates GUr1, GUr2 are linked. This then ensures a clear assignment of the information representing the intermediate times of the respective clearing signal group to the hostile entry signal group Sge.
  • the respective counter position of the counter Cnt2 also determines the entry signal group Sge with which the query circuit Rc2 reads information from the intermediate time matrix ZM.
  • the interrogation circuit Rc2 should be designed such that it only reads out the largest numerical value for each entry signal group Sge from the intermediate time matrix ZM. In the case of the entry signal group Sge denoted by “4”, only the value “6” is thus read out of the intermediate time matrix ZM by means of the query circuit Rc2. With regard to the entry signal group "5" - which may be a pedestrian signal group - the value "8" is read out of the split time matrix ZM by means of the query circuit Rc2.
  • control pulses are supplied to the memory Spe in a fixed cycle of, for example, 1 sec, upon the occurrence of which the content of those memory cells of this memory Spe is reduced by a certain value, for example by 1, associated with the relevant input ST are connected. In the present case, this applies to the memory or register cell Sp4e, but not to the memory or register cell Sp5e.
  • This last-mentioned register cell Sp5e receives corresponding control pulses via an AND gate GU2e, which will be discussed below.
  • Registers Sp1t and Sp2t are connected on the input side to the outputs of the AND gates GUr1 and GUr2 already considered. These registers Sp1t, Sp2t are permanently assigned to the entry signal group labeled “4”. This is indicated by a 4 in the right part of the respective register Sp1t, Sp2t.
  • the clearing times representing the clearing times are entered, which have the clearing signal groups Sgr designated “1” or “2” in the intermediate times matrix ZM with respect to the entry signal group Sge designated “4”. Accordingly, the value 3 is entered in the register Sp1t, and the value 6 is entered in the register Sp2t.
  • Subtractor circuits Sub1 are at the outputs of the two registers last viewed or Sub2 with their one inputs connected.
  • a subtracting circuit Sub1 is connected to the one input side of the output side of the register Sp1t.
  • a subtraction circuit Sub2 is connected with its one input side. With their respective other input side, the subtracting circuits Sub1 and Sub2 are jointly connected to the output of one of the memory cells of the memory Spe. This is the memory cell which belongs to the entry signal group and to which the registers Splt, Sp2t connected to the subtracting circuits Sub1, Sub2 also belong.
  • An evaluation circuit Sw1, Sw2 and Sw4 is connected to the outputs of the subtracting circuits Subl, Sub2 and to the output side of the memory cell Sp4e of the memory Spe.
  • These evaluation circuits may be threshold value circuits which emit a binary signal “H” on the output side when they are supplied with an input signal which is characteristic of a difference value of zero between two subtracted numbers or for a time specification reduced to zero.
  • the relevant evaluation circuits may also output a corresponding binary signal “H” on the output side if the difference signal supplied to them on the input side is characteristic of a negative difference between the numbers subtracted from one another.
  • the signal circuits Sg1, Sg2 and Sg4 already mentioned in connection with FIG. 4 belong to the evaluation circuits Sw1, Sw2, Sw4 just considered.
  • the signal generator Sg1 is connected on the input side to the connections Q, Q of a bistable flip-flop BK1, which is connected directly to a reset input R and to a set input S via a negation element GN1 at the output of the evaluation circuit Sw1.
  • the signal generator Sg2 is connected on the input side in a corresponding manner to outputs Q, Q of a bistable flip-flop BK2, which is connected directly to a reset input R and to a set input S via a negation element GN2 at the output of the evaluation circuit Sw2.
  • the signal generator Sg4 is finally connected in a corresponding manner on the input side to the outputs Q, Q of a bistable flip-flop BK4, which is connected directly to the output of the evaluation circuit Sw4 with its set input S and with its reset input R via a negation element GN4.
  • the circles in the signal generators Sg1, Sg2, Sg4 and Sg5 indicated in FIG. 5 and provided with a horizontal line are intended to indicate the respective green signal lamp; however, a circle with a vertical line should indicate the red signal lamp in the respective signal transmitter.
  • an AND element GU1e is also provided in the circuit arrangement shown in FIG. 5, which together with the AND element GU2e already mentioned forms a logic arrangement.
  • the inputs of the AND gate GU1e are connected to the outputs of the two evaluation circuits Sw1 and Sw2.
  • the output of the AND gate GU1e is connected to an input of the AND gate GU2e.
  • This AND gate GU2e is connected to a further input at the switching point ST, to which control pulses are supplied.
  • the AND gate GU2e emits the control pulses supplied to it from the switching point ST in the event that it is capable of transmission.
  • an evaluation circuit Sw5 is connected, which may be designed in a manner corresponding to the other evaluation circuits Sw1, Sw2, Sw4 previously mentioned.
  • another bistable flip-flop BK5 with its set input S is connected directly and with its reset input R via a negation element GN5.
  • the signal generator Sg5 is connected to the outputs Q, Q of this bistable flip-flop BK5.
  • the mode of operation of the circuit arrangement shown in FIG. 5 is explained in more detail below.
  • the signal sequence shown in FIG. 6 is also dealt with, by which the mode of operation of the circuit arrangement in question is particularly well illustrated. 6, the control processes to be carried out for the individual signal generators Sg1, Sg2, Sg4 and Sg5 according to FIGS. 4 and 5 are illustrated.
  • a red signal phase is indicated by the thick lines, and a green signal phase is indicated by the thin lines.
  • a green end is indicated by a circle, and a red end is indicated by a short vertical line.
  • the transition times red / yellow or yellow are not taken into account in the illustration in question, since these are not essential here for understanding the invention.
  • the query circuits Rc1 and Rc2 read out time information from the intermediate time matrix ZM and into the relevant registers, such as the registers Sp1t, Sp2t, and into corresponding memory respectively. Register cells such as Sp4e and Sp5e of the memory Spe are stored. Subsequently, in the subtracting circuits Subl, Sub2, a difference is formed between the time information stored in the registers Sp1t and Sp2t.
  • the present circuit arrangement for influencing or determining a signal change does not take into account the intermediate times of all entry signal groups which are hostile to one and the same clearing signal groups. Rather, in the present case the intermediate times of selected entry signal groups are disregarded in that the relevant intermediate times are marked separately.
  • the run-in split time of the run-in signal group Sge5 is such a marked split time.
  • This intermediate time "8" has been stored in the intermediate times matrix ZM in the register Sp5e. In this separate register, this intermediate time "8" remains unchanged as a kind of marked intermediate time until the entry intermediate times 3 and 6 of the clearing signal groups Sgr1 and Sgr2 expire.
  • the evaluation circuit Sw5 emits a binary signal “H” on the output side, by means of which the bistable flip-flop BK5 is set, so that the signal generator Sg5 lights up its green signal lamp. It is assumed that the signal generator Sg5 as well as the signal generator Sg4 are initially reset so that the red signal lamps of these signal generators first light up.
  • the diagram shown in FIG. It can be seen from the signal sequence shown in FIG. 6 that only the signal generator Sg2 receives a green end signal at the time t0, so that it lights up its red signal lamp from the time t0. At this point, the signal generator Sg1 still lights up its green signal lamp, while the signal generators Sg4 and Sg5 still light up their red signal lamps. At the time t3 - which may be three seconds after the time t0 - the signal generator Sg1 then also receives a green end signal, whereupon this signal generator Sg1 lights up its red signal lamp. The signal generators Sg4 and Sg5 continue to light up their red signal lamps.
  • the AND gate GUle outputs a binary signal “H” on the output side. From this time t3, the intermediate time information 8 contained in the register Sp5e is gradually reduced to 0. Since in the present case this takes place every second, the signal generator Sg5 only switches on its green signal lamp eight seconds after the time t3, that is to say at the time t11. Due to the different stopping of the traffic flows 1 and 2 with respect to the release of the traffic flows 4 and 5, it is thus possible in an optimal manner to actually take into account the existing conditions, while at the same time selectively the intermediate times of the entry points to be taken into account for the definition or influencing of the respective signal change. Signal groups can be selected. In other words, this means that the intermediate times of selected entry signal groups can be selectively disregarded in a corresponding manner.
  • An intermediate time of this type that has not been taken into account is the intermediate time 8 of the entry signal group 5 entered in the intermediate times matrix ZM according to FIG. 5.
  • entry signal group 5 it should also be noted that its entry intermediate time of eight seconds in the present case is only based on the enemy evacuation signal group Sg1 is observed, while there is a longer intermediate time to the enemy signal group Sg2 than by the intermediate time measure trix ZM required.
  • this is accepted in the present case, since the procedure described ensures that the entry signal group Sge5 cannot, because of its relatively long meantime, promptly terminate the clearing signal groups Sgr1 and Sgr2, which are hostile to it, in the event that these clearing signal groups each still have a green signal.
  • the marking can also be carried out in such a way that corresponding marking information is included in the split times matrix, which causes the corresponding split times to be treated accordingly when the associated split times are read out.
  • the two counters Cnt1 and Cnt2 of the relevant circuit arrangement receive counter setting signals from the control device PC.
  • the delivery of these counter setting signals will take place in accordance with the overall signal plan to be processed, with respect to which the required intermediate times between the individual signal groups which are hostile to one another are contained in the intermediate times matrix ZM.
  • the control device PC therefore only needs to set the two counters Cnt1, Cnt2 at the time t0 according to FIG. 6.
  • the control device PC can contain information about the required meter settings (these are the relevant meter setting signals) in a correspondingly defined schedule. In this case, the control device PC will provide the corresponding information in good time. This can be done in such a way that all details of the intermediate time matrix ZM are read out in a rhythm of one second, as is also the case with the circuit arrangement according to FIG. 2.
  • circuit arrangements explained in connection with FIGS. 2 and 5 can not only be implemented in discrete circuit technology, but can also be constructed using a microcomputer system using at least one microprocessor.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Traffic Control Systems (AREA)
  • Time Recorders, Dirve Recorders, Access Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)

Claims (6)

1. Installation de signalisation de circulation comportant une majeure partie de groupes de signaux (Sg1, Sg2, Sg4) commutables au moyen de signaux de réglage, dans laquelle un signal de réglage provoquant la délivrance d'un signal de libération par un groupe de signaux (groupe de signaux de passage Sg4) est rendu dépendant de l'écoulement d'intervalles de temps (3, 6) qui sont déterminés respectivement de façon individuelle par rapport à des groupes de signaux (groupes de signaux de blocage Sgl, Sg2) incompatibles avec le groupe concerné de signaux de passage (Sg4) et sont consignés dans des mémoires (Sp1t, Sp2t, Sp4e), et dont l'écoulement a lieu de façon commandée en cadence, caractérisée en ce que simplement les plus importants des intervalles de temps (6) venant respectivement en question sont reçus en supplément dans une mémoire particulière (Sp4e) et sont diminués dans celle-ci de façon commandée en cadence, qu'au rythme de la cadence est respectivement effectuée une comparaison des données mémorisées entre le contenu de la mémoire particulière (Sp4e) et le contenu de la mémoire (Sp1t, Sp2t) contenant les intervalles de temps(3, 6), que l'instant du début de chaque intervalle de temps (3, 6) est déterminé par une différence nulle apparaissant lors d'une telle comparaison des données mémorisées, et qu'aux instants de débuts respectifs (t0, t3) est respectivement produit un signal de réglage d'arrêt provoquant la délivrance d'un signal d'arrêt par le groupe respectif de signaux d'arrêt (Sg1, Sg2), et qu'enfin la production du signal de réglage pour la délivrance d'un signal de libération par le groupe concerné de signaux de passage (Sg4) s'effectue avec la fin simultanée de tous les intervalles de temps (3, 6).
2. Installation de signalisation de circulation suivant la revendication 1, caractérisée par le fait que des intervalles de temps repérés de façon particulière (8) sont associés à des groupes (Sg5) de signaux de passage, que l'écoulement d'un tel intervalle de temps repéré a lieu avec le début du plus petit intervalle de temps non repéré (3), et qu'un tel intervalle de temps repéré (8) est évalué simplement à la fin pour fournir un signal de réglage donnant lieu à un signal de libération du groupe concerné (Sg5) de signaux de passage.
3. Installation de signalisation de circulation suivant la revendication 1, caractérisée par le fait qu'à une matrice (ZM) d'intervalles de temps contenant les intervalles de temps de façon classée, est relié un circuit d'interrogation (Rcl, Rc2) qui lit respectivement, à partir de la matrice (ZM) d'intervalles de temps, les intervalles de temps des groupes concernés (Sge) de signaux de passage par rapport aux groupes (par exemple Sge4) de signaux d'arrêt qui leur sont incompatibles, et mémorise ceux-ci, dans les registres associés (Sp1t, Sp2t) et le plus important de ces intervalles de temps (6) en supplément dans une mémoire distincte (Spe) associé au groupe concerné (Sge4) de signaux de passage, où la valeur mémorisée de l'intervalle de temps le plus important concerné (6) peut être diminuée en rythme jusqu'à zéro, et qu'en aval des registres (Splt, Sp2t) et de la mémoire (Spe) sont disposés des circuits soustracteurs (Subl, Sub2) qui forment la différence entre le contenu de la mémoire et les contenus des registres.
4. Installation de signalisation de circulation suivant la revendication 3, caractérisée en ce que pour sa commande le circuit d'interrogation (Rc1, Rc2) est relié à des compteurs (Cntl, Cnt2) dont l'un indique, par ses positions de comptage, des groupes (Sge) de signaux de passage et dont l'autre indique, par ses positions de comptage, les groupes (Sgr) de signaux d'arrêt incompatibles avec le groupe respectif de signaux de passage, et que pour leur réglage les compteurs (Cnt1, Cnt2) sont reliés à un dispositif de commande (FC).
5. Installation de signalisation de circulation suivant la revendication 2, caractérisée en ce que pour la mémorisation des intervalles de temps repérés de façon particulière (8) sont prévus des registres particuliers (Sp5e) qui reçoivent, sur une entrée de commande, leurs impulsions de commande réduisant la valeur des intervalles de temps respectivement mémorisées provenant d'un agencement combinatoire (GU2e, GU1e), seulement au début d'un intervalle de temps non repéré (3).
6. Installation de signalisation de circulation suivant la revendication 5, caractérisée par le fait que l'agencement combinatoire comporte un premier élément ET (GU1e) et un second élément ET (GU2e), et que le premier élément ET (GU1e) est relié côté entrée à des circuits d'évaluation (Sw1, Sw2) délivrant des signaux de réglage, qui sont associés aux groupes (Sg1, Sg2) de signaux respectivement incompatibles, et qu'en outre le second élément ET (GU2e) est raccordé, côté entrée, à une source d'impulsions de commande (ST) et à la sortie du premier élément ET (GU1e).
EP80103250A 1979-06-22 1980-06-11 Dispositif de signalisation de circulation Expired EP0021250B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT80103250T ATE1961T1 (de) 1979-06-22 1980-06-11 Verkehrssignalanlage.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE19792925333 DE2925333A1 (de) 1979-06-22 1979-06-22 Verfahren und schaltungsanordnung zur erzeugung von einstellsignalen fuer signalgeber einer verkehrssignalanlage, insbesondere einer strassenverkehrssignalanlage
DE2925333 1979-06-22
DE2938528 1979-09-24
DE19792938528 DE2938528A1 (de) 1979-09-24 1979-09-24 Verfahren und schaltungsanordnung zur erzeugung von einstellsignalen fuer signalgeber einer verkehrssignalanlage, insbesondere einer strassenverkehrssignalanlage

Publications (2)

Publication Number Publication Date
EP0021250A1 EP0021250A1 (fr) 1981-01-07
EP0021250B1 true EP0021250B1 (fr) 1982-12-08

Family

ID=25779639

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80103250A Expired EP0021250B1 (fr) 1979-06-22 1980-06-11 Dispositif de signalisation de circulation

Country Status (4)

Country Link
US (1) US4323970A (fr)
EP (1) EP0021250B1 (fr)
DE (1) DE3061263D1 (fr)
NO (1) NO152390C (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182555A (en) * 1990-07-26 1993-01-26 Farradyne Systems, Inc. Cell messaging process for an in-vehicle traffic congestion information system
US5164904A (en) * 1990-07-26 1992-11-17 Farradyne Systems, Inc. In-vehicle traffic congestion information system
US5173691A (en) * 1990-07-26 1992-12-22 Farradyne Systems, Inc. Data fusion process for an in-vehicle traffic congestion information system
US5257194A (en) * 1991-04-30 1993-10-26 Mitsubishi Corporation Highway traffic signal local controller
US6466862B1 (en) * 1999-04-19 2002-10-15 Bruce DeKock System for providing traffic information
US20060074546A1 (en) * 1999-04-19 2006-04-06 Dekock Bruce W System for providing traffic information
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing
MX344434B (es) 2011-12-16 2016-12-15 Pragmatek Transp Innovations Inc Aprendizaje por refuerzo de agentes multiples para control de señales de transito adaptable, integrado y conectado en red.
US9978270B2 (en) 2014-07-28 2018-05-22 Econolite Group, Inc. Self-configuring traffic signal controller

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967245A (en) * 1970-03-06 1976-06-29 Omron Tateisi Electronics Co. Traffic signal control device with core memory
DE2044511C3 (de) * 1970-09-08 1974-05-02 Siemens Ag, 1000 Berlin U. 8000 Muenchen Straßenverkehrssignalanlage
US3885227A (en) * 1972-04-20 1975-05-20 Siemens Ag Street traffic signalling system
DE2348666C3 (de) * 1973-09-27 1978-08-24 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verkehrssignalanlage
DE2412963C3 (de) * 1974-03-18 1979-07-12 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur automatischen Schutzzeitüberwachung in Straßenverkehrssignalanlagen
DE2739616C3 (de) * 1977-09-02 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Verfahren und Einrichtung zur Sicherstellung der an einer Kreuzung erforderlichen Zwischenzeiten beim Betrieb einer Straßenverkehrssignalanlage

Also Published As

Publication number Publication date
NO152390B (no) 1985-06-10
DE3061263D1 (en) 1983-01-13
NO801773L (no) 1980-12-23
US4323970A (en) 1982-04-06
EP0021250A1 (fr) 1981-01-07
NO152390C (no) 1985-09-18

Similar Documents

Publication Publication Date Title
DE2614000C2 (de) Diagnoseeinrichtung zur Prüfung von Funktionseinheiten
DE2130299B2 (de) Eingabe-/Ausgabekanal für eine Datenverarb eitungsanlage
DE3015992A1 (de) Programmierbare logische anordnung
EP0021250B1 (fr) Dispositif de signalisation de circulation
DE2926322A1 (de) Speicher-subsystem
DE2210426C2 (de) Verfahren zur vorranggesteuerten Auswahl einer von mehreren Funktions einheiten zur Anschaltung an eine ihnen gemeinsam zugeordnete Einrichtung in Datenverarbeitungsanlagen und Schaltung zur Durchführung des Verfahrens
DE2854782A1 (de) Datenverarbeitungssystem
DE3501194A1 (de) Verfahren und vorrichtung zum datenaustausch zwischen mikroprozessoren
DE1191145B (de) Elektronische Zifferrechenmaschine
DE1499191B2 (de) Elektronische einrichtung fuer eine datenverarbeitungsanlage
EP0491998B1 (fr) Procédé commandé par programme et agencement pour la génération d'impulsions dans les intervalles de temps successifs
EP0012171B1 (fr) Dispositif de commande programmable
DE2739616C3 (de) Verfahren und Einrichtung zur Sicherstellung der an einer Kreuzung erforderlichen Zwischenzeiten beim Betrieb einer Straßenverkehrssignalanlage
DE2622974A1 (de) Mikroprogrammierbares steuerwerk
DE2002583C2 (de) Schaltung zum Vorwärts/Rückwärts-Zählen der von einem optischen System gelieferten Interferenzsstreifen
DE2727188A1 (de) Anordnung zum adressieren eines speichers
DE2857623C2 (de) Zeitfolgesteueranordnung
DE2954533C2 (fr)
DE2938528A1 (de) Verfahren und schaltungsanordnung zur erzeugung von einstellsignalen fuer signalgeber einer verkehrssignalanlage, insbesondere einer strassenverkehrssignalanlage
DE3314702C2 (fr)
EP0006488B1 (fr) Procédé pour l'exécution d'un saut d'adresse dans un dispositif de commande séquentielle à mémoire, destiné à la commande de machines, en particulier de machines à coudre industrielles, et circuits de commande séquentielle pour la réalisation du procédé
DE2317772C3 (de) Schaltungsanordnung für eine unter Verwendung eines gespeicherten Programms zentralgesteuerte, Funktionsblöcke enthaltende Vermittlungsanlage
DE2015129A1 (de) Patentwesen, Ost-Berlin WPI39039 Steuerbarer Taktgenerator für digitale informationsverarbeitende Systeme
DE2248451A1 (de) Pruefsystem in datenverarbeitungsanlagen
DE2007335A1 (de) Einrichtung zum Steuern von Verkehrsampelsignalen

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): AT BE CH DE FR GB IT NL SE

17P Request for examination filed

Effective date: 19810202

ITF It: translation for a ep patent filed

Owner name: STUDIO JAUMANN

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): AT BE CH DE FR GB IT NL SE

REF Corresponds to:

Ref document number: 1961

Country of ref document: AT

Date of ref document: 19821215

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3061263

Country of ref document: DE

Date of ref document: 19830113

ET Fr: translation filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19840626

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19840630

Year of fee payment: 5

Ref country code: BE

Payment date: 19840630

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19860630

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19870612

BERE Be: lapsed

Owner name: SIEMENS A.G. BERLIN UND MUNCHEN

Effective date: 19870630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19880101

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19881118

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19890228

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19890630

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19940914

Year of fee payment: 15

EUG Se: european patent has lapsed

Ref document number: 80103250.9

Effective date: 19880711

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 19950524

Year of fee payment: 16

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19950630

Ref country code: CH

Effective date: 19950630

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Effective date: 19960611

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19980819

Year of fee payment: 19

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990630

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT