EP0013342A1 - Verfahren zur Herstellung selbstausrichtender Feldeffekt-Transistoren des Metallhalbleitertyps - Google Patents
Verfahren zur Herstellung selbstausrichtender Feldeffekt-Transistoren des Metallhalbleitertyps Download PDFInfo
- Publication number
- EP0013342A1 EP0013342A1 EP79104878A EP79104878A EP0013342A1 EP 0013342 A1 EP0013342 A1 EP 0013342A1 EP 79104878 A EP79104878 A EP 79104878A EP 79104878 A EP79104878 A EP 79104878A EP 0013342 A1 EP0013342 A1 EP 0013342A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- approximately
- pickling
- thickness
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005554 pickling Methods 0.000 claims abstract description 16
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 4
- 239000012535 impurity Substances 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 229910021140 PdSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/139—Schottky barrier
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/143—Shadow masking
Definitions
- the present invention relates to a method for manufacturing field effect transistors (FET) and, more particularly, to a method for manufacturing field effect transistors of the metal-semiconductor type (MESFET).
- FET field effect transistors
- MESFET metal-semiconductor type
- One of the objects of the present invention is therefore to provide self-aligned MESFET devices having reduced series resistance.
- Another object of the invention is to provide insulation between the source, the drain and the door of a MESFET device.
- Another object of the invention is to produce, in a MESFET device, source and drain regions of silicon which are fixed to the semiconductor substrate.
- Another object of the invention is to provide a MESFET device having a minimum surface.
- the present invention makes it possible in particular to achieve the above objectives by using a technique for manufacturing self-aligned, field effect and Schottky barrier transistors (MESFET) as described below.
- MESFET self-aligned, field effect and Schottky barrier transistors
- a MESFET device is produced by depositing on an semiconductor body an epitaxial layer of opposite polarity, this layer being covered with a layer of Si0 2 , itself covered with a layer of Si 3 N 4 .
- a photo-sensitive resin is then deposited on the layer of Si 3 N 4 , exposed and developed to define a configuration of openings and to expose determined regions of the layer of Si 3N .
- the exposed parts of the Si3N4 layer and pickling is continued in the underlying Si0 2 layer so as to expose certain regions of the epitaxial layer.
- Doped silicon is then deposited on the exposed regions of the epitaxial silicon, then the unexposed parts of the photo-sensitive resin are removed so as to retain doped Si mesas constituting source and drain regions, the parts of the substrate located between these regions being reserved for the purpose of subsequent deposition of gate regions.
- a second layer of photo-sensitive resin is applied to the layer of Si 3 N 4 and to the Si mesas. This resin is then exposed and developed with the exception of the region reserved for the production of a metal door. The regions of the Si 3 N 4 layer exposed during development are removed by pickling, then the photo-sensitive resin is removed from the door regions. The Si mesas are oxidized. Finally, the Si 3 N 4 is removed by pickling, as is the underlying layer of Si0 2 .
- a metal door is defined, by means of an appropriate configuration, on the exposed epitaxial layer, using conventional techniques using the use of photosensitive resins. A suitable metallic layer can subsequently be deposited by evaporation to make source, drain and Schottky door contacts as well as the interconnection network.
- FIGS. 3A to 3G represent, in section, different stages of manufacture of a field effect and Schottky barrier transistor of the type represented in FIG. 2.
- FIG. 1 shows a MESFET device of the prior art.
- a semiconductor body 11 is covered with an epitaxial layer 12 of a polarity opposite to that of the body 11.
- a source 13, a door 14 and a drain 15 are deposited on the surface of the epitaxial layer 12.
- the source 13, door 14 and drain 15 are defined using standard lithographic techniques, which has the effect of leaving a space A between door 14 and source 13, and a space B between door 14 and drain 15 , each of said spaces corresponding approximately to the width of the door 14.
- the spaces A and B are, to a large extent, at the origin of the parasitic resistance of the device, and define the lower limits of the dimensions of the resulting MESFET.
- Figure 2 shows a MESFET device produced in accordance with the method of the present invention.
- the dimensions of the space A can be reduced between the source 13 and the door 14, and the space B between the door 14 and the drain 15 the thickness of an oxide layer 20.
- FIGS. 3A to 3G illustrate different stages of the production of a MESFET transistor in accordance with the method of the present invention.
- a MESFET device is produced on a semiconductor body 11 by first growing thereon an epitaxial layer 12 of opposite polarity. If, for example, the layer 12 is of type n, its thickness should be between 1000 ⁇ and 10 000 A and it should be doped by means of As or P until a level of 1 0 15 is obtained 1 0 16 donors per cm 3, the exact values being a function of the desired operating mode, that is to say, the enhancement mode or depletion mode.
- a layer of silicon dioxide 22 with a thickness of between 100 A and 1000 A approximately, is then deposited on the epitaxial layer 12.
- the thickness of the layer 22 should be approximately 150 A.
- This layer is then covered with a layer 24 of Si 3 N 4 , the thickness of which can vary between 200 A and 1000 A approximately and must be preferably about 500 A. If its thickness is less than about 200 ⁇ , the layer 24 does not sufficiently protect the underlying structure to avoid further oxidation.
- Layer 26 is then selectively exposed and developed to form a detailed configuration mined with openings 28, which has the effect of exposing regions 30 of the layer 24 of Si 3 N 4 .
- the technique used for the purposes of this selective exposure and of this development should preferably make it possible to obtain a profile 31, exhibiting a lateral stripping, as shown in FIG. 3B.
- a technique for obtaining such a profile is described in the article by BJ Carvanello, M. Hatzakis and JM Shaw, entitled “Process for Obtaining Undercutting of a Photoresist to Facilitate Lift Off", published in the publication entitled “IBM Technical Disclosure Bulletin "Vol. 19, No. 10, page 4048, March 1977.
- the exposed regions 30 of the layer 24 are pickled by means of a chemical pickling technique using a solution of H 3 PO 4 brought to a temperature of 180 ° C, or by means of reactive ions generated from a mixture of 70% CF 4 and 30% H 2 .
- the latter pickling technique will preferably be used.
- the pickling continues until the silicon nitride as well as the layer 22 of Si0 2 have been removed from the regions 30. This has the effect of exposing the regions 32 of the epitaxial layer 12, as shown in FIG. 3B .
- the doped Si covers the photo-sensitive resin with a layer of polysilicon 33 and forms a source 13 and a drain 15 of polysilicon, as shown in FIG. 3C.
- the epitaxial layer is n-type silicon
- silicon doped with phosphorus should be used until a level of 10 20 donors per cm 3 is obtained. Evaporation can be achieved by heating the silicon with an electron beam. The layers 26 and 33 can then be removed using a solvent such as acetone.
- Mesas 13 and 15 are then obtained serving respectively as source and drain, the region which separates them, C, being reserved for the purposes of the subsequent deposition of a door, as shown in Figure 3D.
- a second layer 36 of photo-sensitive resin having a thickness of between 5,000 A and approximately 10,000 A, is applied to the layer 24 of Si 3 N 4 and to the doped mesas 13 and 15.
- the layer 36 is selectively exposed and developed so as to expose certain parts of the layer 24 and of the mesas 13 and 15, while covering the part of the film 24 which covers the region reserved for the doors.
- Layer 36 after development, is shown in Figure 3E.
- the exposed parts 38 of the film 24 are then removed by pickling. For example, if the film has a thickness of approximately 500 A, its removal can be carried out by chemical etching, preferably carried out using H 3 P0 4 at 180 ° C for approximately five minutes. Another stripping step makes it possible to remove, if necessary, the layer 22 located in the regions 38.
- the remaining layer 36 is then removed using a solvent such as acetone and the device is ready to undergo a oxidation.
- Mesas 13 and 15 are thermally oxidized, preferably in steam at approximately 1000 ° C for several minutes, so as to create an oxide layer with a thickness 0 of approximately 1000 A. During this time interval, the oxide layers in regions 38 continue to thicken.
- the resulting structure is shown in Figure 3F.
- the remaining part of the Si 3 N 4 film 24 which covers the region C reserved for the doors is removed by chemical pickling; this will preferably be carried out, as previously, using a stripper such as H 3 P0 4 at 180 ° C for five about minutes.
- the layer 22 of Si0 2 can be removed by pickling using a solution of hydrofluoric acid buffered with NH 4 F. A part 40 of epitaxial layer 12 is thus exposed on which a metal can be deposited so as to constitute a door.
- this metal is chosen from metals capable of forming a Schottky barrier with Si, for example Pt, Ti or W, a MESFET device with Schottky barrier is obtained.
- Metal silicides such as PdSi 2 or PtSi, can also be used.
- junction gate region by introducing a p-type dopant into the exposed part 40 of the layer 12. This introduction can be carried out either by thermal diffusion or by ion implantation, the latter technique being preferred because it limits the lateral diffusion of the dopant.
- the removed door electrode should. form ohmic contact with the door region.
- Aluminum is a suitable metal that can be used to make up the door.
- the doors can be defined using conventional lithographic techniques in which the photo-sensitive resin is first applied, after which the regions thereof which are above the door region are exposed and developed. Again, this has the effect of exposing the part 40 of the substrate on which the metal is deposited.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/974,592 US4222164A (en) | 1978-12-29 | 1978-12-29 | Method of fabrication of self-aligned metal-semiconductor field effect transistors |
US974592 | 1978-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0013342A1 true EP0013342A1 (de) | 1980-07-23 |
EP0013342B1 EP0013342B1 (de) | 1982-02-24 |
Family
ID=25522230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP79104878A Expired EP0013342B1 (de) | 1978-12-29 | 1979-12-04 | Verfahren zur Herstellung selbstausrichtender Feldeffekt-Transistoren des Metallhalbleitertyps |
Country Status (4)
Country | Link |
---|---|
US (1) | US4222164A (de) |
EP (1) | EP0013342B1 (de) |
JP (1) | JPS5924551B2 (de) |
DE (1) | DE2962217D1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0024222A1 (de) * | 1979-07-27 | 1981-02-25 | Thomson-Csf | Verfahren zur Herstellung eines Feldeffekttransistors mit selbstjustiertem SCHOTTKY-Gate |
FR2583220A1 (fr) * | 1985-06-11 | 1986-12-12 | Thomson Csf | Procede de realisation d'au moins deux metallisations d'un composant semi-conducteur, recouvertes d'une couche de dielectrique et composant obtenu par ce dielectrique |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4546366A (en) * | 1978-04-24 | 1985-10-08 | Buchanan Bobby L | Polysilicon/silicon junction field effect transistors and integrated circuits (POSFET) |
FR2461358A1 (fr) * | 1979-07-06 | 1981-01-30 | Thomson Csf | Procede de realisation d'un transistor a effet de champ a grille auto-alignee, et transistor obtenu par ce procede |
US4377899A (en) * | 1979-11-19 | 1983-03-29 | Sumitomo Electric Industries, Ltd. | Method of manufacturing Schottky field-effect transistors utilizing shadow masking |
US4393578A (en) * | 1980-01-02 | 1983-07-19 | General Electric Company | Method of making silicon-on-sapphire FET |
US4387386A (en) * | 1980-06-09 | 1983-06-07 | The United States Of America As Represented By The Secretary Of The Army | Microwave controlled field effect switching device |
US4359816A (en) * | 1980-07-08 | 1982-11-23 | International Business Machines Corporation | Self-aligned metal process for field effect transistor integrated circuits |
EP0057605B1 (de) * | 1981-01-29 | 1986-10-08 | Sumitomo Electric Industries Limited | Schottky-Gate-Feldeffekttransistor und Verfahren zu seiner Herstellung |
US4389768A (en) * | 1981-04-17 | 1983-06-28 | International Business Machines Corporation | Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors |
US4601095A (en) * | 1981-10-27 | 1986-07-22 | Sumitomo Electric Industries, Ltd. | Process for fabricating a Schottky-barrier gate field effect transistor |
US4587541A (en) * | 1983-07-28 | 1986-05-06 | Cornell Research Foundation, Inc. | Monolithic coplanar waveguide travelling wave transistor amplifier |
US4670090A (en) * | 1986-01-23 | 1987-06-02 | Rockwell International Corporation | Method for producing a field effect transistor |
US4803173A (en) * | 1987-06-29 | 1989-02-07 | North American Philips Corporation, Signetics Division | Method of fabrication of semiconductor device having a planar configuration |
US4818712A (en) * | 1987-10-13 | 1989-04-04 | Northrop Corporation | Aluminum liftoff masking process and product |
US4945067A (en) * | 1988-09-16 | 1990-07-31 | Xerox Corporation | Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication |
US5143857A (en) * | 1988-11-07 | 1992-09-01 | Triquint Semiconductor, Inc. | Method of fabricating an electronic device with reduced susceptiblity to backgating effects |
US7310287B2 (en) | 2003-05-30 | 2007-12-18 | Fairfield Industries Incorporated | Method and apparatus for seismic data acquisition |
US7561493B2 (en) | 2003-05-30 | 2009-07-14 | Fairfield Industries, Inc. | Method and apparatus for land based seismic data acquisition |
JP2007294618A (ja) * | 2006-04-24 | 2007-11-08 | Elpida Memory Inc | 半導体装置の製造方法及び半導体装置 |
US8611191B2 (en) | 2008-05-22 | 2013-12-17 | Fairfield Industries, Inc. | Land based unit for seismic data acquisition |
CN105870190B (zh) * | 2016-04-22 | 2019-04-12 | 西安电子科技大学 | 一种具有双高栅的4H-SiC金属半导体场效应晶体管的制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3855690A (en) * | 1972-12-26 | 1974-12-24 | Westinghouse Electric Corp | Application of facet-growth to self-aligned schottky barrier gate field effect transistors |
GB1499090A (en) * | 1975-11-26 | 1978-01-25 | Ibm | Field effect transistor structure |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH461646A (de) * | 1967-04-18 | 1968-08-31 | Ibm | Feld-Effekt-Transistor und Verfahren zu seiner Herstellung |
GB1265017A (de) * | 1968-08-19 | 1972-03-01 | ||
US3574010A (en) * | 1968-12-30 | 1971-04-06 | Texas Instruments Inc | Fabrication of metal insulator semiconductor field effect transistors |
US3756924A (en) * | 1971-04-01 | 1973-09-04 | Texas Instruments Inc | Method of fabricating a semiconductor device |
US3943622A (en) * | 1972-12-26 | 1976-03-16 | Westinghouse Electric Corporation | Application of facet-growth to self-aligned Shottky barrier gate field effect transistors |
US3906541A (en) * | 1974-03-29 | 1975-09-16 | Gen Electric | Field effect transistor devices and methods of making same |
US3909925A (en) * | 1974-05-06 | 1975-10-07 | Telex Computer Products | N-Channel charge coupled device fabrication process |
US4029522A (en) * | 1976-06-30 | 1977-06-14 | International Business Machines Corporation | Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors |
-
1978
- 1978-12-29 US US05/974,592 patent/US4222164A/en not_active Expired - Lifetime
-
1979
- 1979-10-19 JP JP54134314A patent/JPS5924551B2/ja not_active Expired
- 1979-12-04 EP EP79104878A patent/EP0013342B1/de not_active Expired
- 1979-12-04 DE DE7979104878T patent/DE2962217D1/de not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3855690A (en) * | 1972-12-26 | 1974-12-24 | Westinghouse Electric Corp | Application of facet-growth to self-aligned schottky barrier gate field effect transistors |
GB1499090A (en) * | 1975-11-26 | 1978-01-25 | Ibm | Field effect transistor structure |
Non-Patent Citations (1)
Title |
---|
IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol. SC-12, No. 4 Aout 1977 New York H. HOSACK et al. "Submicron patterning of surfaces". * Pages 363 a 367 * * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0024222A1 (de) * | 1979-07-27 | 1981-02-25 | Thomson-Csf | Verfahren zur Herstellung eines Feldeffekttransistors mit selbstjustiertem SCHOTTKY-Gate |
FR2583220A1 (fr) * | 1985-06-11 | 1986-12-12 | Thomson Csf | Procede de realisation d'au moins deux metallisations d'un composant semi-conducteur, recouvertes d'une couche de dielectrique et composant obtenu par ce dielectrique |
EP0209419A1 (de) * | 1985-06-11 | 1987-01-21 | Thomson-Csf | Verfahren zur Herstellung von mindestens zwei mit einer dielektrischen Schicht versehenen Metallisierungen auf einem Halbleiterkörper und Halbleiteranordnung mit dieser Schicht |
Also Published As
Publication number | Publication date |
---|---|
EP0013342B1 (de) | 1982-02-24 |
US4222164A (en) | 1980-09-16 |
DE2962217D1 (en) | 1982-03-25 |
JPS5591881A (en) | 1980-07-11 |
JPS5924551B2 (ja) | 1984-06-09 |
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