EP0000975B1 - Structure JFET-bipolaire composite - Google Patents

Structure JFET-bipolaire composite Download PDF

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Publication number
EP0000975B1
EP0000975B1 EP78200164A EP78200164A EP0000975B1 EP 0000975 B1 EP0000975 B1 EP 0000975B1 EP 78200164 A EP78200164 A EP 78200164A EP 78200164 A EP78200164 A EP 78200164A EP 0000975 B1 EP0000975 B1 EP 0000975B1
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EP
European Patent Office
Prior art keywords
region
body portion
source
drain
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78200164A
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German (de)
English (en)
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EP0000975A1 (fr
Inventor
Steve Wilcox Mylroie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication of EP0000975A1 publication Critical patent/EP0000975A1/fr
Application granted granted Critical
Publication of EP0000975B1 publication Critical patent/EP0000975B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors

Definitions

  • This invention carries the above developments one step further by merging a junction field effect transistor with a bipolar transistor in a single composite device for use in analog circuitry, within a single isolation region by the use of planar processing techniques.
  • a composite semiconductor device of the type mentioned in the preamble is characterized in that the said means constituting a gate region are separated from the source and drain regions and from the emitter region, are located closer to the source region than the drain region, and are connected separately with contact means.
  • the composite semiconductor device includes a lower semiconductor body portion or substrate 10 of P type silicon upon which an upper semiconductor body portion or epitaxial layer 12 of N type conductivity may be grown.
  • the epitaxial layer 12 has a planar top of major surface 14.
  • the isolation region 16 may be a P+ region.
  • the isolation region may be of insulating material such as silicon dioxide.
  • a buried layer 18 of the same type conductivity as and of higher conductivity than the epitaxial layer 12 forms a junction with the substrate 10 and extends laterally a substantial distance within the confines of the isolation region 16, but not in contact with the latter.
  • the buried layer 18 is accordingly labeled N+ to indicate its high conductivity.
  • the buried layer 18 may be formed by diffusing into the substrate 10, prior to growth of the epitaxial layer 12, an appropriate concentration of N type impurity, such as arsenic or antimony, according to well-known practice.
  • An annular source region 20 of P type conductivity extends from the major surface 14 into the epitaxial layer 12 a substantial portion of the depth of the layer 12 but spaced from the buried layer 18.
  • the annular source region 20 may be formed by diffusing a P type impurity of appropriate concentration, such as boron, into the epitaxial layer 12, forming a PN junction therewith.
  • a drain region 22 of P type conductivity is located centrally within the portion of the epitaxial layer 12 circumscribed by the annular source region 20.
  • the drain region 22 extends from the major surface 14 into the epitaxial layer about the same depth as the annular source region 20.
  • the drain region 22 may be formed by diffusion at the same time as the formation of the annular source region 20.
  • the drain region 22 also constitutes the base zone of a bipolar transistor, the collector zone of which is constituted by the epitaxial layer 12 which forms a PN junction with the region and zone 22.
  • An emitter zone 24 of N type conductivity is formed within the drain region 22, forming a PN junction therewith, and extends to the major surface 14.
  • a collector contact zone 26 of N type conductivity is located within a portion of the epitaxial layer 12 lying between the annular source region 20 and the isolation region 16. The collector contact zone 26 thus lies outside the region of the epitaxial layer 12 circumscribed by the annular source region 20.
  • Both N type zones 24 and 26 are of high conductivity, and thus labeled N+, and may be formed by simultaneous diffusion.
  • annular channel region 28 of P type conductivity extends between the annular source region 20 and drain region 22.
  • the annular channel region 28 is labeled P- as having a lower conductivity than the source and drain regions 20, 22 which are labeled P.
  • the annular channel region 28 overlaps both the source region 20 and the drain region 22 but is spaced from the emitter zone 24.
  • the annular channel region 28 extends from the major surface 14 into the epitaxial layer 12 a shallow distance much smaller than the depth of the source and drain regions 20, 22 and forms a PN junction with the epitaxial layer 12.
  • Both the annular channel region 28 and the top gate region 30 are surface regions extending to the major surface 12 and are preferably formed by ion implantation.
  • the desirable nature of ion implantation is such that the order in which the regions 28 and 30 may be implanted is optional.
  • the channel region 28 may be implanted before or after the top gate region 30 is implanted.
  • the concentration of dopant for the N type top gate may be tailored to the current versus voltage characteristics desired of the junction field effect transistor.
  • a surface layer of metallization is applied to form a collector contact 32 to the collector contact zone 26, an annular source contact 34 to the annular source region 20, an annular top gate contact 36 to the annular top gate 30 and an emitter contact 38 to the emitter region 24.
  • the contacts 32, 34, 36 and 38 are formed through openings in a surface oxide insulating layer 40.
  • a metal region forming a Schottky barrier junction with the channel region 28 could be used in place of the annular top gate region 30 of N type conductivity.
  • the metal region would serve to provide both the Schottky barrier junction as well as the metal contact for the barrier junction.
  • the surface concentration of the channel region 28 should be less than 10 15 atoms per cubic centimeter. A metal such as platinum has been found to make reliable Schottky barrier junction with silicon.
  • the collector contact 32 if made of aluminium, can be applied directly to the body portion 12 rather than to a high conductivity zone such as collector contact zone 26. In such case a higher conductivity P+ zone is unnecessary.
  • FIG. 2 An equivalent circuit for the composite integrated structure of Figure 1 is shown in Figure 2.
  • the gate contact 36 is shown as the input terminal of the JFET which also includes the source 20 and source contact 34, drain 22, and channel 28.
  • the top gate region 30 is shown in Figure 2 as the negative of N side of a diode or rectifying PN junction which the top gate region 30 forms with the channel 28.
  • the positive of P side of the diode or rectifying junction is shown directly connected to the channel 28.
  • the diode or junction is shown with a polarity that is conventional for a P charnel JFET.
  • the source contact 34 is shown as a terminal connected to a positive voltage supply +V ss .
  • the other side of the channel 28 is shown coupled through a second diode or Pn rectifying junction to the collector 12 of the bipolar transistor which also includes the emitter 24 and base 22.
  • the collector contact 32 is shown as an output terminal connected to ground and the emitter contact 38 is shown as an output terminal connected through a load resistor 42 to the negative voltage supply -V EE'
  • the body portion or collector 12 of the bipolar transistor also serves as the bottom gate of the JFET, which bottom gate is shown as the negative or N side 12 of the PN junction it forms with the bottom side of the channel 28.
  • the base of the bipolar transistor and the drain of the JFET are merged in the same region 22 as indicated previously, although the circuit diagram of Figure 2 shows them as separate elements 22 conductively connected together to indicate their individual functions in their respective devices.
  • the signal input to the gate terminal 36 is negative.
  • the negative signal will reduce the reverse bias on the gate to channel junction so as to narrow the depletion region in the channel 28, increase the conductivity of the channel 28 and cause a larger current to flow in the JFET from the source 20 to the drain 22.
  • the drain 22 is merged with the base 22 of the bipolar transistor, the drain current is forced to flow as base current drive to the bipolar transistor, which increases the current flowing in the emitter circuit.
  • This increased current flow in the emitter circuit causes a voltage drop across the load resistor 40 and drives the output voltage at the terminal 38 less negative, or in a positive direction.
  • a negative input signal will produce a positive output signal, and an inversion has occurred.
  • a positive input signal will increase the reverse bias on the gate to channel junction so as to widen the depletion region in the channel 28 and reduce the source to drain current in the JFET.
  • the base drive to the bipolar transistor is accordingly reduced and the emitter current is reduced, thereby causing the voltage at the output terminal 38 to decrease towards the level of the supply voltage -V EE . Since this is a negative voltage, it is apparent that an inversion of the positive input signal has occurred.
  • the emitter terminal 38 is the effective drain terminal of the JFET.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Claims (7)

1. Dispositif semiconducteur composé comportant un corps semiconducteur présentant une partie de premier type de conductivité contigue à une surface principale, et muni d'une structure fusionnée de transistor à effet de champ à jonction et de transistor bipolaire comportant:
a. des regions de source et de drain sépe- rées de second type de conductivité qui sont formées dans ladite partie de corps semiconducteur et qui, dans cette partie de corps, s'étendent à partir de ladite surface principale sur une profondeur donnée.
b. une région du canal de second type de conductivité qui s'étend sur toute la distance séparant lesdites régions de source et de drain et qui, dans ladite partie de corps, s'étend à partir de ladite surface sur une distance inférieure à ladite profondeur donnée.
c. une zone dudit premier type de conductivité qui est située dans la région de drain et forme une zone d'émetteur du transistor bipolaire, alors que la région de drain et ladite partie de corps de premier type de conductivité forment respectivement la région de base et la région de collecteur du transistor bipolaire.
d. des moyens qui forment une jonction redresseuse avec une partie superficielle de la région de canal et constitue une région de grille du transistor à effet de champ à jonction;
e. des moyens de contact raccordés à ladite partie de corps, à ladite zone d'émetteur et à ladite région de source;

caractérisé en ce que lesdits moyens constituant une région de grille sont séparés des régions de source et de drain ainsi que de la région d'émetteur, en ce qu'ils sont plus proches de la région de source que de la région de drain et en ce qu'ils sont raccordés séparément à des moyens de contact.
2. Dispositif semiconducteur selon la revendication 1, caractérisé en ce que la région de source est formée par une région annulaire de second type de conductivité, et en ce que la région de drain est formé par une seconde région de second type de conductivité située dans la région de ladite partie de corps circonscrite par ladite première région annulaire.
3. Dispositif semiconducteur selon l'une quelconque des revendications 1 à 2, caractérisé en ce'que la région de collecteur du transistor bipolaire comporte une région enterrée, située dans la partie inférieure de ladite partie de corps, et séparée desdites régions de source et de drain, sa conductivité étant supérieure par rapport à celles-ci, région enterrée qui s'étend latéralement sur une distance couvrant au moins la distance existant entre la région de drain et les moyens de contact de ladite partie de corps, moyens de contact qui comportent d'une part une zone superficielle située dans ladite partie de corps et ayant une conductivité supérieure par rapport à celle-ci, et d'autre part une partie métallique formant un contact ohmique avec ladite zone superficielle.
4. Dispositif semiconducteur selon l'une quelconque des revendications 1 à 3, caractérisé en ce que la partie de corps semiconducteur est de type de conductivité N.
5. Dispositif semiconducteur selon la revendication 4, caractérisé en ce que le transistor à effet de champ à jonction et le transistor bipolaire sont prévus dans une partie de corps commune, en forme d'une îlot, du corps semiconducteur, alors que ledit corps comporte des moyens d'isolation entourant ladite partie de corps.
6. Dispositif semiconducteur selon la revendication 4, caractérisé en ce que les régions de source et de drain et la zone d'émetteur sont réalisées par diffusion et en ce que ladite région de canal et ladite région de grille sont réalisées par implantation ionique.
7. Dispositif semiconducteur selon l'une quelconque des revendications 1 à 6, caractérisé en ce que lesdits moyens constituant une région de grille du transistor à effet de champ à jonction comporte une région métallique formant une jonction d'arrêt Schottky avec ladite région de canal.
EP78200164A 1977-08-30 1978-08-29 Structure JFET-bipolaire composite Expired EP0000975B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/828,999 US4143392A (en) 1977-08-30 1977-08-30 Composite jfet-bipolar structure
US828999 1977-08-30

Publications (2)

Publication Number Publication Date
EP0000975A1 EP0000975A1 (fr) 1979-03-07
EP0000975B1 true EP0000975B1 (fr) 1982-01-06

Family

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EP78200164A Expired EP0000975B1 (fr) 1977-08-30 1978-08-29 Structure JFET-bipolaire composite

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US (1) US4143392A (fr)
EP (1) EP0000975B1 (fr)
JP (1) JPS5452994A (fr)
DE (1) DE2861510D1 (fr)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314267A (en) * 1978-06-13 1982-02-02 Ibm Corporation Dense high performance JFET compatible with NPN transistor formation and merged BIFET
US4322738A (en) * 1980-01-21 1982-03-30 Texas Instruments Incorporated N-Channel JFET device compatible with existing bipolar integrated circuit processing techniques
US4395812A (en) * 1980-02-04 1983-08-02 Ibm Corporation Forming an integrated circuit
US4362574A (en) * 1980-07-09 1982-12-07 Raytheon Company Integrated circuit and manufacturing method
EP0063139A4 (fr) * 1980-10-28 1984-02-07 Hughes Aircraft Co Procede de fabrication d'un transistor bipolaire iii-v par implantation selective d'ions et dispositif obtenu selon ce procede.
US4916505A (en) * 1981-02-03 1990-04-10 Research Corporation Of The University Of Hawaii Composite unipolar-bipolar semiconductor devices
JPH0750560B2 (ja) * 1981-05-09 1995-05-31 ヤマハ株式会社 ディジタル集積回路装置
US4441116A (en) * 1981-07-13 1984-04-03 National Semiconductor Corporation Controlling secondary breakdown in bipolar power transistors
US4456918A (en) * 1981-10-06 1984-06-26 Harris Corporation Isolated gate JFET structure
US4495694A (en) * 1981-10-06 1985-01-29 Harris Corporation Method of fabricating an isolated gate JFET
US4485392A (en) * 1981-12-28 1984-11-27 North American Philips Corporation Lateral junction field effect transistor device
US4729008A (en) * 1982-12-08 1988-03-01 Harris Corporation High voltage IC bipolar transistors operable to BVCBO and method of fabrication
JPS61158177A (ja) * 1984-12-28 1986-07-17 Toshiba Corp 半導体装置
JPS62119972A (ja) * 1985-11-19 1987-06-01 Fujitsu Ltd 接合型トランジスタ
US4808547A (en) * 1986-07-07 1989-02-28 Harris Corporation Method of fabrication of high voltage IC bopolar transistors operable to BVCBO
US4876579A (en) * 1989-01-26 1989-10-24 Harris Corporation Low top gate resistance JFET structure
US5191401A (en) * 1989-03-10 1993-03-02 Kabushiki Kaisha Toshiba MOS transistor with high breakdown voltage
EP0435541A3 (en) * 1989-12-26 1991-07-31 Motorola Inc. Semiconductor device having internal current limit overvoltage protection
DE10206133C1 (de) * 2002-02-14 2003-09-25 Infineon Technologies Ag Vertikaler Bipolartransistor mit innewohnendem Junction-Feldeffekttransistor (J-FET)
US7518194B2 (en) * 2006-05-20 2009-04-14 Sergey Antonov Current amplifying integrated circuit
TWI408808B (zh) * 2007-10-24 2013-09-11 Chun Chu Yang 同軸電晶體結構
US8481372B2 (en) * 2008-12-11 2013-07-09 Micron Technology, Inc. JFET device structures and methods for fabricating the same
KR101807334B1 (ko) 2013-04-12 2018-01-11 매그나칩 반도체 유한회사 멀티 소오스 jfet 디바이스
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
KR101975630B1 (ko) * 2015-04-03 2019-08-29 매그나칩 반도체 유한회사 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법

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US4048649A (en) * 1976-02-06 1977-09-13 Transitron Electronic Corporation Superintegrated v-groove isolated bipolar and vmos transistors
US4066917A (en) * 1976-05-03 1978-01-03 National Semiconductor Corporation Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic

Also Published As

Publication number Publication date
EP0000975A1 (fr) 1979-03-07
DE2861510D1 (en) 1982-02-25
US4143392A (en) 1979-03-06
JPS6153861B2 (fr) 1986-11-19
JPS5452994A (en) 1979-04-25

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