EA201800204A1 - DEVICE FOR EQUIPMENT BY EIGHT MODULE - Google Patents

DEVICE FOR EQUIPMENT BY EIGHT MODULE

Info

Publication number
EA201800204A1
EA201800204A1 EA201800204A EA201800204A EA201800204A1 EA 201800204 A1 EA201800204 A1 EA 201800204A1 EA 201800204 A EA201800204 A EA 201800204A EA 201800204 A EA201800204 A EA 201800204A EA 201800204 A1 EA201800204 A1 EA 201800204A1
Authority
EA
Eurasian Patent Office
Prior art keywords
inputs
values
elements
mod
outputs
Prior art date
Application number
EA201800204A
Other languages
Russian (ru)
Other versions
EA033823B1 (en
Inventor
Валерий Павлович Супрун
Данила Андреевич Городецкий
Original Assignee
Белорусский Государственный Университет (Бгу)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Белорусский Государственный Университет (Бгу) filed Critical Белорусский Государственный Университет (Бгу)
Priority to EA201800204A priority Critical patent/EA033823B1/en
Publication of EA201800204A1 publication Critical patent/EA201800204A1/en
Publication of EA033823B1 publication Critical patent/EA033823B1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)

Abstract

Изобретение относится к области вычислительной техники и микроэлектроники и может быть использовано для построения средств аппаратурного контроля и цифровых устройств, работающих в системе остаточных классов. Вычислительное устройство предназначено для реализации операции умножения A∙B=R (mod 8). Устройство содержит семь элементов И, два элемента СЛОЖЕНИЕ ПО МОДУЛЮ ДВА, шесть входов и три выхода. Сложность устройства (по числу входов логических элементов) равна 22, а быстродействие, определяемое глубиной схемы, составляет 2τ, где τ - задержка на один логический элемент. Устройство для умножения по модулю восемь работает следующим образом. На входы устройства поступают значения двоичных переменных a, b, a, b, a, b, принимающие значения младших, средних и старших разрядов операндов A и B, где A=a+2a+4aи B=b+2b+4b. На выходах устройства реализуются логические функции R, R, R, принимающие значения младшего r, среднего rи старшего rразрядов результата выполнения операции A∙B=R (mod 8), где R=r+2r+4r.The invention relates to the field of computer engineering and microelectronics and can be used to build hardware control equipment and digital devices operating in a system of residual classes. The computing device is designed to implement the multiplication operation A ∙ B = R (mod 8). The device contains seven AND elements, two elements MODULE TWO, six inputs and three outputs. The complexity of the device (by the number of inputs of the logic elements) is 22, and the speed determined by the depth of the circuit is 2τ, where τ is the delay by one logic element. A device for multiplying modulo eight works as follows. The values of the binary variables a, b, a, b, a, b are received at the inputs of the device, taking the values of the lower, middle, and high bits of the operands A and B, where A = a + 2a + 4a and B = b + 2b + 4b. At the device outputs, logical functions R, R, R are implemented that take values of the lower r, middle r, and high r bits of the result of the operation A ∙ B = R (mod 8), where R = r + 2r + 4r.

EA201800204A 2018-02-06 2018-02-06 Modulo eigth multiplication device EA033823B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EA201800204A EA033823B1 (en) 2018-02-06 2018-02-06 Modulo eigth multiplication device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EA201800204A EA033823B1 (en) 2018-02-06 2018-02-06 Modulo eigth multiplication device

Publications (2)

Publication Number Publication Date
EA201800204A1 true EA201800204A1 (en) 2019-08-30
EA033823B1 EA033823B1 (en) 2019-11-29

Family

ID=67734893

Family Applications (1)

Application Number Title Priority Date Filing Date
EA201800204A EA033823B1 (en) 2018-02-06 2018-02-06 Modulo eigth multiplication device

Country Status (1)

Country Link
EA (1) EA033823B1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3417286B2 (en) * 1998-02-23 2003-06-16 株式会社デンソー Multiplier
RU2143722C1 (en) * 1999-03-16 1999-12-27 Балтийский государственный технический университет "Военмех" им.Д.Ф.Устинова Device for multiplication by modulo 7
RU2181904C1 (en) * 2000-12-06 2002-04-27 Балтийский государственный технический университет "Военмех" им. Д.Ф. Устинова Modulo five multiplier
US8433736B2 (en) * 2009-02-27 2013-04-30 George Mason Intellectual Properties, Inc. Scalable Montgomery multiplication architecture
RU2589361C1 (en) * 2015-03-10 2016-07-10 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Северо-Кавказский федеральный университет" Modulo multiplier

Also Published As

Publication number Publication date
EA033823B1 (en) 2019-11-29

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Legal Events

Date Code Title Description
MM4A Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s)

Designated state(s): AM AZ KZ KG TJ TM RU