RU2681702C1 - Arithmetic-logic apparatus and a method for converting data using such device - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to computer engineering. Device includes three data inputs, operation code input, data output, cyclic shift unit for 8, 16, 24 bits, inversion unit, mask masking unit '0×FF', ALU 1, performing operations of adding operands, subtracting operands, logical operations AND, OR, XOR, shifting by 1–7 bits of the first operand, transmission of one of the operands to the output, ALU 2 No. 1 and ALU 2 No. 2, performing operations of addition of operands, logical operations AND, OR, XOR, transfer of the first operand to output.

EFFECT: technical result consists in increase in the device performance in solving discrete mathematics problems.

2 cl, 1 dwg

Description

Technical field

The present device relates to digital computing devices, namely, elements of computers with a memorized program.

State of the art

The closest device of the same purpose to the claimed invention in terms of features is the arithmetic logic device of the high-performance cryptographic processor Cryptoraptor (Gokhan Sayilar, Derek Chiou. Cryptoraptor: High Throughput Reconfigurable Cryptographic Processor ISBN: 978-1-4799-6277- 8), which consists of the arithmetic unit AU, the logical operation unit LOU, the rotation and shift unit SRU, the polling unit of the TLU tables, and the mixing unit PEU. Moreover, the AU arithmetic unit has four input ports for transmitting data four bytes wide, one output port for transmitting data one byte wide, an Adder adder, a Subtracter subtracter, four blocks for performing the XOR operation, three multiplexers, two modules for adding and subtracting modulo 8 and 2 modules for addition and subtraction modulo 16. The LOU logical operation unit has 6 input ports for data transfer, one output port for data transfer and eight CLB logical conversion modules.

The arithmetic-logic device of the Cryptoraptor cryptographic processor has a tree structure and allows you to implement most of the discrete mathematics algorithms, and it is worth noting that the AU arithmetic unit allows one addition and one subtraction operation modulo 8, 16 or 32 of two operands per cycle. The inability to sum more than two operands per cycle in an arithmetic logic device slows down the operation of some cryptographic algorithms, for example, MD5. Also, due to the wide coverage of possible operations, the arithmetic-logical device of the cryptographic processor Cryptoraptor contains a large number of different functional units that require a large amount of hardware resources for their implementation.

The reason that impedes the achievement of the technical result is the structure of the AU arithmetic unit, which allows the addition of only two operands, as well as the large number of functional units of this arithmetic-logical device and their architectural complexity, in one clock cycle.

Object of the invention

The problem to which the proposed technical solution is directed is to create a high-performance arithmetic-logic device for solving discrete mathematics problems, requiring a small amount of hardware resources for its implementation.

The technical result of the invention is to increase the productivity of the device in solving discrete mathematics problems and reduce the amount of hardware resources required for its implementation.

SUMMARY OF THE INVENTION

The problem is solved, and the claimed technical result is achieved due to the fact that the arithmetic logic device (ALU) for solving discrete mathematics problems contains:

- three external data entry groups,

- an external input code group of operations and an external data output group,

- a cyclic shift unit, the data input of which is connected to the data input No. 1, the command input of the cyclic shift unit is connected to the input of the operation code, and the data output with the second input of the inversion unit, containing the MX 1 multiplexer, the data inputs of which are connected to the data input No. 1, moreover, the operand from the data input No. 1 is cyclically shifted 8 bits to the right to the second input of the multiplexer, the operand from the data input No. 1 is cyclically shifted 16 bits to the third input, and the operand from the data input No. 1 cyclically shifted by 24 to the fourth input bat right Wherein the first, control, input 1 of the multiplexer MX is coupled to the input of commands cyclic shift unit and the output from the cyclic shift unit output,

- an inversion unit, the first input of which is connected to the input of the operation code, and the output with the second data input of the mask unit, containing an addition module modulo 2, the first input of which is connected to the first input of the inversion unit, the second input with the second input of the inversion unit, and the output is with the output of the inversion block,

- a mask unit, the first input of which is connected to the input of the operation code, and the output with input A ALU 1 and input A ALU 2 No. 2, consisting of a logical AND element, the first input of which is connected to the first input of the mask unit, the second input with the second input mask block, and the output is with the output of the mask block,

- ALU 1, whose input B is connected to data input No. 2, input K to the operation code input, and output to input A ALU 2 No. 1, which contains an addition module modulo two, the first input of which is connected to input K, the second input to input B, and the output with the second input of the adder ADD, the adder ADD, the first input of which is connected to input A, and the output - with the first input of the multiplexer MX 2, the module is two modulo addition, the first input of which is connected to input A, the second input is connected to input B, and the output with the second input of the MX 2 multiplexer, a logical OR module, the first input of which connected to input A, the second input is connected to input B, and the output is to the third input of the MX 2 multiplexer, the logical module is AND, the first input of which is connected to input A, the second input is connected to input B, and the output to the fourth input of multiplexer MX 2, MX 2 multiplexer, fifth, sixth, seventh, eighth, ninth, tenth, eleventh input port of which is connected to input A, and the operand from input A is supplied with an operand from input A cyclically shifted to the right by 1, 2, 3, 4, 5, 6, 7 bits respectively, the twelfth input is connected to input A, the thirteenth input to input ohm B, the control input with input K, and the output with the output of ALU 1,

- ALU 2 No. 1, input B of which is connected to the output of ALU 2 No. 2, input K with the input of the operation code, and output with data output, which contains the adder ADD, the first input of which is connected to input A, the second input with input B, and the output with the first input of the MX 3 multiplexer, an addition module modulo two, the first input of which is connected to input A, the second input with input B, and the output with the second input of the MX 3 multiplexer, logical OR module, the first input of which is connected to input A, the second input with input B, and output with the third input of the MX 3 multiplexer, logical AND module, first input One of which is connected to input A, the second input with input B, and the output with the fourth input of the MX 3 multiplexer, MX 3 multiplexer, the fifth input of which is connected to input A, the control input with input K, and the output with ALU 2 output No. 2,

- ALU 2 No. 2, the internal structure of which coincides with the internal structure of ALU 2 No. 1, and the input B of which is connected to the data input No. 3 and the input of which is connected to the input of the operation code, the internal structure of which coincides with the structure of ALU 2 No. 1.

The problem is solved, and the claimed technical result is also achieved due to the fact that the processing method using the described arithmetic-logic device for solving discrete mathematics includes the following steps, in which:

- operands are fed to the data inputs of the described device, and the required command is fed to the input of the command field,

- the corresponding bits of the command are fed to the multiplexers and addition elements modulo two in the blocks of the described device,

- blocks of the described arithmetic-logical device perform the required set of arithmetic-logical operations on operands, in accordance with the code of the command.

Also, the claimed method can be characterized in that the set of executed commands is associated with a set of arithmetic-logical operations as follows:

- if the two least significant bits of the required instruction are equal to '00', '01', '10', '11', the cyclic shift unit will perform the operation of cyclic right shift of the operand from data input No. 1 to 0, 8, 16, 24 bits, respectively;

- if the third bit of the required instruction is '1', the inversion unit will perform the operation of logical inversion of the operand from the output of the rotation unit, otherwise, the operand will not change;

- if the bits of the desired command from the fourth to thirty-fifth inclusive take values from '0 × 00000000' to '0 × FFFFFFF', the mask block will perform the operation of masking the operand with the value in the corresponding bits of the command, if the command bit is '0', then the corresponding the operand bit at the output of the mask block will be '0', and if the command bit is '1', then the operand bit will be equal to the value of the corresponding operand bit at the input of the mask block;

- if the bits of the required command from the thirty-sixth to the thirty-ninth inclusive take values from '0000' to '1110', then accordingly ALU 1 will perform the operations - transfer of operand A, transfer of operand B, logical shift by 1-7 bits of operand A, operation addition of operands modulo 2, logical OR operation on operands, logical AND operation on operands, subtracting operand B from operand A, adding operands;

- if the bits of the required command from the fortieth to forty-second inclusive take a value from '000' to '101', respectively, the small ALU 2 No. 1 will perform operations - transfer operand A to the output, the operation of adding operands modulo two, a logical OR operation on operands , logical operation AND on operands, addition of operands.

The essence of the invention lies in the fact that the arithmetic logic device includes three data inputs, an operation code input, a data output, a 8.16, 24-bit cyclic shift block, an inversion block, a mask overlay block '0 × FF', ALU 1 performing operations of addition of operands, subtraction of operands, logical operations AND, OR, XOR, shift of 1-7 bits of the first operand, transfer of one of the operands to the output, ALU 2 No. 1 and ALU 2 No. 2, performing operations of addition of operands, logical operations AND, OR, XOR, passing the first operand to the output.

A method of converting data using such a device comprises the steps of submitting a command and data to the inputs of the device, transmitting the corresponding bits of the command to each of the blocks of the device, and performing the corresponding blocks on the operands by the blocks of the device.

Brief Description of the Drawings

The device is illustrated in FIG. 1, which shows a block diagram of an arithmetic logic device.

In FIG. 1 adopted the following notation:

- элемент логического И,

- an element of logical AND,

- модуль сложения по модулю 2,

- addition module modulo 2,

- модуль логического ИЛИ,

- logical OR module,

ADD - adder,

>> N is a cyclic shift of N bits to the right,

MX 1, 2, 3 - multiplexers,

The arithmetic logic device consists of a cyclic shift unit, consisting of an MX 1 multiplexer, an inversion unit, consisting of an addition module modulo two, a mask unit, consisting of a logical AND module, ALU 1, consisting of an addition module modulo 2, an adder ADD, an addition module modulo 2 operands, a logical OR module, a logical AND module and an MX 2 multiplexer, ALU 2 No. 1 and ALU 2 No. 2, consisting of an ADD adder, an addition module modulo two operands, a logical OR module, a logical AND module, and a multiplexer MX 3.

Detailed Description of the Invention

Arithmetic logic device operates as follows. The first, second and third operands are fed to the corresponding data inputs. At the same time, a command is given to the input of the operation code that defines operations on operands that must be performed by units of the arithmetic-logical device. Corresponding bits of the command are fed to the control inputs of the multiplexers and to the input of some modules of logical transformations.

If the two least significant bits of the instruction are equal to '00', '01', '10', '11', the cyclic shift unit will perform the operation of cyclic right shift of the operand from data input No. 1 to 0, 8, 16, 24 bits, respectively.

If the third bit of the instruction is '1', the inversion block will perform the operation of logical inversion of the operand from the output of the rotation block, otherwise, the operand will not change.

If the command bits from the fourth to thirty-fifth inclusive take values from '0 × 00000000' to '0 × FFFFFFF', the mask block will perform the operation of masking the operand with the value in the corresponding bits of the command, if the command bit is '0', then the corresponding operand bit at the output of the mask block will be equal to '0', and if the bit of the command is equal to '1', then the operand bit will be equal to the value of the corresponding bit of the operand at the input of the mask block.

If the instruction bits from the thirty-sixth to the thirty-ninth inclusive take values from '0000' to '1110', then accordingly ALU 1 will perform operations - transfer of operand A, transfer of operand B, logical shift by 1-7 bits of operand A, operation of addition of operands modulo 2, logical OR operation on operands, logical AND operation on operands, subtracting operand B from operand A, adding operands.

If the bits of the command from the fortieth to forty-second inclusive take a value from '000' to '101', respectively, the small ALU 2 No. 1 will perform operations - transfer operand A to the output, the operation of adding operands modulo two, a logical OR operation on the operands, logical And operation on operands, addition of operands.

Examples of carrying out the invention

The proposed arithmetic logic device for solving discrete mathematics problems can be implemented on the basis of the FPGA Xilinx XC7V585 computing device of 512 processor elements. The width of the data bus of the inputs and outputs of the device is 4 bytes, and the frequency of the clock signal of the arithmetic logic device is 250 MHz.

To estimate the amount of resources required for the implementation of the arithmetic-logical device on the VLSI, an assessment was carried out using library elements of 28 nm technological process in CAD Cadence RTL Compiler systems of 512 processor elements. One arithmetic-logic device in this device occupies about 1250 square meters. microns, which is more than 20 times less than the total area of the blocks AU, LOU, SRU arithmetic logic device in the considered prototype of about 28,000 square meters. μm (Table III).

One of the tasks of discrete mathematics is the MD5 cryptographic hash function calculation algorithm. A graphic diagram showing the steps involved in calculating one round of MD5 in a prototype is presented in Figure 7.17 of the dissertation (Gokhan Sayilar, Cryptoraptor: High Throughput Reconfigurable Cryptographic Processor for Symmetric Key Encryption and Cryptographic Hash Functions. PhD dissertation. The University of Texas. Austin. 2014) . It follows from section 7.3.2 of this dissertation that the implementation of one MD5 round on two processor elements requires 4 clock cycles, and the second processor element is used to sum the operands A, Mi, Ki and can reduce the number of clock cycles required for implementation by one. Thus, the execution of one round of MD5 on one arithmetic-logical device of the cryptographic processor Cryptoraptor (prototype) takes 5 clock cycles.

The implementation of the MD5 round in the proposed device takes 4 cycles, and the performance gain is due to the presence of an adder in the small arithmetic-logic unit No. 2, which allows the summation of three operands A, Mi and Ki in one cycle.

Thus, in the proposed arithmetic-logical device, in comparison with the prototype - the arithmetic-logical device of the Cryptoraptor cryptographic processor, when working at the same clock frequency, productivity is improved on discrete mathematics tasks in which it is possible to speed up the work by implementing the summation of three operands. The increase in performance in the proposed arithmetic-logical device is achieved due to the presence of the second adder module in the small arithmetic-logical unit No. 2.

The above information allows us to conclude that the proposed arithmetic-logical device and the conversion method solve the problem - the creation of a high-performance arithmetic-logical device for solving discrete mathematics tasks that require a small amount of hardware resources for its implementation, and corresponds to the claimed technical result - increased productivity devices for solving discrete mathematics problems and reducing the amount of hardware resources required for it implementation.

Claims (16)

1. Arithmetic-logical device for solving problems of discrete mathematics, containing: - three external data entry groups; - an external group of entry of the operation code and an external group of data output; - a cyclic shift unit, the data input of which is connected to the data input No. 1, the command input of the cyclic shift unit is connected to the input of the operation code, and the data output with the second input of the inversion unit, containing the MX 1 multiplexer, the data inputs of which are connected to the data input No. 1, moreover, the operand from data input No. 1 cyclically shifted 8 bits to the right is fed to the second input of the multiplexer, the operand from data input No. 1 cyclically shifted 16 bits to the right to the third input, and the operand from data input No. 1 to the fourth input, 24-bit cyclically shifted ABO, wherein the first, control, MX 1 multiplexer input connected to the input circular shift command unit and output - with a yield of cyclic shift unit; - an inversion unit, the first input of which is connected to the input of the operation code, and the output with the second data input of the mask unit, containing an addition module modulo 2, the first input of which is connected to the first input of the inversion unit, the second input - with the second input of the inversion unit, and the output - with the output of the inversion block; - a mask block, the first input of which is connected to the input of the operation code, and the output - with the input A ALU 1 and with the input A ALU 2 No. 2, consisting of a logical AND element, the first input of which is connected to the first input of the mask block, the second input - with the second input of the mask block, and the output with the output of the mask block; - ALU 1, whose input B is connected to data input No. 2, input K to the operation code input, and output to input A ALU 2 No. 1, which contains an addition module modulo two, the first input of which is connected to input K, the second input to input B, and the output with the second input of the adder ADD, the adder ADD, the first input of which is connected to input A, and the output - with the first input of the multiplexer MX 2, the module is two modulo addition, the first input of which is connected to input A, the second input is connected to input B, and the output with the second input of the MX 2 multiplexer, a logical OR module, the first input of which connected to input A, the second input is connected to input B, and the output is to the third input of the MX 2 multiplexer, the logical module is AND, the first input of which is connected to input A, the second input is connected to input B, and the output to the fourth input of multiplexer MX 2, MX 2 multiplexer, fifth, sixth, seventh, eighth, ninth, tenth, eleventh input port which is connected to input A, and the operand from input A is fed to the multiplexer inputs, cyclically shifted to the right by 1, 2, 3, 4, 5, 6 , 7 bits respectively, twelfth input connected to input A, thirteenth input with input ohm B, the control input to the input R, and output - with output of the ALU 1; - ALU 2 No. 1, input B of which is connected to the output of the second ALU 2 No. 2, input K with the input of the operation code, and output with data output, which contains the adder ADD, the first input of which is connected to input A, the second input with input B, and the output with the first input of the MX 3 multiplexer, the modulus of addition two, the first input of which is connected to input A, the second input with input B, and the output with the second input of the MX 3 multiplexer, logical OR module, the first input of which is connected to input A, the second input with input B, and the output with the third input of the MX 3 multiplexer, logical AND module, p the first input of which is connected to input A, the second input with input B, and the output with the fourth input of the MX 3 multiplexer, MX 3 multiplexer, the fifth input of which is connected to input A, the control input with input K, and the output with the output of ALU 2 No. 2; - ALU 2 No. 2, the internal structure of which coincides with the internal structure of ALU 2 No. 1, and the input B of which is connected to the data input No. 3 and the input of which is connected to the input of the operation code, the internal structure of which coincides with the structure of ALU 2 No. 1. 2. A processing method using an arithmetic logic device according to claim 1 for solving discrete mathematics problems, comprising the following steps, in which: - operands are fed to the device data inputs according to claim 1, and the required command is supplied to the input of the command field; - if the two least significant bits of the required instruction are equal to '00', '01', '10', '11', the cyclic shift unit will perform the operation of cyclic right shift of the operand from data input No. 1 to 0, 8, 16, 24 bits, respectively; - if the third bit of the required instruction is '1', the inversion unit will perform the operation of logical inversion of the operand from the output of the rotation unit, otherwise, the operand will not change; - if the bits of the required command from the fourth to thirty-fifth inclusive take values from '0x00000000' to '0xFFFFFFF', the mask block will perform the operation of masking the operand with the value in the corresponding bits of the command, if the command bit is '0', then the corresponding operand bit at the output the mask block will be equal to '0', and if the command bit is equal to '1', then the operand bit will be equal to the value of the corresponding operand bit at the input of the mask block; - if the bits of the required command from the thirty-sixth to the thirty-ninth inclusive take values from '0000' to '1110', then accordingly ALU 1 will perform the operations - transfer of operand A, transfer of operand B, logical shift by 1-7 bits of operand A, operation addition of operands modulo 2, logical OR operation on operands, logical AND operation on operands, subtracting operand B from operand A, adding operands; - if the bits of the required command from the fortieth to forty-second inclusive take a value from '000' to '101', respectively, the small ALU 2 No. 1 will perform operations - transfer operand A to the output, the operation of adding operands modulo two, a logical OR operation on operands , logical operation AND on operands, addition of operands.

Images