EA201800205A1 - DEVICE FOR MULTIPLE UNIT CODES - Google Patents
DEVICE FOR MULTIPLE UNIT CODESInfo
- Publication number
- EA201800205A1 EA201800205A1 EA201800205A EA201800205A EA201800205A1 EA 201800205 A1 EA201800205 A1 EA 201800205A1 EA 201800205 A EA201800205 A EA 201800205A EA 201800205 A EA201800205 A EA 201800205A EA 201800205 A1 EA201800205 A1 EA 201800205A1
- Authority
- EA
- Eurasian Patent Office
- Prior art keywords
- equal
- mod
- unitary
- inputs
- operand
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Logic Circuits (AREA)
Abstract
Изобретение относится к области вычислительной техники и микроэлектроники и может быть использовано для построения средств аппаратурного контроля и цифровых устройств, работающих в системе остаточных классов. Устройство для умножения унитарных кодов предназначено для реализации операции умножения A∙B=P (mod 4). Устройство содержит мажоритарный элемент с порогом два, два элемента ИСКЛЮЧАЮЩЕЕ ИЛИ с порогом три, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ, восемь входов и четыре выхода. Сложность устройства (по числу входов логических элементов) равна 22, а быстродействие, определяемое глубиной схемы, составляет τ, где τ - задержка на один логический элемент. Устройство для умножения унитарных кодов работает следующим образом. На входы устройства поступают разряды "равно нулю", "равно единице", "равно двум", "равно трем" унитарного двоичного кода первого операнда A=(a,a,a,a) и разряды "равно нулю", "равно единице", "равно двум", "равно трем" унитарного двоичного кода второго операнда B=(b,b,b,b), где a,a,a,a,b,b,b,b∈ {0,1}. При этом a=1 и b=1 тогда и только тогда, когда A=k (mod 4) и B=k (mod 4), где k=0, 1, 2, 3. На выходах устройства формируется унитарный двоичный код результата выполнения операции A∙B=P (mod 4), где P=(p,p,p,p) и p,p,p,p∈ {0,1}. Причем здесь p=1 тогда и только тогда, когда A∙B=k (mod 4), где k=0, 1, 2, 3.The invention relates to the field of computer engineering and microelectronics and can be used to build hardware control equipment and digital devices operating in a system of residual classes. A unit for multiplying unitary codes is intended to implement the multiplication operation A ∙ B = P (mod 4). The device contains a majority element with a threshold of two, two elements of EXCLUSIVE OR with a threshold of three, an element of EXCLUSIVE OR, eight inputs and four outputs. The complexity of the device (by the number of inputs of logic elements) is 22, and the speed determined by the depth of the circuit is τ, where τ is the delay by one logic element. A device for multiplying unitary codes works as follows. The inputs of the device receive the bits "equal to zero", "equal to one", "equal to two", "equal to three" of the unitary binary code of the first operand A = (a, a, a, a) and the bits "equal to zero", "equal to one "," equals two "," equals three "unitary binary code of the second operand B = (b, b, b, b), where a, a, a, a, b, b, b, b∈ {0,1} . Moreover, a = 1 and b = 1 if and only if A = k (mod 4) and B = k (mod 4), where k = 0, 1, 2, 3. A unitary binary result code is generated at the device outputs performing the operation A ∙ B = P (mod 4), where P = (p, p, p, p) and p, p, p, p∈ {0,1}. Moreover, here p = 1 if and only if A ∙ B = k (mod 4), where k = 0, 1, 2, 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EA201800205A EA033759B1 (en) | 2018-02-06 | 2018-02-06 | Unitary codes multiplying device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EA201800205A EA033759B1 (en) | 2018-02-06 | 2018-02-06 | Unitary codes multiplying device |
Publications (2)
Publication Number | Publication Date |
---|---|
EA201800205A1 true EA201800205A1 (en) | 2019-08-30 |
EA033759B1 EA033759B1 (en) | 2019-11-22 |
Family
ID=67734895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EA201800205A EA033759B1 (en) | 2018-02-06 | 2018-02-06 | Unitary codes multiplying device |
Country Status (1)
Country | Link |
---|---|
EA (1) | EA033759B1 (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987487A (en) * | 1996-03-11 | 1999-11-16 | Cirrus Logic, Inc. | Methods and apparatus for the processing of digital signals |
RU2143723C1 (en) * | 1998-07-29 | 1999-12-27 | Воронежский государственный университет | Device for modulo multiplication of numbers |
-
2018
- 2018-02-06 EA EA201800205A patent/EA033759B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EA033759B1 (en) | 2019-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE322715T1 (en) | HIGH SPEED CALCULATION IN AN ARITHMETIC AND LOGIC CIRCUIT | |
AR115577A1 (en) | EFFICIENT ESTIMATION OF WEIGHTED PROBABILITY FOR BINARY ARITHMETIC CODING | |
EA201800205A1 (en) | DEVICE FOR MULTIPLE UNIT CODES | |
US9898254B2 (en) | Data extraction method and apparatus | |
EA201800203A1 (en) | UNIT CODES COMPUTER | |
RU2626329C1 (en) | Comparator of binary numbers | |
EA201800204A1 (en) | DEVICE FOR EQUIPMENT BY EIGHT MODULE | |
EA201700003A1 (en) | SUMMATOR OF UNITARY CODES BY MODULE FOUR | |
EA201600051A1 (en) | COMPUTATIONAL DEVICE OF UNITARY CODES BY MODULE THREE | |
EA201700414A1 (en) | COMPUTATIONAL DEVICE BY MODULE FOUR | |
RU2544748C1 (en) | Adder accumulator | |
EA201700002A1 (en) | SUMMATOR BY MODULE FOUR | |
RU2562411C1 (en) | Device for calculation of modulus of complex number | |
EA201600047A1 (en) | COMPUTATIONAL DEVICE BY MODULE THREE | |
EA026000B1 (en) | Device to calculate sheffer symmetrical boolean functions of five variables | |
RU2665255C1 (en) | Binary code comparator device | |
RU2537046C2 (en) | Method and device for adding binary codes | |
RU2772311C1 (en) | Device for implementing the cubic operation and | |
RU187997U1 (en) | PROBABILITY OF FINDING AN ANALYTICAL PROBABILITY FOR A GROUP OF JOINT EVENTS IN A DIRECTED GRAPH | |
CN102214082B (en) | Zoom device for residue number system | |
Maeda et al. | Markov binary sequences generated by post-processing based on feedback shift registers | |
RU2633142C1 (en) | Device for calculating function of √x2+y2 | |
Li et al. | Transition Mappings between De Bruijn Sequences | |
RU2090924C1 (en) | Modulo-three computer | |
RU2551414C1 (en) | Pulse counter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s) |
Designated state(s): AM AZ KZ KG TJ TM RU |