EA201800205A1 - DEVICE FOR MULTIPLE UNIT CODES - Google Patents

DEVICE FOR MULTIPLE UNIT CODES

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Publication number
EA201800205A1
EA201800205A1 EA201800205A EA201800205A EA201800205A1 EA 201800205 A1 EA201800205 A1 EA 201800205A1 EA 201800205 A EA201800205 A EA 201800205A EA 201800205 A EA201800205 A EA 201800205A EA 201800205 A1 EA201800205 A1 EA 201800205A1
Authority
EA
Eurasian Patent Office
Prior art keywords
equal
mod
unitary
inputs
operand
Prior art date
Application number
EA201800205A
Other languages
Russian (ru)
Other versions
EA033759B1 (en
Inventor
Валерий Павлович Супрун
Original Assignee
Белорусский Государственный Университет (Бгу)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Белорусский Государственный Университет (Бгу) filed Critical Белорусский Государственный Университет (Бгу)
Priority to EA201800205A priority Critical patent/EA033759B1/en
Publication of EA201800205A1 publication Critical patent/EA201800205A1/en
Publication of EA033759B1 publication Critical patent/EA033759B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)

Abstract

Изобретение относится к области вычислительной техники и микроэлектроники и может быть использовано для построения средств аппаратурного контроля и цифровых устройств, работающих в системе остаточных классов. Устройство для умножения унитарных кодов предназначено для реализации операции умножения A∙B=P (mod 4). Устройство содержит мажоритарный элемент с порогом два, два элемента ИСКЛЮЧАЮЩЕЕ ИЛИ с порогом три, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ, восемь входов и четыре выхода. Сложность устройства (по числу входов логических элементов) равна 22, а быстродействие, определяемое глубиной схемы, составляет τ, где τ - задержка на один логический элемент. Устройство для умножения унитарных кодов работает следующим образом. На входы устройства поступают разряды "равно нулю", "равно единице", "равно двум", "равно трем" унитарного двоичного кода первого операнда A=(a,a,a,a) и разряды "равно нулю", "равно единице", "равно двум", "равно трем" унитарного двоичного кода второго операнда B=(b,b,b,b), где a,a,a,a,b,b,b,b∈ {0,1}. При этом a=1 и b=1 тогда и только тогда, когда A=k (mod 4) и B=k (mod 4), где k=0, 1, 2, 3. На выходах устройства формируется унитарный двоичный код результата выполнения операции A∙B=P (mod 4), где P=(p,p,p,p) и p,p,p,p∈ {0,1}. Причем здесь p=1 тогда и только тогда, когда A∙B=k (mod 4), где k=0, 1, 2, 3.The invention relates to the field of computer engineering and microelectronics and can be used to build hardware control equipment and digital devices operating in a system of residual classes. A unit for multiplying unitary codes is intended to implement the multiplication operation A ∙ B = P (mod 4). The device contains a majority element with a threshold of two, two elements of EXCLUSIVE OR with a threshold of three, an element of EXCLUSIVE OR, eight inputs and four outputs. The complexity of the device (by the number of inputs of logic elements) is 22, and the speed determined by the depth of the circuit is τ, where τ is the delay by one logic element. A device for multiplying unitary codes works as follows. The inputs of the device receive the bits "equal to zero", "equal to one", "equal to two", "equal to three" of the unitary binary code of the first operand A = (a, a, a, a) and the bits "equal to zero", "equal to one "," equals two "," equals three "unitary binary code of the second operand B = (b, b, b, b), where a, a, a, a, b, b, b, b∈ {0,1} . Moreover, a = 1 and b = 1 if and only if A = k (mod 4) and B = k (mod 4), where k = 0, 1, 2, 3. A unitary binary result code is generated at the device outputs performing the operation A ∙ B = P (mod 4), where P = (p, p, p, p) and p, p, p, p∈ {0,1}. Moreover, here p = 1 if and only if A ∙ B = k (mod 4), where k = 0, 1, 2, 3.

EA201800205A 2018-02-06 2018-02-06 Unitary codes multiplying device EA033759B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EA201800205A EA033759B1 (en) 2018-02-06 2018-02-06 Unitary codes multiplying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EA201800205A EA033759B1 (en) 2018-02-06 2018-02-06 Unitary codes multiplying device

Publications (2)

Publication Number Publication Date
EA201800205A1 true EA201800205A1 (en) 2019-08-30
EA033759B1 EA033759B1 (en) 2019-11-22

Family

ID=67734895

Family Applications (1)

Application Number Title Priority Date Filing Date
EA201800205A EA033759B1 (en) 2018-02-06 2018-02-06 Unitary codes multiplying device

Country Status (1)

Country Link
EA (1) EA033759B1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987487A (en) * 1996-03-11 1999-11-16 Cirrus Logic, Inc. Methods and apparatus for the processing of digital signals
RU2143723C1 (en) * 1998-07-29 1999-12-27 Воронежский государственный университет Device for modulo multiplication of numbers

Also Published As

Publication number Publication date
EA033759B1 (en) 2019-11-22

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Legal Events

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MM4A Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s)

Designated state(s): AM AZ KZ KG TJ TM RU