EA201700002A1 - SUMMATOR BY MODULE FOUR - Google Patents
SUMMATOR BY MODULE FOURInfo
- Publication number
- EA201700002A1 EA201700002A1 EA201700002A EA201700002A EA201700002A1 EA 201700002 A1 EA201700002 A1 EA 201700002A1 EA 201700002 A EA201700002 A EA 201700002A EA 201700002 A EA201700002 A EA 201700002A EA 201700002 A1 EA201700002 A1 EA 201700002A1
- Authority
- EA
- Eurasian Patent Office
- Prior art keywords
- adder
- inputs
- mod
- outputs
- values
- Prior art date
Links
Landscapes
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Предполагаемое изобретение относится к области вычислительной техники и микроэлектроники и может быть использовано для построения средств аппаратурного контроля и цифровых устройств, работающих в системе остаточных классов. Сумматор по модулю четыре содержит два элемента СЛОЖЕНИЕ ПО МОДУЛЮ ДВА, мажоритарный элемент с порогом два, элемент И, восемь входов и два выхода. Конструктивная сложность сумматора (по числу входов логических элементов) равна 18. Быстродействие, определяемое глубиной схемы, составляет 2τ, где τ -задержка на один логический элемент. Сумматор выполняет операцию A + B + C + D = S(mod 4). При этом входные операнды A, B, C, Dпредставлены как A=2a+aB=2b+b, C = 2c+ cи D = 2d+d, где a, a, b, b, c, c, d, d∈{0, 1}. Сумматор работает следующим образом. На входы сумматора поступают значения двоичных переменных a, a, b, b, c, c, dd,а на его выходах реализуются логические функции Sи S,которые принимают значения младшего sи старшего sразрядов результата выполнения операции A + B + C + D = S(mod 4), где S = 2s+s.The alleged invention relates to the field of computing and microelectronics, and can be used to build hardware control devices and digital devices operating in the system of residual classes. Modulo four contains two elements: COMPLEX ON MODULE TWO, a majority element with a threshold of two, an AND element, eight inputs and two outputs. The constructive complexity of the adder (according to the number of inputs of logic elements) is 18. The speed, determined by the depth of the circuit, is 2τ, where τ is the delay by one logical element. The adder performs the operation A + B + C + D = S (mod 4). In this case, the input operands A, B, C, D are represented as A = 2a + aB = 2b + b, C = 2c + c and D = 2d + d, where a, a, b, b, c, c, d, d∈ { 0, 1}. The adder works as follows. The inputs of the adder receive the values of the binary variables a, a, b, b, c, c, dd, and its outputs implement the logical functions S and S, which take the values of the lower s and the higher s bits of the result of the operation A + B + C + D = S (mod 4), where S = 2s + s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EA201700002A EA030205B1 (en) | 2016-11-10 | 2016-11-10 | Modulo four adder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EA201700002A EA030205B1 (en) | 2016-11-10 | 2016-11-10 | Modulo four adder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EA201700002A1 true EA201700002A1 (en) | 2018-05-31 |
| EA030205B1 EA030205B1 (en) | 2018-07-31 |
Family
ID=62217537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EA201700002A EA030205B1 (en) | 2016-11-10 | 2016-11-10 | Modulo four adder |
Country Status (1)
| Country | Link |
|---|---|
| EA (1) | EA030205B1 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0238978A1 (en) * | 1986-03-25 | 1987-09-30 | Siemens Aktiengesellschaft | Modulo-2 adder for three input signals |
| RU2012038C1 (en) * | 1992-03-27 | 1994-04-30 | Белорусский государственный университет | Modulo-five adder |
-
2016
- 2016-11-10 EA EA201700002A patent/EA030205B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EA030205B1 (en) | 2018-07-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s) |
Designated state(s): AM AZ KZ KG TJ TM RU |