EA200000462A1 - Арифметическое устройство для работы с целыми числами с многократно увеличенной точностью - Google Patents

Арифметическое устройство для работы с целыми числами с многократно увеличенной точностью

Info

Publication number
EA200000462A1
EA200000462A1 EA200000462A EA200000462A EA200000462A1 EA 200000462 A1 EA200000462 A1 EA 200000462A1 EA 200000462 A EA200000462 A EA 200000462A EA 200000462 A EA200000462 A EA 200000462A EA 200000462 A1 EA200000462 A1 EA 200000462A1
Authority
EA
Eurasian Patent Office
Prior art keywords
large numbers
multiplier
adder
fed
working
Prior art date
Application number
EA200000462A
Other languages
English (en)
Other versions
EA002183B1 (ru
Inventor
Михаэл Сабин
Марк В. Хайзинг
Original Assignee
Атмел Корпорейшн
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Атмел Корпорейшн filed Critical Атмел Корпорейшн
Publication of EA200000462A1 publication Critical patent/EA200000462A1/ru
Publication of EA002183B1 publication Critical patent/EA002183B1/ru

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction

Abstract

(57) Система и метод для выполнения умножения и модульного приведения больших целых чисел. Система включает, по крайней мере, один блок больших чисел (21). Каждый блок больших чисел имеет умножитель (22), сумматор (23) и регистр (24). Первый и второй входные сигналы умножителя подаются на умножитель, а первый и второй входные сигналы сумматора подаются на сумматор. Один выходной сигнал умножителя также подается на сумматор. Множество блоков больших чисел может быть связано в матрицу блоков больших чисел (39), которая включает схему дополнения (35) и регистр-фиксатор (34). Второй выходной сигнал умножителя подается на первый вход сумматора следующего блока больших чисел, причём скорость обработки увеличивается, поскольку к массиву добавляются дополнительные блоки больших чисел.Международная заявка была опубликована вместе с отчетом о международном поиске.
EA200000462A 1997-11-26 1998-11-04 Арифметическое устройство для работы с целыми числами с многократно увеличенной точностью EA002183B1 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/979,803 US6026421A (en) 1997-11-26 1997-11-26 Apparatus for multiprecision integer arithmetic
PCT/US1998/023476 WO1999027437A1 (en) 1997-11-26 1998-11-04 Apparatus for multiprecision integer arithmetic

Publications (2)

Publication Number Publication Date
EA200000462A1 true EA200000462A1 (ru) 2000-12-25
EA002183B1 EA002183B1 (ru) 2002-02-28

Family

ID=25527160

Family Applications (1)

Application Number Title Priority Date Filing Date
EA200000462A EA002183B1 (ru) 1997-11-26 1998-11-04 Арифметическое устройство для работы с целыми числами с многократно увеличенной точностью

Country Status (10)

Country Link
US (2) US6026421A (ru)
EP (2) EP1818809A1 (ru)
JP (2) JP4201980B2 (ru)
CN (1) CN1205538C (ru)
AU (1) AU1379899A (ru)
CA (1) CA2310418C (ru)
DE (1) DE69840871D1 (ru)
EA (1) EA002183B1 (ru)
NO (1) NO20002672L (ru)
WO (1) WO1999027437A1 (ru)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1100291C (zh) * 1997-08-20 2003-01-29 松下电器产业株式会社 数据处理装置
US6963644B1 (en) * 1999-04-07 2005-11-08 Matsushita Electric Industrial Co., Ltd. Multi-word arithmetic device for faster computation of cryptosystem calculations
US6957242B1 (en) * 2000-10-26 2005-10-18 Cypress Semiconductor Corp. Noninterfering multiply-MAC (multiply accumulate) circuit
JP3709553B2 (ja) 2000-12-19 2005-10-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 演算回路および演算方法
TW480436B (en) * 2000-12-21 2002-03-21 Goldkey Technology Corp Modular multiplier and ciphering/deciphering machine using the modular multiplier
JP3950638B2 (ja) * 2001-03-05 2007-08-01 株式会社日立製作所 耐タンパーモジュラ演算処理方法
US7017064B2 (en) * 2001-05-09 2006-03-21 Mosaid Technologies, Inc. Calculating apparatus having a plurality of stages
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7451326B2 (en) * 2002-08-26 2008-11-11 Mosaid Technologies, Inc. Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies
US7386705B2 (en) 2002-08-27 2008-06-10 Mosaid Technologies Inc. Method for allocating processor resources and system for encrypting data
FR2853425B1 (fr) * 2003-04-07 2006-01-13 Atmel Corp Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur
US7243118B2 (en) * 2003-07-30 2007-07-10 Broadcom Corporation Method and apparatus for efficient derivation of modulo arithmetic for frequency selection
US7346482B1 (en) 2005-03-08 2008-03-18 Xilinx, Inc. Shared memory for co-simulation
US7343572B1 (en) 2005-03-31 2008-03-11 Xilinx, Inc. Vector interface to shared memory in simulating a circuit design
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
EP1975906B1 (en) * 2006-01-13 2012-07-04 Fujitsu Ltd. Montgomery s algorithm multiplication remainder calculator
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
CN101271570B (zh) * 2008-05-07 2011-08-17 威盛电子股份有限公司 用于绘图处理单元中的大整数乘法运算的装置和方法
JP5097138B2 (ja) * 2009-01-15 2012-12-12 シャープ株式会社 モンゴメリ乗算のための演算回路及び暗号回路
EP2276194B1 (en) * 2009-07-17 2014-11-26 Certicom Corp. System and method for reducing the computation and storage requirements for a Montgomery-style reduction
CN103888246A (zh) * 2014-03-10 2014-06-25 深圳华视微电子有限公司 低功耗小面积的数据处理方法及其数据处理装置
GB2537942B (en) * 2015-05-01 2017-06-14 Imagination Tech Ltd Fault tolerant processor for real-time systems
CN109190414B (zh) * 2018-08-09 2021-06-15 宁波大学 一种用于乘法器的全同态混淆方法
CN109634558B (zh) * 2018-12-12 2020-01-14 上海燧原科技有限公司 可编程的混合精度运算单元
CN110543291A (zh) * 2019-06-11 2019-12-06 南通大学 有限域大整数乘法器及基于ssa算法的大整数乘法的实现方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215617A (en) * 1976-11-22 1980-08-05 The Board Of Trustees Of Leland Stanford Junior University Musical instrument and method for generating musical sound
US4608634A (en) * 1982-02-22 1986-08-26 Texas Instruments Incorporated Microcomputer with offset in store-accumulator operations
JPS6297060A (ja) * 1985-10-23 1987-05-06 Mitsubishi Electric Corp デイジタルシグナルプロセツサ
US5278781A (en) * 1987-11-12 1994-01-11 Matsushita Electric Industrial Co., Ltd. Digital signal processing system
US5194681A (en) * 1989-09-22 1993-03-16 Yamaha Corporation Musical tone generating apparatus
US5245564A (en) * 1991-05-10 1993-09-14 Weitek Corporation Apparatus for multiplying operands
ATE183315T1 (de) * 1991-09-05 1999-08-15 Canon Kk Verfahren und gerät zum verschlüsseln und entschlüsseln von kommunikationsdaten
JPH0612229A (ja) * 1992-06-10 1994-01-21 Nec Corp 乗累算回路
US5321751A (en) 1993-02-18 1994-06-14 Eastman Kodak Company Method and apparatus for credit card verification
US5661673A (en) * 1995-08-31 1997-08-26 National Semiconductor Corporation Power efficient booth multiplier using clock gating

Also Published As

Publication number Publication date
AU1379899A (en) 1999-06-15
NO20002672D0 (no) 2000-05-25
EA002183B1 (ru) 2002-02-28
EP1818809A1 (en) 2007-08-15
EP1032873B1 (en) 2009-06-03
CA2310418C (en) 2002-10-22
JP2001524698A (ja) 2001-12-04
WO1999027437A1 (en) 1999-06-03
US6269383B1 (en) 2001-07-31
EP1032873A4 (en) 2005-10-12
JP2002099208A (ja) 2002-04-05
DE69840871D1 (de) 2009-07-16
CA2310418A1 (en) 1999-06-03
US6026421A (en) 2000-02-15
NO20002672L (no) 2000-07-26
EP1032873A1 (en) 2000-09-06
CN1279781A (zh) 2001-01-10
JP4201980B2 (ja) 2008-12-24
CN1205538C (zh) 2005-06-08

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MM4A Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s)

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MM4A Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s)

Designated state(s): BY RU